drivers/staging/r8188eu/hal/rtl8188e_rf6052.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4 /******************************************************************************
   5  *
   6  *
   7  * Module:      rtl8192c_rf6052.c       ( Source C File)
   8  *
   9  * Note:        Provide RF 6052 series relative API.
  10  *
  11  * Function:
  12  *
  13  * Export:
  14  *
  15  * Abbrev:
  16  *
  17  * History:
  18  * Data                 Who             Remark
  19  *
  20  * 09/25/2008   MHC             Create initial version.
  21  * 11/05/2008   MHC             Add API for tw power setting.
  22  *
  23  *
  24 ******************************************************************************/
  25
  26 #define _RTL8188E_RF6052_C_
  27
  28 #include "../include/osdep_service.h"
  29 #include "../include/drv_types.h"
  30 #include "../include/rtl8188e_hal.h"
  31
  32 /*---------------------------Define Local Constant---------------------------*/
  33 /*  Define local structure for debug!!!!! */
  34 struct rf_shadow {
  35         /*  Shadow register value */
  36         u32 Value;
  37         /*  Compare or not flag */
  38         u8 Compare;
  39         /*  Record If it had ever modified unpredicted */
  40         u8 ErrorOrNot;
  41         /*  Recorver Flag */
  42         u8 Recorver;
  43         /*  */
  44         u8 Driver_Write;
  45 };
  46
  47 /*---------------------------Define Local Constant---------------------------*/
  48
  49 /*------------------------Define global variable-----------------------------*/
  50
  51 /*------------------------Define local variable------------------------------*/
  52
  53 /*-----------------------------------------------------------------------------
  54  * Function:    RF_ChangeTxPath
  55  *
  56  * Overview:    For RL6052, we must change some RF settign for 1T or 2T.
  57  *
  58  * Input:               u16 DataRate            0x80-8f, 0x90-9f
  59  *
  60  * Output:      NONE
  61  *
  62  * Return:      NONE
  63  *
  64  * Revised History:
  65  * When                 Who             Remark
  66  * 09/25/2008   MHC             Create Version 0.
  67  *                                              Firmwaer support the utility later.
  68  *
  69  *---------------------------------------------------------------------------*/
  70 void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate)
  71 {
  72 /*  We do not support gain table change inACUT now !!!! Delete later !!! */
  73 }       /* RF_ChangeTxPath */
  74
  75 /*-----------------------------------------------------------------------------
  76  * Function:    PHY_RF6052SetBandwidth()
  77  *
  78  * Overview:    This function is called by SetBWModeCallback8190Pci() only
  79  *
  80  * Input:       struct adapter *Adapter
  81  *                      WIRELESS_BANDWIDTH_E    Bandwidth       20M or 40M
  82  *
  83  * Output:      NONE
  84  *
  85  * Return:      NONE
  86  *
  87  * Note:                For RF type 0222D
  88  *---------------------------------------------------------------------------*/
  89 void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
  90                                      enum ht_channel_width Bandwidth)
  91 {
  92         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
  93
  94         switch (Bandwidth) {
  95         case HT_CHANNEL_WIDTH_20:
  96                 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
  97                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
  98                 break;
  99         case HT_CHANNEL_WIDTH_40:
 100                 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
 101                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
 102                 break;
 103         default:
 104                 break;
 105         }
 106 }
 107
 108 /*-----------------------------------------------------------------------------
 109  * Function:    PHY_RF6052SetCckTxPower
 110  *
 111  * Overview:
 112  *
 113  * Input:       NONE
 114  *
 115  * Output:      NONE
 116  *
 117  * Return:      NONE
 118  *
 119  * Revised History:
 120  * When                 Who             Remark
 121  * 11/05/2008   MHC             Simulate 8192series..
 122  *
 123  *---------------------------------------------------------------------------*/
 124
 125 void
 126 rtl8188e_PHY_RF6052SetCckTxPower(
 127                 struct adapter *Adapter,
 128                 u8 *pPowerlevel)
 129 {
 130         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 131         struct dm_priv *pdmpriv = &pHalData->dmpriv;
 132         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
 133         u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
 134         bool TurboScanOff = false;
 135         u8 idx1, idx2;
 136         u8 *ptr;
 137         u8 direction;
 138         /* FOR CE ,must disable turbo scan */
 139         TurboScanOff = true;
 140
 141         if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
 142                 TxAGC[RF_PATH_A] = 0x3f3f3f3f;
 143                 TxAGC[RF_PATH_B] = 0x3f3f3f3f;
 144
 145                 TurboScanOff = true;/* disable turbo scan */
 146
 147                 if (TurboScanOff) {
 148                         for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
 149                                 TxAGC[idx1] =
 150                                         pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
 151                                         (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
 152                                 /*  2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
 153                                 if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
 154                                         TxAGC[idx1] = 0x20;
 155                         }
 156                 }
 157         } else {
 158                 /* Driver dynamic Tx power shall not affect Tx power.
 159                  * It shall be determined by power training mechanism.
 160 i                *  Currently, we cannot fully disable driver dynamic
 161                  * tx power mechanism because it is referenced by BT
 162                  * coexist mechanism.
 163                  * In the future, two mechanism shall be separated from
 164                  * each other and maintained independently. */
 165                 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
 166                         TxAGC[RF_PATH_A] = 0x10101010;
 167                         TxAGC[RF_PATH_B] = 0x10101010;
 168                 } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
 169                         TxAGC[RF_PATH_A] = 0x00000000;
 170                         TxAGC[RF_PATH_B] = 0x00000000;
 171                 } else {
 172                         for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
 173                                 TxAGC[idx1] =
 174                                         pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
 175                                         (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
 176                         }
 177                         if (pHalData->EEPROMRegulatory == 0) {
 178                                 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
 179                                                 (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
 180                                 TxAGC[RF_PATH_A] += tmpval;
 181
 182                                 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
 183                                                 (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
 184                                 TxAGC[RF_PATH_B] += tmpval;
 185                         }
 186                 }
 187         }
 188         for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
 189                 ptr = (u8 *)(&(TxAGC[idx1]));
 190                 for (idx2 = 0; idx2 < 4; idx2++) {
 191                         if (*ptr > RF6052_MAX_TX_PWR)
 192                                 *ptr = RF6052_MAX_TX_PWR;
 193                         ptr++;
 194                 }
 195         }
 196         ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
 197
 198         if (direction == 1) {
 199                 /*  Increase TX power */
 200                 TxAGC[0] += pwrtrac_value;
 201                 TxAGC[1] += pwrtrac_value;
 202         } else if (direction == 2) {
 203                 /*  Decrease TX power */
 204                 TxAGC[0] -=  pwrtrac_value;
 205                 TxAGC[1] -=  pwrtrac_value;
 206         }
 207
 208         /*  rf-A cck tx power */
 209         tmpval = TxAGC[RF_PATH_A]&0xff;
 210         PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
 211         tmpval = TxAGC[RF_PATH_A]>>8;
 212         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 213
 214         /*  rf-B cck tx power */
 215         tmpval = TxAGC[RF_PATH_B]>>24;
 216         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
 217         tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
 218         PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
 219 }       /* PHY_RF6052SetCckTxPower */
 220
 221 /*  */
 222 /*  powerbase0 for OFDM rates */
 223 /*  powerbase1 for HT MCS rates */
 224 /*  */
 225 static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
 226                             u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
 227 {
 228         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 229         u32 powerBase0, powerBase1;
 230         u8 i, powerlevel[2];
 231
 232         for (i = 0; i < 2; i++) {
 233                 powerBase0 = pPowerLevelOFDM[i];
 234
 235                 powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
 236                 *(OfdmBase+i) = powerBase0;
 237         }
 238         for (i = 0; i < pHalData->NumTotalRFPath; i++) {
 239                 /* Check HT20 to HT40 diff */
 240                 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 241                         powerlevel[i] = pPowerLevelBW20[i];
 242                 else
 243                         powerlevel[i] = pPowerLevelBW40[i];
 244                 powerBase1 = powerlevel[i];
 245                 powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
 246                 *(MCSBase+i) = powerBase1;
 247         }
 248 }
 249 static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
 250                                     u8 index, u32 *powerBase0, u32 *powerBase1,
 251                                     u32 *pOutWriteVal)
 252 {
 253         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 254         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
 255         u8      i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
 256         s8      pwr_diff = 0;
 257         u32     writeVal, customer_limit, rf;
 258         u8      Regulatory = pHalData->EEPROMRegulatory;
 259
 260         /*  Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
 261
 262         for (rf = 0; rf < 2; rf++) {
 263                 switch (Regulatory) {
 264                 case 0: /*  Realtek better performance */
 265                                 /*  increase power diff defined by Realtek for large power */
 266                         chnlGroup = 0;
 267                         writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
 268                                 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 269                         break;
 270                 case 1: /*  Realtek regulatory */
 271                         /*  increase power diff defined by Realtek for regulatory */
 272                         if (pHalData->pwrGroupCnt == 1)
 273                                 chnlGroup = 0;
 274                         if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
 275                                 if (Channel < 3)                        /*  Channel 1-2 */
 276                                         chnlGroup = 0;
 277                                 else if (Channel < 6)           /*  Channel 3-5 */
 278                                         chnlGroup = 1;
 279                                 else     if (Channel < 9)               /*  Channel 6-8 */
 280                                         chnlGroup = 2;
 281                                 else if (Channel < 12)          /*  Channel 9-11 */
 282                                         chnlGroup = 3;
 283                                 else if (Channel < 14)          /*  Channel 12-13 */
 284                                         chnlGroup = 4;
 285                                 else if (Channel == 14)         /*  Channel 14 */
 286                                         chnlGroup = 5;
 287                         }
 288                         writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
 289                                         ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 290                         break;
 291                 case 2: /*  Better regulatory */
 292                                 /*  don't increase any power diff */
 293                         writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 294                         break;
 295                 case 3: /*  Customer defined power diff. */
 296                                 /*  increase power diff defined by customer. */
 297                         chnlGroup = 0;
 298
 299                         if (index < 2)
 300                                 pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
 301                         else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 302                                 pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
 303
 304                         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
 305                                 customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
 306                         else
 307                                 customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
 308
 309                         if (pwr_diff >= customer_pwr_limit)
 310                                 pwr_diff = 0;
 311                         else
 312                                 pwr_diff = customer_pwr_limit - pwr_diff;
 313
 314                         for (i = 0; i < 4; i++) {
 315                                 pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8));
 316
 317                                 if (pwr_diff_limit[i] > pwr_diff)
 318                                         pwr_diff_limit[i] = pwr_diff;
 319                         }
 320                         customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
 321                                          (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
 322                         writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 323                         break;
 324                 default:
 325                         chnlGroup = 0;
 326                         writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
 327                                         ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 328                         break;
 329                 }
 330 /*  20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
 331 /*  Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
 332 /*  In the future, two mechanism shall be separated from each other and maintained independently. Thanks for Lanhsin's reminder. */
 333                 /* 92d do not need this */
 334                 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
 335                         writeVal = 0x14141414;
 336                 else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
 337                         writeVal = 0x00000000;
 338
 339                 /*  20100628 Joseph: High power mode for BT-Coexist mechanism. */
 340                 /*  This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
 341                 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
 342                         writeVal = writeVal - 0x06060606;
 343                 *(pOutWriteVal+rf) = writeVal;
 344         }
 345 }
 346 static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
 347 {
 348         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 349         u16 regoffset_a[6] = {
 350                 rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
 351                 rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
 352                 rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
 353         u16 regoffset_b[6] = {
 354                 rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
 355                 rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
 356                 rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
 357         u8 i, rf, pwr_val[4];
 358         u32 writeVal;
 359         u16 regoffset;
 360
 361         for (rf = 0; rf < 2; rf++) {
 362                 writeVal = pValue[rf];
 363                 for (i = 0; i < 4; i++) {
 364                         pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
 365                         if (pwr_val[i]  > RF6052_MAX_TX_PWR)
 366                                 pwr_val[i]  = RF6052_MAX_TX_PWR;
 367                 }
 368                 writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0];
 369
 370                 if (rf == 0)
 371                         regoffset = regoffset_a[index];
 372                 else
 373                         regoffset = regoffset_b[index];
 374
 375                 PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
 376
 377                 /*  201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
 378                 if (((pHalData->rf_type == RF_2T2R) &&
 379                      (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) ||
 380                     ((pHalData->rf_type != RF_2T2R) &&
 381                      (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) {
 382                         writeVal = pwr_val[3];
 383                         if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
 384                                 regoffset = 0xc90;
 385                         if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
 386                                 regoffset = 0xc98;
 387                         for (i = 0; i < 3; i++) {
 388                                 if (i != 2)
 389                                         writeVal = (writeVal > 8) ? (writeVal-8) : 0;
 390                                 else
 391                                         writeVal = (writeVal > 6) ? (writeVal-6) : 0;
 392                                 rtw_write8(Adapter, (u32)(regoffset+i), (u8)writeVal);
 393                         }
 394                 }
 395         }
 396 }
 397
 398 /*-----------------------------------------------------------------------------
 399  * Function:    PHY_RF6052SetOFDMTxPower
 400  *
 401  * Overview:    For legacy and HY OFDM, we must read EEPROM TX power index for
 402  *                      different channel and read original value in TX power register area from
 403  *                      0xe00. We increase offset and original value to be correct tx pwr.
 404  *
 405  * Input:       NONE
 406  *
 407  * Output:      NONE
 408  *
 409  * Return:      NONE
 410  *
 411  * Revised History:
 412  * When                 Who             Remark
 413  * 11/05/2008   MHC             Simulate 8192 series method.
 414  * 01/06/2009   MHC             1. Prevent Path B tx power overflow or underflow dure to
 415  *                                              A/B pwr difference or legacy/HT pwr diff.
 416  *                                              2. We concern with path B legacy/HT OFDM difference.
 417  * 01/22/2009   MHC             Support new EPRO format from SD3.
 418  *
 419  *---------------------------------------------------------------------------*/
 420
 421 void
 422 rtl8188e_PHY_RF6052SetOFDMTxPower(
 423                 struct adapter *Adapter,
 424                 u8 *pPowerLevelOFDM,
 425                 u8 *pPowerLevelBW20,
 426                 u8 *pPowerLevelBW40,
 427                 u8 Channel)
 428 {
 429         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 430         u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
 431         u8 direction;
 432         u8 index = 0;
 433
 434         getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
 435
 436         /*  2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
 437         /*  This is ued to fix unstable power tracking mode. */
 438         ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
 439
 440         for (index = 0; index < 6; index++) {
 441                 get_rx_power_val_by_reg(Adapter, Channel, index,
 442                                         &powerBase0[0], &powerBase1[0],
 443                                         &writeVal[0]);
 444
 445                 if (direction == 1) {
 446                         writeVal[0] += pwrtrac_value;
 447                         writeVal[1] += pwrtrac_value;
 448                 } else if (direction == 2) {
 449                         writeVal[0] -= pwrtrac_value;
 450                         writeVal[1] -= pwrtrac_value;
 451                 }
 452                 writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
 453         }
 454 }
 455
 456 static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
 457 {
 458         struct bb_reg_def *pPhyReg;
 459         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 460         u32 u4RegValue = 0;
 461         u8 eRFPath;
 462         int rtStatus = _SUCCESS;
 463
 464         /* 3----------------------------------------------------------------- */
 465         /* 3 <2> Initialize RF */
 466         /* 3----------------------------------------------------------------- */
 467         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
 468                 pPhyReg = &pHalData->PHYRegDef[eRFPath];
 469
 470                 /*----Store original RFENV control type----*/
 471                 switch (eRFPath) {
 472                 case RF_PATH_A:
 473                 case RF_PATH_C:
 474                         u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
 475                         break;
 476                 case RF_PATH_B:
 477                 case RF_PATH_D:
 478                         u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
 479                         break;
 480                 }
 481                 /*----Set RF_ENV enable----*/
 482                 PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 483                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 484
 485                 /*----Set RF_ENV output high----*/
 486                 PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 487                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 488
 489                 /* Set bit number of Address and Data for RF register */
 490                 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  /*  Set 1 to 4 bits for 8255 */
 491                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 492
 493                 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     /*  Set 0 to 12  bits for 8255 */
 494                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 495
 496                 /*----Initialize RF fom connfiguration file----*/
 497                 switch (eRFPath) {
 498                 case RF_PATH_A:
 499                         if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
 500                                 rtStatus = _FAIL;
 501                         break;
 502                 case RF_PATH_B:
 503                 if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
 504                                 rtStatus = _FAIL;
 505                         break;
 506                 case RF_PATH_C:
 507                         break;
 508                 case RF_PATH_D:
 509                         break;
 510                 }
 511                 /*----Restore RFENV control type----*/;
 512                 switch (eRFPath) {
 513                 case RF_PATH_A:
 514                 case RF_PATH_C:
 515                         PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 516                         break;
 517                 case RF_PATH_B:
 518                 case RF_PATH_D:
 519                         PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
 520                         break;
 521                 }
 522                 if (rtStatus != _SUCCESS)
 523                         goto phy_RF6052_Config_ParaFile_Fail;
 524         }
 525         return rtStatus;
 526
 527 phy_RF6052_Config_ParaFile_Fail:
 528         return rtStatus;
 529 }
 530
 531 int PHY_RF6052_Config8188E(struct adapter *Adapter)
 532 {
 533         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 534         int rtStatus = _SUCCESS;
 535
 536         /*  */
 537         /*  Initialize general global value */
 538         /*  */
 539         /*  TODO: Extend RF_PATH_C and RF_PATH_D in the future */
 540         if (pHalData->rf_type == RF_1T1R)
 541                 pHalData->NumTotalRFPath = 1;
 542         else
 543                 pHalData->NumTotalRFPath = 2;
 544
 545         /*  */
 546         /*  Config BB and RF */
 547         /*  */
 548         rtStatus = phy_RF6052_Config_ParaFile(Adapter);
 549         return rtStatus;
 550 }