drivers/staging/r8188eu/hal/rtl8188e_rf6052.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 /******************************************************************************
  21  *
  22  *
  23  * Module:      rtl8192c_rf6052.c       ( Source C File)
  24  *
  25  * Note:        Provide RF 6052 series relative API.
  26  *
  27  * Function:
  28  *
  29  * Export:
  30  *
  31  * Abbrev:
  32  *
  33  * History:
  34  * Data                 Who             Remark
  35  *
  36  * 09/25/2008   MHC             Create initial version.
  37  * 11/05/2008   MHC             Add API for tw power setting.
  38  *
  39  *
  40 ******************************************************************************/
  41
  42 #define _RTL8188E_RF6052_C_
  43
  44 #include <osdep_service.h>
  45 #include <drv_types.h>
  46
  47 #include <rtl8188e_hal.h>
  48
  49 /*---------------------------Define Local Constant---------------------------*/
  50 /*  Define local structure for debug!!!!! */
  51 struct rf_shadow {
  52         /*  Shadow register value */
  53         u32 Value;
  54         /*  Compare or not flag */
  55         u8 Compare;
  56         /*  Record If it had ever modified unpredicted */
  57         u8 ErrorOrNot;
  58         /*  Recorver Flag */
  59         u8 Recorver;
  60         /*  */
  61         u8 Driver_Write;
  62 };
  63
  64 /*---------------------------Define Local Constant---------------------------*/
  65
  66 /*------------------------Define global variable-----------------------------*/
  67
  68 /*------------------------Define local variable------------------------------*/
  69
  70 /*-----------------------------------------------------------------------------
  71  * Function:    RF_ChangeTxPath
  72  *
  73  * Overview:    For RL6052, we must change some RF settign for 1T or 2T.
  74  *
  75  * Input:               u16 DataRate            0x80-8f, 0x90-9f
  76  *
  77  * Output:      NONE
  78  *
  79  * Return:      NONE
  80  *
  81  * Revised History:
  82  * When                 Who             Remark
  83  * 09/25/2008   MHC             Create Version 0.
  84  *                                              Firmwaer support the utility later.
  85  *
  86  *---------------------------------------------------------------------------*/
  87 void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate)
  88 {
  89 /*  We do not support gain table change inACUT now !!!! Delete later !!! */
  90 }       /* RF_ChangeTxPath */
  91
  92 /*-----------------------------------------------------------------------------
  93  * Function:    PHY_RF6052SetBandwidth()
  94  *
  95  * Overview:    This function is called by SetBWModeCallback8190Pci() only
  96  *
  97  * Input:       struct adapter *Adapter
  98  *                      WIRELESS_BANDWIDTH_E    Bandwidth       20M or 40M
  99  *
 100  * Output:      NONE
 101  *
 102  * Return:      NONE
 103  *
 104  * Note:                For RF type 0222D
 105  *---------------------------------------------------------------------------*/
 106 void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
 107                                      enum ht_channel_width Bandwidth)
 108 {
 109         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 110
 111         switch (Bandwidth) {
 112         case HT_CHANNEL_WIDTH_20:
 113                 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
 114                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
 115                 break;
 116         case HT_CHANNEL_WIDTH_40:
 117                 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
 118                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
 119                 break;
 120         default:
 121                 break;
 122         }
 123 }
 124
 125 /*-----------------------------------------------------------------------------
 126  * Function:    PHY_RF6052SetCckTxPower
 127  *
 128  * Overview:
 129  *
 130  * Input:       NONE
 131  *
 132  * Output:      NONE
 133  *
 134  * Return:      NONE
 135  *
 136  * Revised History:
 137  * When                 Who             Remark
 138  * 11/05/2008   MHC             Simulate 8192series..
 139  *
 140  *---------------------------------------------------------------------------*/
 141
 142 void
 143 rtl8188e_PHY_RF6052SetCckTxPower(
 144                 struct adapter *Adapter,
 145                 u8 *pPowerlevel)
 146 {
 147         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 148         struct dm_priv *pdmpriv = &pHalData->dmpriv;
 149         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
 150         u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
 151         bool TurboScanOff = false;
 152         u8 idx1, idx2;
 153         u8 *ptr;
 154         u8 direction;
 155         /* FOR CE ,must disable turbo scan */
 156         TurboScanOff = true;
 157
 158         if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
 159                 TxAGC[RF_PATH_A] = 0x3f3f3f3f;
 160                 TxAGC[RF_PATH_B] = 0x3f3f3f3f;
 161
 162                 TurboScanOff = true;/* disable turbo scan */
 163
 164                 if (TurboScanOff) {
 165                         for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
 166                                 TxAGC[idx1] =
 167                                         pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
 168                                         (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
 169                                 /*  2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
 170                                 if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
 171                                         TxAGC[idx1] = 0x20;
 172                         }
 173                 }
 174         } else {
 175                 /* Driver dynamic Tx power shall not affect Tx power.
 176                  * It shall be determined by power training mechanism.
 177 i                *  Currently, we cannot fully disable driver dynamic
 178                  * tx power mechanism because it is referenced by BT
 179                  * coexist mechanism.
 180                  * In the future, two mechanism shall be separated from
 181                  * each other and maintained independently. */
 182                 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
 183                         TxAGC[RF_PATH_A] = 0x10101010;
 184                         TxAGC[RF_PATH_B] = 0x10101010;
 185                 } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
 186                         TxAGC[RF_PATH_A] = 0x00000000;
 187                         TxAGC[RF_PATH_B] = 0x00000000;
 188                 } else {
 189                         for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
 190                                 TxAGC[idx1] =
 191                                         pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
 192                                         (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
 193                         }
 194                         if (pHalData->EEPROMRegulatory == 0) {
 195                                 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
 196                                                 (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
 197                                 TxAGC[RF_PATH_A] += tmpval;
 198
 199                                 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
 200                                                 (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
 201                                 TxAGC[RF_PATH_B] += tmpval;
 202                         }
 203                 }
 204         }
 205         for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
 206                 ptr = (u8 *)(&(TxAGC[idx1]));
 207                 for (idx2 = 0; idx2 < 4; idx2++) {
 208                         if (*ptr > RF6052_MAX_TX_PWR)
 209                                 *ptr = RF6052_MAX_TX_PWR;
 210                         ptr++;
 211                 }
 212         }
 213         ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
 214
 215         if (direction == 1) {
 216                 /*  Increase TX power */
 217                 TxAGC[0] += pwrtrac_value;
 218                 TxAGC[1] += pwrtrac_value;
 219         } else if (direction == 2) {
 220                 /*  Decrease TX power */
 221                 TxAGC[0] -=  pwrtrac_value;
 222                 TxAGC[1] -=  pwrtrac_value;
 223         }
 224
 225         /*  rf-A cck tx power */
 226         tmpval = TxAGC[RF_PATH_A]&0xff;
 227         PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
 228         tmpval = TxAGC[RF_PATH_A]>>8;
 229         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 230
 231         /*  rf-B cck tx power */
 232         tmpval = TxAGC[RF_PATH_B]>>24;
 233         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
 234         tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
 235         PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
 236 }       /* PHY_RF6052SetCckTxPower */
 237
 238 /*  */
 239 /*  powerbase0 for OFDM rates */
 240 /*  powerbase1 for HT MCS rates */
 241 /*  */
 242 static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
 243                             u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
 244 {
 245         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 246         u32 powerBase0, powerBase1;
 247         u8 i, powerlevel[2];
 248
 249         for (i = 0; i < 2; i++) {
 250                 powerBase0 = pPowerLevelOFDM[i];
 251
 252                 powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
 253                 *(OfdmBase+i) = powerBase0;
 254         }
 255         for (i = 0; i < pHalData->NumTotalRFPath; i++) {
 256                 /* Check HT20 to HT40 diff */
 257                 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 258                         powerlevel[i] = pPowerLevelBW20[i];
 259                 else
 260                         powerlevel[i] = pPowerLevelBW40[i];
 261                 powerBase1 = powerlevel[i];
 262                 powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
 263                 *(MCSBase+i) = powerBase1;
 264         }
 265 }
 266 static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
 267                                     u8 index, u32 *powerBase0, u32 *powerBase1,
 268                                     u32 *pOutWriteVal)
 269 {
 270         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 271         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
 272         u8      i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
 273         s8      pwr_diff = 0;
 274         u32     writeVal, customer_limit, rf;
 275         u8      Regulatory = pHalData->EEPROMRegulatory;
 276
 277         /*  Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
 278
 279         for (rf = 0; rf < 2; rf++) {
 280                 switch (Regulatory) {
 281                 case 0: /*  Realtek better performance */
 282                                 /*  increase power diff defined by Realtek for large power */
 283                         chnlGroup = 0;
 284                         writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
 285                                 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 286                         break;
 287                 case 1: /*  Realtek regulatory */
 288                         /*  increase power diff defined by Realtek for regulatory */
 289                         if (pHalData->pwrGroupCnt == 1)
 290                                 chnlGroup = 0;
 291                         if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
 292                                 if (Channel < 3)                        /*  Channel 1-2 */
 293                                         chnlGroup = 0;
 294                                 else if (Channel < 6)           /*  Channel 3-5 */
 295                                         chnlGroup = 1;
 296                                 else     if (Channel < 9)               /*  Channel 6-8 */
 297                                         chnlGroup = 2;
 298                                 else if (Channel < 12)          /*  Channel 9-11 */
 299                                         chnlGroup = 3;
 300                                 else if (Channel < 14)          /*  Channel 12-13 */
 301                                         chnlGroup = 4;
 302                                 else if (Channel == 14)         /*  Channel 14 */
 303                                         chnlGroup = 5;
 304                         }
 305                         writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
 306                                         ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 307                         break;
 308                 case 2: /*  Better regulatory */
 309                                 /*  don't increase any power diff */
 310                         writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 311                         break;
 312                 case 3: /*  Customer defined power diff. */
 313                                 /*  increase power diff defined by customer. */
 314                         chnlGroup = 0;
 315
 316                         if (index < 2)
 317                                 pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
 318                         else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 319                                 pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
 320
 321                         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
 322                                 customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
 323                         else
 324                                 customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
 325
 326                         if (pwr_diff >= customer_pwr_limit)
 327                                 pwr_diff = 0;
 328                         else
 329                                 pwr_diff = customer_pwr_limit - pwr_diff;
 330
 331                         for (i = 0; i < 4; i++) {
 332                                 pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8));
 333
 334                                 if (pwr_diff_limit[i] > pwr_diff)
 335                                         pwr_diff_limit[i] = pwr_diff;
 336                         }
 337                         customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
 338                                          (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
 339                         writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 340                         break;
 341                 default:
 342                         chnlGroup = 0;
 343                         writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
 344                                         ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 345                         break;
 346                 }
 347 /*  20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
 348 /*  Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
 349 /*  In the future, two mechanism shall be separated from each other and maintained independently. Thanks for Lanhsin's reminder. */
 350                 /* 92d do not need this */
 351                 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
 352                         writeVal = 0x14141414;
 353                 else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
 354                         writeVal = 0x00000000;
 355
 356                 /*  20100628 Joseph: High power mode for BT-Coexist mechanism. */
 357                 /*  This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
 358                 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
 359                         writeVal = writeVal - 0x06060606;
 360                 else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
 361                         writeVal = writeVal;
 362                 *(pOutWriteVal+rf) = writeVal;
 363         }
 364 }
 365 static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
 366 {
 367         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 368         u16 regoffset_a[6] = {
 369                 rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
 370                 rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
 371                 rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
 372         u16 regoffset_b[6] = {
 373                 rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
 374                 rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
 375                 rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
 376         u8 i, rf, pwr_val[4];
 377         u32 writeVal;
 378         u16 regoffset;
 379
 380         for (rf = 0; rf < 2; rf++) {
 381                 writeVal = pValue[rf];
 382                 for (i = 0; i < 4; i++) {
 383                         pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
 384                         if (pwr_val[i]  > RF6052_MAX_TX_PWR)
 385                                 pwr_val[i]  = RF6052_MAX_TX_PWR;
 386                 }
 387                 writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0];
 388
 389                 if (rf == 0)
 390                         regoffset = regoffset_a[index];
 391                 else
 392                         regoffset = regoffset_b[index];
 393
 394                 PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
 395
 396                 /*  201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
 397                 if (((pHalData->rf_type == RF_2T2R) &&
 398                      (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) ||
 399                     ((pHalData->rf_type != RF_2T2R) &&
 400                      (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) {
 401                         writeVal = pwr_val[3];
 402                         if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
 403                                 regoffset = 0xc90;
 404                         if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
 405                                 regoffset = 0xc98;
 406                         for (i = 0; i < 3; i++) {
 407                                 if (i != 2)
 408                                         writeVal = (writeVal > 8) ? (writeVal-8) : 0;
 409                                 else
 410                                         writeVal = (writeVal > 6) ? (writeVal-6) : 0;
 411                                 rtw_write8(Adapter, (u32)(regoffset+i), (u8)writeVal);
 412                         }
 413                 }
 414         }
 415 }
 416
 417 /*-----------------------------------------------------------------------------
 418  * Function:    PHY_RF6052SetOFDMTxPower
 419  *
 420  * Overview:    For legacy and HY OFDM, we must read EEPROM TX power index for
 421  *                      different channel and read original value in TX power register area from
 422  *                      0xe00. We increase offset and original value to be correct tx pwr.
 423  *
 424  * Input:       NONE
 425  *
 426  * Output:      NONE
 427  *
 428  * Return:      NONE
 429  *
 430  * Revised History:
 431  * When                 Who             Remark
 432  * 11/05/2008   MHC             Simulate 8192 series method.
 433  * 01/06/2009   MHC             1. Prevent Path B tx power overflow or underflow dure to
 434  *                                              A/B pwr difference or legacy/HT pwr diff.
 435  *                                              2. We concern with path B legacy/HT OFDM difference.
 436  * 01/22/2009   MHC             Support new EPRO format from SD3.
 437  *
 438  *---------------------------------------------------------------------------*/
 439
 440 void
 441 rtl8188e_PHY_RF6052SetOFDMTxPower(
 442                 struct adapter *Adapter,
 443                 u8 *pPowerLevelOFDM,
 444                 u8 *pPowerLevelBW20,
 445                 u8 *pPowerLevelBW40,
 446                 u8 Channel)
 447 {
 448         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 449         u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
 450         u8 direction;
 451         u8 index = 0;
 452
 453         getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
 454
 455         /*  2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
 456         /*  This is ued to fix unstable power tracking mode. */
 457         ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
 458
 459         for (index = 0; index < 6; index++) {
 460                 get_rx_power_val_by_reg(Adapter, Channel, index,
 461                                         &powerBase0[0], &powerBase1[0],
 462                                         &writeVal[0]);
 463
 464                 if (direction == 1) {
 465                         writeVal[0] += pwrtrac_value;
 466                         writeVal[1] += pwrtrac_value;
 467                 } else if (direction == 2) {
 468                         writeVal[0] -= pwrtrac_value;
 469                         writeVal[1] -= pwrtrac_value;
 470                 }
 471                 writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
 472         }
 473 }
 474
 475 static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
 476 {
 477         struct bb_reg_def *pPhyReg;
 478         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 479         u32 u4RegValue = 0;
 480         u8 eRFPath;
 481         int rtStatus = _SUCCESS;
 482
 483         /* 3----------------------------------------------------------------- */
 484         /* 3 <2> Initialize RF */
 485         /* 3----------------------------------------------------------------- */
 486         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
 487                 pPhyReg = &pHalData->PHYRegDef[eRFPath];
 488
 489                 /*----Store original RFENV control type----*/
 490                 switch (eRFPath) {
 491                 case RF_PATH_A:
 492                 case RF_PATH_C:
 493                         u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
 494                         break;
 495                 case RF_PATH_B:
 496                 case RF_PATH_D:
 497                         u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
 498                         break;
 499                 }
 500                 /*----Set RF_ENV enable----*/
 501                 PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 502                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 503
 504                 /*----Set RF_ENV output high----*/
 505                 PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 506                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 507
 508                 /* Set bit number of Address and Data for RF register */
 509                 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  /*  Set 1 to 4 bits for 8255 */
 510                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 511
 512                 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     /*  Set 0 to 12  bits for 8255 */
 513                 rtw_udelay_os(1);/* PlatformStallExecution(1); */
 514
 515                 /*----Initialize RF fom connfiguration file----*/
 516                 switch (eRFPath) {
 517                 case RF_PATH_A:
 518                         if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
 519                                 rtStatus = _FAIL;
 520                         break;
 521                 case RF_PATH_B:
 522                 if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
 523                                 rtStatus = _FAIL;
 524                         break;
 525                 case RF_PATH_C:
 526                         break;
 527                 case RF_PATH_D:
 528                         break;
 529                 }
 530                 /*----Restore RFENV control type----*/;
 531                 switch (eRFPath) {
 532                 case RF_PATH_A:
 533                 case RF_PATH_C:
 534                         PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 535                         break;
 536                 case RF_PATH_B:
 537                 case RF_PATH_D:
 538                         PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
 539                         break;
 540                 }
 541                 if (rtStatus != _SUCCESS)
 542                         goto phy_RF6052_Config_ParaFile_Fail;
 543         }
 544         return rtStatus;
 545
 546 phy_RF6052_Config_ParaFile_Fail:
 547         return rtStatus;
 548 }
 549
 550 int PHY_RF6052_Config8188E(struct adapter *Adapter)
 551 {
 552         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 553         int rtStatus = _SUCCESS;
 554
 555         /*  */
 556         /*  Initialize general global value */
 557         /*  */
 558         /*  TODO: Extend RF_PATH_C and RF_PATH_D in the future */
 559         if (pHalData->rf_type == RF_1T1R)
 560                 pHalData->NumTotalRFPath = 1;
 561         else
 562                 pHalData->NumTotalRFPath = 2;
 563
 564         /*  */
 565         /*  Config BB and RF */
 566         /*  */
 567         rtStatus = phy_RF6052_Config_ParaFile(Adapter);
 568         return rtStatus;
 569 }