drivers/staging/r8188eu/hal/rtl8188e_phycfg.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _RTL8188E_PHYCFG_C_
  21
  22 #include <osdep_service.h>
  23 #include <drv_types.h>
  24 #include <rtw_iol.h>
  25 #include <rtl8188e_hal.h>
  26
  27 /*---------------------------Define Local Constant---------------------------*/
  28 /* Channel switch:The size of command tables for switch channel*/
  29 #define MAX_PRECMD_CNT 16
  30 #define MAX_RFDEPENDCMD_CNT 16
  31 #define MAX_POSTCMD_CNT 16
  32
  33 #define MAX_DOZE_WAITING_TIMES_9x 64
  34
  35 /*---------------------------Define Local Constant---------------------------*/
  36
  37 /*------------------------Define global variable-----------------------------*/
  38
  39 /*------------------------Define local variable------------------------------*/
  40
  41 /*--------------------Define export function prototype-----------------------*/
  42 /*  Please refer to header file */
  43 /*--------------------Define export function prototype-----------------------*/
  44
  45 /*----------------------------Function Body----------------------------------*/
  46 /*  */
  47 /*  1. BB register R/W API */
  48 /*  */
  49
  50 /**
  51 * Function:     phy_CalculateBitShift
  52 *
  53 * OverView:     Get shifted position of the BitMask
  54 *
  55 * Input:
  56 *                       u32             BitMask,
  57 *
  58 * Output:       none
  59 * Return:               u32             Return the shift bit bit position of the mask
  60 */
  61 static  u32 phy_CalculateBitShift(u32 BitMask)
  62 {
  63         u32 i;
  64
  65         for (i = 0; i <= 31; i++) {
  66                 if (((BitMask>>i) &  0x1) == 1)
  67                         break;
  68         }
  69         return i;
  70 }
  71
  72 /**
  73 * Function:     PHY_QueryBBReg
  74 *
  75 * OverView:     Read "sepcific bits" from BB register
  76 *
  77 * Input:
  78 *                       struct adapter *Adapter,
  79 *                       u32                     RegAddr,        The target address to be readback
  80 *                       u32                     BitMask         The target bit position in the target address
  81 *                                                               to be readback
  82 * Output:       None
  83 * Return:               u32                     Data            The readback register value
  84 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
  85 */
  86 u32
  87 rtl8188e_PHY_QueryBBReg(
  88                 struct adapter *Adapter,
  89                 u32 RegAddr,
  90                 u32 BitMask
  91         )
  92 {
  93         u32 ReturnValue = 0, OriginalValue, BitShift;
  94
  95         OriginalValue = rtw_read32(Adapter, RegAddr);
  96         BitShift = phy_CalculateBitShift(BitMask);
  97         ReturnValue = (OriginalValue & BitMask) >> BitShift;
  98         return ReturnValue;
  99 }
 100
 101 /**
 102 * Function:     PHY_SetBBReg
 103 *
 104 * OverView:     Write "Specific bits" to BB register (page 8~)
 105 *
 106 * Input:
 107 *                       struct adapter *Adapter,
 108 *                       u32                     RegAddr,        The target address to be modified
 109 *                       u32                     BitMask         The target bit position in the target address
 110 *                                                                       to be modified
 111 *                       u32                     Data            The new register value in the target bit position
 112 *                                                                       of the target address
 113 *
 114 * Output:       None
 115 * Return:               None
 116 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 117 */
 118
 119 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
 120 {
 121         u32 OriginalValue, BitShift;
 122
 123         if (BitMask != bMaskDWord) { /* if not "double word" write */
 124                 OriginalValue = rtw_read32(Adapter, RegAddr);
 125                 BitShift = phy_CalculateBitShift(BitMask);
 126                 Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));
 127         }
 128
 129         rtw_write32(Adapter, RegAddr, Data);
 130 }
 131
 132 /*  */
 133 /*  2. RF register R/W API */
 134 /*  */
 135 /**
 136 * Function:     phy_RFSerialRead
 137 *
 138 * OverView:     Read regster from RF chips
 139 *
 140 * Input:
 141 *                       struct adapter *Adapter,
 142 *                       enum rf_radio_path eRFPath,     Radio path of A/B/C/D
 143 *                       u32                     Offset,         The target address to be read
 144 *
 145 * Output:       None
 146 * Return:               u32                     reback value
 147 * Note:         Threre are three types of serial operations:
 148 *                       1. Software serial write
 149 *                       2. Hardware LSSI-Low Speed Serial Interface
 150 *                       3. Hardware HSSI-High speed
 151 *                       serial write. Driver need to implement (1) and (2).
 152 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 153 */
 154 static  u32
 155 phy_RFSerialRead(
 156                 struct adapter *Adapter,
 157                 enum rf_radio_path eRFPath,
 158                 u32 Offset
 159         )
 160 {
 161         u32 retValue = 0;
 162         struct hal_data_8188e                           *pHalData = GET_HAL_DATA(Adapter);
 163         struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 164         u32 NewOffset;
 165         u32 tmplong, tmplong2;
 166         u8      RfPiEnable = 0;
 167         /*  */
 168         /*  Make sure RF register offset is correct */
 169         /*  */
 170         Offset &= 0xff;
 171
 172         /*  */
 173         /*  Switch page for 8256 RF IC */
 174         /*  */
 175         NewOffset = Offset;
 176
 177         /*  For 92S LSSI Read RFLSSIRead */
 178         /*  For RF A/B write 0x824/82c(does not work in the future) */
 179         /*  We must use 0x824 for RF A and B to execute read trigger */
 180         tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
 181         if (eRFPath == RF_PATH_A)
 182                 tmplong2 = tmplong;
 183         else
 184                 tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
 185
 186         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  /* T65 RF */
 187
 188         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
 189         rtw_udelay_os(10);/*  PlatformStallExecution(10); */
 190
 191         PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
 192         rtw_udelay_os(100);/* PlatformStallExecution(100); */
 193
 194         rtw_udelay_os(10);/* PlatformStallExecution(10); */
 195
 196         if (eRFPath == RF_PATH_A)
 197                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
 198         else if (eRFPath == RF_PATH_B)
 199                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
 200
 201         if (RfPiEnable) {       /*  Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
 202                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
 203         } else {        /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
 204                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 205         }
 206         return retValue;
 207 }
 208
 209 /**
 210 * Function:     phy_RFSerialWrite
 211 *
 212 * OverView:     Write data to RF register (page 8~)
 213 *
 214 * Input:
 215 *                       struct adapter *Adapter,
 216 *                       enum rf_radio_path eRFPath,     Radio path of A/B/C/D
 217 *                       u32                     Offset,         The target address to be read
 218 *                       u32                     Data            The new register Data in the target bit position
 219 *                                                                       of the target to be read
 220 *
 221 * Output:       None
 222 * Return:               None
 223 * Note:         Threre are three types of serial operations:
 224 *                       1. Software serial write
 225 *                       2. Hardware LSSI-Low Speed Serial Interface
 226 *                       3. Hardware HSSI-High speed
 227 *                       serial write. Driver need to implement (1) and (2).
 228 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 229  *
 230  * Note:                  For RF8256 only
 231  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 232  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 233  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 234  *                       programming guide" for more details.
 235  *                       Thus, we define a sub-finction for RTL8526 register address conversion
 236  *                     ===========================================================
 237  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
 238  *                                                              (Reg00[12])             (Reg00[10])
 239  *                     ===========================================================
 240  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
 241  *                     ------------------------------------------------------------------
 242  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
 243  *                     ------------------------------------------------------------------
 244  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 245  *                     ------------------------------------------------------------------
 246  *
 247  *      2008/09/02      MH      Add 92S RF definition
 248  *
 249  *
 250  *
 251 */
 252 static  void
 253 phy_RFSerialWrite(
 254                 struct adapter *Adapter,
 255                 enum rf_radio_path eRFPath,
 256                 u32 Offset,
 257                 u32 Data
 258         )
 259 {
 260         u32 DataAndAddr = 0;
 261         struct hal_data_8188e                           *pHalData = GET_HAL_DATA(Adapter);
 262         struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 263         u32 NewOffset;
 264
 265         /*  2009/06/17 MH We can not execute IO for power save or other accident mode. */
 266
 267         Offset &= 0xff;
 268
 269         /*  */
 270         /*  Switch page for 8256 RF IC */
 271         /*  */
 272         NewOffset = Offset;
 273
 274         /*  */
 275         /*  Put write addr in [5:0]  and write data in [31:16] */
 276         /*  */
 277         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       /*  T65 RF */
 278
 279         /*  */
 280         /*  Write Operation */
 281         /*  */
 282         PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 283 }
 284
 285 /**
 286 * Function:     PHY_QueryRFReg
 287 *
 288 * OverView:     Query "Specific bits" to RF register (page 8~)
 289 *
 290 * Input:
 291 *                       struct adapter *Adapter,
 292 *                       enum rf_radio_path eRFPath,     Radio path of A/B/C/D
 293 *                       u32                     RegAddr,        The target address to be read
 294 *                       u32                     BitMask         The target bit position in the target address
 295 *                                                                       to be read
 296 *
 297 * Output:       None
 298 * Return:               u32                     Readback value
 299 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 300 */
 301 u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, enum rf_radio_path eRFPath,
 302                             u32 RegAddr, u32 BitMask)
 303 {
 304         u32 Original_Value, Readback_Value, BitShift;
 305
 306         Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
 307
 308         BitShift =  phy_CalculateBitShift(BitMask);
 309         Readback_Value = (Original_Value & BitMask) >> BitShift;
 310         return Readback_Value;
 311 }
 312
 313 /**
 314 * Function:     PHY_SetRFReg
 315 *
 316 * OverView:     Write "Specific bits" to RF register (page 8~)
 317 *
 318 * Input:
 319 *                       struct adapter *Adapter,
 320 *                       enum rf_radio_path eRFPath,     Radio path of A/B/C/D
 321 *                       u32                     RegAddr,        The target address to be modified
 322 *                       u32                     BitMask         The target bit position in the target address
 323 *                                                                       to be modified
 324 *                       u32                     Data            The new register Data in the target bit position
 325 *                                                                       of the target address
 326 *
 327 * Output:       None
 328 * Return:               None
 329 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 330 */
 331 void
 332 rtl8188e_PHY_SetRFReg(
 333                 struct adapter *Adapter,
 334                 enum rf_radio_path eRFPath,
 335                 u32 RegAddr,
 336                 u32 BitMask,
 337                 u32 Data
 338         )
 339 {
 340         u32 Original_Value, BitShift;
 341
 342         /*  RF data is 12 bits only */
 343         if (BitMask != bRFRegOffsetMask) {
 344                 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
 345                 BitShift =  phy_CalculateBitShift(BitMask);
 346                 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
 347         }
 348
 349         phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
 350 }
 351
 352 /*  */
 353 /*  3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
 354 /*  */
 355
 356 /*-----------------------------------------------------------------------------
 357  * Function:    PHY_MACConfig8192C
 358  *
 359  * Overview:    Condig MAC by header file or parameter file.
 360  *
 361  * Input:       NONE
 362  *
 363  * Output:      NONE
 364  *
 365  * Return:      NONE
 366  *
 367  * Revised History:
 368  *  When                Who             Remark
 369  *  08/12/2008  MHC             Create Version 0.
 370  *
 371  *---------------------------------------------------------------------------*/
 372 s32 PHY_MACConfig8188E(struct adapter *Adapter)
 373 {
 374         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
 375         int rtStatus = _SUCCESS;
 376
 377         /*  */
 378         /*  Config MAC */
 379         /*  */
 380         if (HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
 381                 rtStatus = _FAIL;
 382
 383         /*  2010.07.13 AMPDU aggregation number B */
 384         rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
 385
 386         return rtStatus;
 387 }
 388
 389 /**
 390 * Function:     phy_InitBBRFRegisterDefinition
 391 *
 392 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
 393 *
 394 * Input:
 395 *                       struct adapter *Adapter,
 396 *
 397 * Output:       None
 398 * Return:               None
 399 * Note:         The initialization value is constant and it should never be changes
 400 */
 401 static  void
 402 phy_InitBBRFRegisterDefinition(
 403                 struct adapter *Adapter
 404 )
 405 {
 406         struct hal_data_8188e           *pHalData = GET_HAL_DATA(Adapter);
 407
 408         /*  RF Interface Sowrtware Control */
 409         pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 LSBs if read 32-bit from 0x870 */
 410         pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 411         pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;/*  16 LSBs if read 32-bit from 0x874 */
 412         pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;/*  16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 413
 414         /*  RF Interface Readback Value */
 415         pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; /*  16 LSBs if read 32-bit from 0x8E0 */
 416         pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;/*  16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 417         pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;/*  16 LSBs if read 32-bit from 0x8E4 */
 418         pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;/*  16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 419
 420         /*  RF Interface Output (and Enable) */
 421         pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /*  16 LSBs if read 32-bit from 0x860 */
 422         pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /*  16 LSBs if read 32-bit from 0x864 */
 423
 424         /*  RF Interface (Output and)  Enable */
 425         pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /*  16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 426         pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /*  16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 427
 428         /* Addr of LSSI. Wirte RF register by driver */
 429         pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
 430         pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 431
 432         /*  RF parameter */
 433         pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  /* BB Band Select */
 434         pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 435         pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 436         pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 437
 438         /*  Tx AGC Gain Stage (same for all path. Should we remove this?) */
 439         pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
 440         pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
 441         pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
 442         pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
 443
 444         /*  Tranceiver A~D HSSI Parameter-1 */
 445         pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  /* wire control parameter1 */
 446         pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  /* wire control parameter1 */
 447
 448         /*  Tranceiver A~D HSSI Parameter-2 */
 449         pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
 450         pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
 451
 452         /*  RF switch Control */
 453         pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */
 454         pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 455         pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 456         pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 457
 458         /*  AGC control 1 */
 459         pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 460         pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 461         pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 462         pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 463
 464         /*  AGC control 2 */
 465         pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 466         pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 467         pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 468         pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 469
 470         /*  RX AFE control 1 */
 471         pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 472         pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 473         pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 474         pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 475
 476         /*  RX AFE control 1 */
 477         pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 478         pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 479         pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 480         pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 481
 482         /*  Tx AFE control 1 */
 483         pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 484         pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 485         pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 486         pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 487
 488         /*  Tx AFE control 2 */
 489         pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 490         pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 491         pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 492         pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 493
 494         /*  Tranceiver LSSI Readback SI mode */
 495         pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 496         pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 497         pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 498         pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 499
 500         /*  Tranceiver LSSI Readback PI mode */
 501         pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 502         pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
 503 }
 504
 505 void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
 506 {
 507         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
 508
 509         if (RegAddr == rTxAGC_A_Rate18_06)
 510                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
 511         if (RegAddr == rTxAGC_A_Rate54_24)
 512                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
 513         if (RegAddr == rTxAGC_A_CCK1_Mcs32)
 514                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
 515         if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
 516                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
 517         if (RegAddr == rTxAGC_A_Mcs03_Mcs00)
 518                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
 519         if (RegAddr == rTxAGC_A_Mcs07_Mcs04)
 520                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
 521         if (RegAddr == rTxAGC_A_Mcs11_Mcs08)
 522                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
 523         if (RegAddr == rTxAGC_A_Mcs15_Mcs12) {
 524                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
 525                 if (pHalData->rf_type == RF_1T1R)
 526                         pHalData->pwrGroupCnt++;
 527         }
 528         if (RegAddr == rTxAGC_B_Rate18_06)
 529                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
 530         if (RegAddr == rTxAGC_B_Rate54_24)
 531                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
 532         if (RegAddr == rTxAGC_B_CCK1_55_Mcs32)
 533                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
 534         if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
 535                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
 536         if (RegAddr == rTxAGC_B_Mcs03_Mcs00)
 537                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
 538         if (RegAddr == rTxAGC_B_Mcs07_Mcs04)
 539                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
 540         if (RegAddr == rTxAGC_B_Mcs11_Mcs08)
 541                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
 542         if (RegAddr == rTxAGC_B_Mcs15_Mcs12) {
 543                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
 544                 if (pHalData->rf_type != RF_1T1R)
 545                         pHalData->pwrGroupCnt++;
 546         }
 547 }
 548
 549 static  int phy_BB8188E_Config_ParaFile(struct adapter *Adapter)
 550 {
 551         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
 552         struct hal_data_8188e           *pHalData = GET_HAL_DATA(Adapter);
 553         int                     rtStatus = _SUCCESS;
 554
 555         /*  */
 556         /*  1. Read PHY_REG.TXT BB INIT!! */
 557         /*  We will separate as 88C / 92C according to chip version */
 558         /*  */
 559         if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
 560                 rtStatus = _FAIL;
 561         if (rtStatus != _SUCCESS)
 562                 goto phy_BB8190_Config_ParaFile_Fail;
 563
 564         /*  2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
 565         if (!pEEPROM->bautoload_fail_flag) {
 566                 pHalData->pwrGroupCnt = 0;
 567
 568                 if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
 569                         rtStatus = _FAIL;
 570         }
 571
 572         if (rtStatus != _SUCCESS)
 573                 goto phy_BB8190_Config_ParaFile_Fail;
 574
 575         /*  3. BB AGC table Initialization */
 576         if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv,  CONFIG_BB_AGC_TAB))
 577                 rtStatus = _FAIL;
 578
 579         if (rtStatus != _SUCCESS)
 580                 goto phy_BB8190_Config_ParaFile_Fail;
 581
 582 phy_BB8190_Config_ParaFile_Fail:
 583
 584         return rtStatus;
 585 }
 586
 587 int
 588 PHY_BBConfig8188E(
 589                 struct adapter *Adapter
 590         )
 591 {
 592         int     rtStatus = _SUCCESS;
 593         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
 594         u32 RegVal;
 595         u8 CrystalCap;
 596
 597         phy_InitBBRFRegisterDefinition(Adapter);
 598
 599         /*  Enable BB and RF */
 600         RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
 601         rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
 602
 603         /*  20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
 604
 605         rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
 606
 607         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
 608
 609         /*  Config BB and AGC */
 610         rtStatus = phy_BB8188E_Config_ParaFile(Adapter);
 611
 612         /*  write 0x24[16:11] = 0x24[22:17] = CrystalCap */
 613         CrystalCap = pHalData->CrystalCap & 0x3F;
 614         PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
 615
 616         return rtStatus;
 617 }
 618
 619 int PHY_RFConfig8188E(struct adapter *Adapter)
 620 {
 621         int             rtStatus = _SUCCESS;
 622
 623         /*  RF config */
 624         rtStatus = PHY_RF6052_Config8188E(Adapter);
 625         return rtStatus;
 626 }
 627
 628 /*-----------------------------------------------------------------------------
 629  * Function:    PHY_ConfigRFWithParaFile()
 630  *
 631  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
 632  *
 633  * Input:       struct adapter *Adapter
 634  *                      ps8                                     pFileName
 635  *                      enum rf_radio_path eRFPath
 636  *
 637  * Output:      NONE
 638  *
 639  * Return:      RT_STATUS_SUCCESS: configuration file exist
 640  *
 641  * Note:                Delay may be required for RF configuration
 642  *---------------------------------------------------------------------------*/
 643 int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *Adapter, u8 *pFileName, enum rf_radio_path eRFPath)
 644 {
 645         return _SUCCESS;
 646 }
 647
 648 void
 649 rtl8192c_PHY_GetHWRegOriginalValue(
 650                 struct adapter *Adapter
 651         )
 652 {
 653         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
 654
 655         /*  read rx initial gain */
 656         pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
 657         pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
 658         pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0);
 659         pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0);
 660
 661         /*  read framesync */
 662         pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0);
 663         pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord);
 664 }
 665
 666 /*  */
 667 /*      Description: */
 668 /*              Map dBm into Tx power index according to */
 669 /*              current HW model, for example, RF and PA, and */
 670 /*              current wireless mode. */
 671 /*      By Bruce, 2008-01-29. */
 672 /*  */
 673 static  u8 phy_DbmToTxPwrIdx(struct adapter *Adapter, enum wireless_mode WirelessMode, int PowerInDbm)
 674 {
 675         u8 TxPwrIdx = 0;
 676         int                             Offset = 0;
 677
 678         /*  */
 679         /*  Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to */
 680         /*  3dbm, and OFDM HT equals to 0dbm respectively. */
 681         /*  Note: */
 682         /*      The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
 683         /*  By Bruce, 2008-01-29. */
 684         /*  */
 685         switch (WirelessMode) {
 686         case WIRELESS_MODE_B:
 687                 Offset = -7;
 688                 break;
 689
 690         case WIRELESS_MODE_G:
 691         case WIRELESS_MODE_N_24G:
 692         default:
 693                 Offset = -8;
 694                 break;
 695         }
 696
 697         if ((PowerInDbm - Offset) > 0)
 698                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
 699         else
 700                 TxPwrIdx = 0;
 701
 702         /*  Tx Power Index is too large. */
 703         if (TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
 704                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
 705
 706         return TxPwrIdx;
 707 }
 708
 709 /*  */
 710 /*      Description: */
 711 /*              Map Tx power index into dBm according to */
 712 /*              current HW model, for example, RF and PA, and */
 713 /*              current wireless mode. */
 714 /*      By Bruce, 2008-01-29. */
 715 /*  */
 716 static int phy_TxPwrIdxToDbm(struct adapter *Adapter, enum wireless_mode WirelessMode, u8 TxPwrIdx)
 717 {
 718         int                             Offset = 0;
 719         int                             PwrOutDbm = 0;
 720
 721         /*  */
 722         /*  Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm. */
 723         /*  Note: */
 724         /*      The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
 725         /*  By Bruce, 2008-01-29. */
 726         /*  */
 727         switch (WirelessMode) {
 728         case WIRELESS_MODE_B:
 729                 Offset = -7;
 730                 break;
 731         case WIRELESS_MODE_G:
 732         case WIRELESS_MODE_N_24G:
 733         default:
 734                 Offset = -8;
 735                 break;
 736         }
 737
 738         PwrOutDbm = TxPwrIdx / 2 + Offset; /*  Discard the decimal part. */
 739
 740         return PwrOutDbm;
 741 }
 742
 743 /*-----------------------------------------------------------------------------
 744  * Function:    GetTxPowerLevel8190()
 745  *
 746  * Overview:    This function is export to "common" moudule
 747  *
 748  * Input:       struct adapter *Adapter
 749  *                      psByte                  Power Level
 750  *
 751  * Output:      NONE
 752  *
 753  * Return:      NONE
 754  *
 755  *---------------------------------------------------------------------------*/
 756 void PHY_GetTxPowerLevel8188E(struct adapter *Adapter, u32 *powerlevel)
 757 {
 758         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
 759         u8 TxPwrLevel = 0;
 760         int                     TxPwrDbm;
 761
 762         /*  */
 763         /*  Because the Tx power indexes are different, we report the maximum of them to */
 764         /*  meet the CCX TPC request. By Bruce, 2008-01-31. */
 765         /*  */
 766
 767         /*  CCK */
 768         TxPwrLevel = pHalData->CurrentCckTxPwrIdx;
 769         TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel);
 770
 771         /*  Legacy OFDM */
 772         TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff;
 773
 774         /*  Compare with Legacy OFDM Tx power. */
 775         if (phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
 776                 TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel);
 777
 778         /*  HT OFDM */
 779         TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx;
 780
 781         /*  Compare with HT OFDM Tx power. */
 782         if (phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
 783                 TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel);
 784
 785         *powerlevel = TxPwrDbm;
 786 }
 787
 788 static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
 789                                u8 *ofdmPowerLevel, u8 *BW20PowerLevel,
 790                                u8 *BW40PowerLevel)
 791 {
 792         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 793         u8 index = (channel - 1);
 794         u8 TxCount = 0, path_nums;
 795
 796         if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R == pHalData->rf_type))
 797                 path_nums = 1;
 798         else
 799                 path_nums = 2;
 800
 801         for (TxCount = 0; TxCount < path_nums; TxCount++) {
 802                 if (TxCount == RF_PATH_A) {
 803                         /*  1. CCK */
 804                         cckPowerLevel[TxCount]  = pHalData->Index24G_CCK_Base[TxCount][index];
 805                         /* 2. OFDM */
 806                         ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 807                                 pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A];
 808                         /*  1. BW20 */
 809                         BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 810                                 pHalData->BW20_24G_Diff[TxCount][RF_PATH_A];
 811                         /* 2. BW40 */
 812                         BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
 813                 } else if (TxCount == RF_PATH_B) {
 814                         /*  1. CCK */
 815                         cckPowerLevel[TxCount]  = pHalData->Index24G_CCK_Base[TxCount][index];
 816                         /* 2. OFDM */
 817                         ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 818                         pHalData->BW20_24G_Diff[RF_PATH_A][index]+
 819                         pHalData->BW20_24G_Diff[TxCount][index];
 820                         /*  1. BW20 */
 821                         BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 822                         pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]+
 823                         pHalData->BW20_24G_Diff[TxCount][index];
 824                         /* 2. BW40 */
 825                         BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
 826                 } else if (TxCount == RF_PATH_C) {
 827                         /*  1. CCK */
 828                         cckPowerLevel[TxCount]  = pHalData->Index24G_CCK_Base[TxCount][index];
 829                         /* 2. OFDM */
 830                         ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 831                         pHalData->BW20_24G_Diff[RF_PATH_A][index]+
 832                         pHalData->BW20_24G_Diff[RF_PATH_B][index]+
 833                         pHalData->BW20_24G_Diff[TxCount][index];
 834                         /*  1. BW20 */
 835                         BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 836                         pHalData->BW20_24G_Diff[RF_PATH_A][index]+
 837                         pHalData->BW20_24G_Diff[RF_PATH_B][index]+
 838                         pHalData->BW20_24G_Diff[TxCount][index];
 839                         /* 2. BW40 */
 840                         BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
 841                 } else if (TxCount == RF_PATH_D) {
 842                         /*  1. CCK */
 843                         cckPowerLevel[TxCount]  = pHalData->Index24G_CCK_Base[TxCount][index];
 844                         /* 2. OFDM */
 845                         ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 846                         pHalData->BW20_24G_Diff[RF_PATH_A][index]+
 847                         pHalData->BW20_24G_Diff[RF_PATH_B][index]+
 848                         pHalData->BW20_24G_Diff[RF_PATH_C][index]+
 849                         pHalData->BW20_24G_Diff[TxCount][index];
 850
 851                         /*  1. BW20 */
 852                         BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
 853                         pHalData->BW20_24G_Diff[RF_PATH_A][index]+
 854                         pHalData->BW20_24G_Diff[RF_PATH_B][index]+
 855                         pHalData->BW20_24G_Diff[RF_PATH_C][index]+
 856                         pHalData->BW20_24G_Diff[TxCount][index];
 857
 858                         /* 2. BW40 */
 859                         BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
 860                 }
 861         }
 862 }
 863
 864 static void phy_PowerIndexCheck88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
 865                                    u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel)
 866 {
 867         struct hal_data_8188e           *pHalData = GET_HAL_DATA(Adapter);
 868
 869         pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
 870         pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
 871         pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];
 872         pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];
 873 }
 874
 875 /*-----------------------------------------------------------------------------
 876  * Function:    SetTxPowerLevel8190()
 877  *
 878  * Overview:    This function is export to "HalCommon" moudule
 879  *                      We must consider RF path later!!!!!!!
 880  *
 881  * Input:       struct adapter *Adapter
 882  *                      u8              channel
 883  *
 884  * Output:      NONE
 885  *
 886  * Return:      NONE
 887  *      2008/11/04      MHC             We remove EEPROM_93C56.
 888  *                                              We need to move CCX relative code to independet file.
 889  *      2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
 890  *
 891  *---------------------------------------------------------------------------*/
 892 void
 893 PHY_SetTxPowerLevel8188E(
 894                 struct adapter *Adapter,
 895                 u8 channel
 896         )
 897 {
 898         u8 cckPowerLevel[MAX_TX_COUNT] = {0};
 899         u8 ofdmPowerLevel[MAX_TX_COUNT] = {0};/*  [0]:RF-A, [1]:RF-B */
 900         u8 BW20PowerLevel[MAX_TX_COUNT] = {0};
 901         u8 BW40PowerLevel[MAX_TX_COUNT] = {0};
 902
 903         getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
 904
 905         phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
 906
 907         rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
 908         rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel);
 909 }
 910
 911 /*  */
 912 /*      Description: */
 913 /*              Update transmit power level of all channel supported. */
 914 /*  */
 915 /*      TODO: */
 916 /*              A mode. */
 917 /*      By Bruce, 2008-02-04. */
 918 /*  */
 919 bool
 920 PHY_UpdateTxPowerDbm8188E(
 921                 struct adapter *Adapter,
 922                 int             powerInDbm
 923         )
 924 {
 925         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
 926         u8 idx;
 927         u8 rf_path;
 928
 929         /*  TODO: A mode Tx power. */
 930         u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm);
 931         u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm);
 932
 933         if (OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)
 934                 OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff;
 935         else
 936                 OfdmTxPwrIdx = 0;
 937
 938         for (idx = 0; idx < 14; idx++) {
 939                 for (rf_path = 0; rf_path < 2; rf_path++) {
 940                         pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
 941                         pHalData->TxPwrLevelHT40_1S[rf_path][idx] =
 942                         pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;
 943                 }
 944         }
 945         return true;
 946 }
 947
 948 void
 949 PHY_ScanOperationBackup8188E(
 950                 struct adapter *Adapter,
 951                 u8 Operation
 952         )
 953 {
 954 }
 955
 956 /*-----------------------------------------------------------------------------
 957  * Function:    PHY_SetBWModeCallback8192C()
 958  *
 959  * Overview:    Timer callback function for SetSetBWMode
 960  *
 961  * Input:               PRT_TIMER               pTimer
 962  *
 963  * Output:      NONE
 964  *
 965  * Return:      NONE
 966  *
 967  * Note:                (1) We do not take j mode into consideration now
 968  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
 969  *                           concurrently?
 970  *---------------------------------------------------------------------------*/
 971 static void
 972 _PHY_SetBWMode92C(
 973                 struct adapter *Adapter
 974 )
 975 {
 976         struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
 977         u8 regBwOpMode;
 978         u8 regRRSR_RSC;
 979
 980         if (pHalData->rf_chip == RF_PSEUDO_11N)
 981                 return;
 982
 983         /*  There is no 40MHz mode in RF_8225. */
 984         if (pHalData->rf_chip == RF_8225)
 985                 return;
 986
 987         if (Adapter->bDriverStopped)
 988                 return;
 989
 990         /* 3 */
 991         /* 3<1>Set MAC register */
 992         /* 3 */
 993
 994         regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
 995         regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
 996
 997         switch (pHalData->CurrentChannelBW) {
 998         case HT_CHANNEL_WIDTH_20:
 999                 regBwOpMode |= BW_OPMODE_20MHZ;
1000                 /*  2007/02/07 Mark by Emily because we have not verify whether this register works */
1001                 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1002                 break;
1003         case HT_CHANNEL_WIDTH_40:
1004                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1005                 /*  2007/02/07 Mark by Emily because we have not verify whether this register works */
1006                 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1007                 regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5);
1008                 rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
1009                 break;
1010         default:
1011                 break;
1012         }
1013
1014         /* 3  */
1015         /* 3 <2>Set PHY related register */
1016         /* 3 */
1017         switch (pHalData->CurrentChannelBW) {
1018         /* 20 MHz channel*/
1019         case HT_CHANNEL_WIDTH_20:
1020                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
1021                 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
1022                 break;
1023         /* 40 MHz channel*/
1024         case HT_CHANNEL_WIDTH_40:
1025                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
1026                 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
1027                 /*  Set Control channel to upper or lower. These settings are required only for 40MHz */
1028                 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
1029                 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
1030                 PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27),
1031                              (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1032                 break;
1033         default:
1034                 break;
1035         }
1036         /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
1037
1038         /* 3<3>Set RF related register */
1039         switch (pHalData->rf_chip) {
1040         case RF_8225:
1041                 break;
1042         case RF_8256:
1043                 /*  Please implement this function in Hal8190PciPhy8256.c */
1044                 break;
1045         case RF_8258:
1046                 /*  Please implement this function in Hal8190PciPhy8258.c */
1047                 break;
1048         case RF_PSEUDO_11N:
1049                 break;
1050         case RF_6052:
1051                 rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
1052                 break;
1053         default:
1054                 break;
1055         }
1056 }
1057
1058  /*-----------------------------------------------------------------------------
1059  * Function:   SetBWMode8190Pci()
1060  *
1061  * Overview:  This function is export to "HalCommon" moudule
1062  *
1063  * Input:               struct adapter *Adapter
1064  *                      enum ht_channel_width Bandwidth 20M or 40M
1065  *
1066  * Output:      NONE
1067  *
1068  * Return:      NONE
1069  *
1070  * Note:                We do not take j mode into consideration now
1071  *---------------------------------------------------------------------------*/
1072 void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth,       /*  20M or 40M */
1073                         unsigned char   Offset)         /*  Upper, Lower, or Don't care */
1074 {
1075         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
1076         enum ht_channel_width tmpBW = pHalData->CurrentChannelBW;
1077
1078         pHalData->CurrentChannelBW = Bandwidth;
1079
1080         pHalData->nCur40MhzPrimeSC = Offset;
1081
1082         if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
1083                 _PHY_SetBWMode92C(Adapter);
1084         else
1085                 pHalData->CurrentChannelBW = tmpBW;
1086 }
1087
1088 static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
1089 {
1090         u8 eRFPath;
1091         u32 param1, param2;
1092         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
1093
1094         if (Adapter->bNotifyChannelChange)
1095                 DBG_88E("[%s] ch = %d\n", __func__, channel);
1096
1097         /* s1. pre common command - CmdID_SetTxPowerLevel */
1098         PHY_SetTxPowerLevel8188E(Adapter, channel);
1099
1100         /* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
1101         param1 = RF_CHNLBW;
1102         param2 = channel;
1103         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
1104                 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
1105                 PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
1106         }
1107 }
1108
1109 void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel)
1110 {
1111         /*  Call after initialization */
1112         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
1113         u8 tmpchannel = pHalData->CurrentChannel;
1114         bool  bResult = true;
1115
1116         if (pHalData->rf_chip == RF_PSEUDO_11N)
1117                 return;         /* return immediately if it is peudo-phy */
1118
1119         if (channel == 0)
1120                 channel = 1;
1121
1122         pHalData->CurrentChannel = channel;
1123
1124         if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
1125                 _PHY_SwChnl8192C(Adapter, channel);
1126
1127                 if (bResult)
1128                         ;
1129                 else
1130                         pHalData->CurrentChannel = tmpchannel;
1131
1132         } else {
1133                 pHalData->CurrentChannel = tmpchannel;
1134         }
1135 }