drivers/staging/r8188eu/hal/rtl8188e_mp.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _RTL8188E_MP_C_
  21
  22 #include <drv_types.h>
  23 #include <rtw_mp.h>
  24 #include <rtl8188e_hal.h>
  25 #include <rtl8188e_dm.h>
  26
  27 s32 Hal_SetPowerTracking(struct adapter *padapter, u8 enable)
  28 {
  29         struct hal_data_8188e   *pHalData = GET_HAL_DATA(padapter);
  30         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
  31
  32         if (!netif_running(padapter->pnetdev)) {
  33                 RT_TRACE(_module_mp_, _drv_warning_,
  34                          ("SetPowerTracking! Fail: interface not opened!\n"));
  35                 return _FAIL;
  36         }
  37
  38         if (!check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE)) {
  39                 RT_TRACE(_module_mp_, _drv_warning_,
  40                          ("SetPowerTracking! Fail: not in MP mode!\n"));
  41                 return _FAIL;
  42         }
  43
  44         if (enable)
  45                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
  46         else
  47                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
  48
  49         return _SUCCESS;
  50 }
  51
  52 void Hal_GetPowerTracking(struct adapter *padapter, u8 *enable)
  53 {
  54         struct hal_data_8188e   *pHalData = GET_HAL_DATA(padapter);
  55         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
  56
  57         *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
  58 }
  59
  60 /*-----------------------------------------------------------------------------
  61  * Function:    mpt_SwitchRfSetting
  62  *
  63  * Overview:    Change RF Setting when we siwthc channel/rate/BW for MP.
  64  *
  65  * Input:       struct adapter *                                pAdapter
  66  *
  67  * Output:      NONE
  68  *
  69  * Return:      NONE
  70  *
  71  * Revised History:
  72  * When                 Who             Remark
  73  * 01/08/2009   MHC             Suggestion from SD3 Willis for 92S series.
  74  * 01/09/2009   MHC             Add CCK modification for 40MHZ. Suggestion from SD3.
  75  *
  76  *---------------------------------------------------------------------------*/
  77 void Hal_mpt_SwitchRfSetting(struct adapter *pAdapter)
  78 {
  79         struct mp_priv  *pmp = &pAdapter->mppriv;
  80
  81         /*  <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. */
  82                 pmp->MptCtx.backup0x52_RF_A = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
  83                 pmp->MptCtx.backup0x52_RF_B = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
  84                 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
  85                 PHY_SetRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
  86
  87         return;
  88 }
  89 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
  90
  91 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
  92 void Hal_MPT_CCKTxPowerAdjust(struct adapter *Adapter, bool bInCH14)
  93 {
  94         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;
  95         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;
  96         u8              i;
  97
  98         /*  get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
  99         CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
 100
 101         if (!bInCH14) {
 102                 /*  Readback the current bb cck swing value and compare with the table to */
 103                 /*  get the current swing index */
 104                 for (i = 0; i < CCK_TABLE_SIZE; i++) {
 105                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
 106                             (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
 107                                 CCKSwingIndex = i;
 108                                 break;
 109                         }
 110                 }
 111
 112                 /* Write 0xa22 0xa23 */
 113                 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
 114                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8);
 115
 116                 /* Write 0xa24 ~ 0xa27 */
 117                 TempVal2 = 0;
 118                 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
 119                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
 120                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16)+
 121                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
 122
 123                 /* Write 0xa28  0xa29 */
 124                 TempVal3 = 0;
 125                 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
 126                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);
 127         } else {
 128                 for (i = 0; i < CCK_TABLE_SIZE; i++) {
 129                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
 130                             (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {
 131                                 CCKSwingIndex = i;
 132                                 break;
 133                         }
 134                 }
 135
 136                 /* Write 0xa22 0xa23 */
 137                 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
 138                                 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8);
 139
 140                 /* Write 0xa24 ~ 0xa27 */
 141                 TempVal2 = 0;
 142                 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
 143                                 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
 144                                 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16)+
 145                                 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
 146
 147                 /* Write 0xa28  0xa29 */
 148                 TempVal3 = 0;
 149                 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
 150                                 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8);
 151         }
 152
 153         write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
 154         write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
 155         write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
 156 }
 157
 158 void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter *pAdapter, bool beven)
 159 {
 160         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 161         struct mpt_context *pMptCtx = &pAdapter->mppriv.MptCtx;
 162         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
 163         s32             TempCCk;
 164         u8              CCK_index, CCK_index_old = 0;
 165         u8              Action = 0;     /* 0: no action, 1: even->odd, 2:odd->even */
 166         s32             i = 0;
 167
 168         if (!IS_92C_SERIAL(pHalData->VersionID))
 169                 return;
 170         if (beven && !pMptCtx->bMptIndexEven) {
 171                 /* odd->even */
 172                 Action = 2;
 173                 pMptCtx->bMptIndexEven = true;
 174         } else if (!beven && pMptCtx->bMptIndexEven) {
 175                 /* even->odd */
 176                 Action = 1;
 177                 pMptCtx->bMptIndexEven = false;
 178         }
 179
 180         if (Action != 0) {
 181                 /* Query CCK default setting From 0xa24 */
 182                 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
 183                 for (i = 0; i < CCK_TABLE_SIZE; i++) {
 184                         if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 185                                 if (!memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch14[i][2], 4)) {
 186                                         CCK_index_old = (u8)i;
 187                                         break;
 188                                 }
 189                         } else {
 190                                 if (!memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch1_Ch13[i][2], 4)) {
 191                                         CCK_index_old = (u8)i;
 192                                         break;
 193                                 }
 194                         }
 195                 }
 196
 197                 if (Action == 1)
 198                         CCK_index = CCK_index_old - 1;
 199                 else
 200                         CCK_index = CCK_index_old + 1;
 201
 202                 /* Adjust CCK according to gain index */
 203                 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 204                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
 205                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
 206                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
 207                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
 208                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
 209                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
 210                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
 211                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
 212                 } else {
 213                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
 214                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
 215                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
 216                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
 217                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
 218                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
 219                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
 220                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
 221                 }
 222         }
 223 }
 224 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
 225
 226 /*
 227  * SetChannel
 228  * Description
 229  *      Use H2C command to change channel,
 230  *      not only modify rf register, but also other setting need to be done.
 231  */
 232 void Hal_SetChannel(struct adapter *pAdapter)
 233 {
 234         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 235         struct mp_priv  *pmp = &pAdapter->mppriv;
 236         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
 237         u8              eRFPath;
 238         u8              channel = pmp->channel;
 239
 240         /*  set RF channel register */
 241         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
 242                 _write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
 243         Hal_mpt_SwitchRfSetting(pAdapter);
 244
 245         SelectChannel(pAdapter, channel);
 246
 247         if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 248                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = true;
 249                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
 250         } else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 251                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = false;
 252                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
 253         }
 254 }
 255
 256 /*
 257  * Notice
 258  *      Switch bandwitdth may change center frequency(channel)
 259  */
 260 void Hal_SetBandwidth(struct adapter *pAdapter)
 261 {
 262         struct mp_priv *pmp = &pAdapter->mppriv;
 263
 264         SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
 265         Hal_mpt_SwitchRfSetting(pAdapter);
 266 }
 267
 268 void Hal_SetCCKTxPower(struct adapter *pAdapter, u8 *TxPower)
 269 {
 270         u32 tmpval = 0;
 271
 272         /*  rf-A cck tx power */
 273         write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
 274         tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
 275         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 276
 277         /*  rf-B cck tx power */
 278         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
 279         tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
 280         write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
 281
 282         RT_TRACE(_module_mp_, _drv_notice_,
 283                  ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
 284                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
 285 }
 286
 287 void Hal_SetOFDMTxPower(struct adapter *pAdapter, u8 *TxPower)
 288 {
 289         u32 TxAGC = 0;
 290         u8 tmpval = 0;
 291
 292         /*  HT Tx-rf(A) */
 293         tmpval = TxPower[RF_PATH_A];
 294         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
 295
 296         write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
 297         write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
 298         write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
 299         write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
 300         write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
 301         write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
 302
 303         /*  HT Tx-rf(B) */
 304         tmpval = TxPower[RF_PATH_B];
 305         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
 306
 307         write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
 308         write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
 309         write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
 310         write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
 311         write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
 312         write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
 313 }
 314
 315 void Hal_SetAntennaPathPower(struct adapter *pAdapter)
 316 {
 317         struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
 318         u8 TxPowerLevel[RF_PATH_MAX];
 319         u8 rfPath;
 320
 321         TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
 322         TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
 323
 324         switch (pAdapter->mppriv.antenna_tx) {
 325         case ANTENNA_A:
 326         default:
 327                 rfPath = RF_PATH_A;
 328                 break;
 329         case ANTENNA_B:
 330                 rfPath = RF_PATH_B;
 331                 break;
 332         case ANTENNA_C:
 333                 rfPath = RF_PATH_C;
 334                 break;
 335         }
 336
 337         switch (pHalData->rf_chip) {
 338         case RF_8225:
 339         case RF_8256:
 340         case RF_6052:
 341                 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
 342                 if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     /*  CCK rate */
 343                         Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
 344                 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
 345                 break;
 346         default:
 347                 break;
 348         }
 349 }
 350
 351 void Hal_SetTxPower(struct adapter *pAdapter)
 352 {
 353         struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
 354         u8 TxPower = pAdapter->mppriv.txpoweridx;
 355         u8 TxPowerLevel[RF_PATH_MAX];
 356         u8 rf, rfPath;
 357
 358         for (rf = 0; rf < RF_PATH_MAX; rf++)
 359                 TxPowerLevel[rf] = TxPower;
 360
 361         switch (pAdapter->mppriv.antenna_tx) {
 362         case ANTENNA_A:
 363         default:
 364                 rfPath = RF_PATH_A;
 365                 break;
 366         case ANTENNA_B:
 367                 rfPath = RF_PATH_B;
 368                 break;
 369         case ANTENNA_C:
 370                 rfPath = RF_PATH_C;
 371                 break;
 372         }
 373
 374         switch (pHalData->rf_chip) {
 375         /*  2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
 376         /*  We should call normal driver API later!! */
 377         case RF_8225:
 378         case RF_8256:
 379         case RF_6052:
 380                 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
 381                 if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     /*  CCK rate */
 382                         Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
 383                 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
 384                 break;
 385         default:
 386                 break;
 387         }
 388 }
 389
 390 void Hal_SetDataRate(struct adapter *pAdapter)
 391 {
 392         Hal_mpt_SwitchRfSetting(pAdapter);
 393 }
 394
 395 void Hal_SetAntenna(struct adapter *pAdapter)
 396 {
 397         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 398
 399         struct ant_sel_ofdm *p_ofdm_tx; /* OFDM Tx register */
 400         struct ant_sel_cck *p_cck_txrx;
 401         u8      r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
 402         u8      chgTx = 0, chgRx = 0;
 403         u32     r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
 404
 405         p_ofdm_tx = (struct ant_sel_ofdm *)&r_ant_select_ofdm_val;
 406         p_cck_txrx = (struct ant_sel_cck *)&r_ant_select_cck_val;
 407
 408         p_ofdm_tx->r_ant_ht1    = 0x1;
 409         p_ofdm_tx->r_ant_ht2    = 0x2;  /*  Second TX RF path is A */
 410         p_ofdm_tx->r_ant_non_ht = 0x3;  /*  0x1+0x2=0x3 */
 411
 412         switch (pAdapter->mppriv.antenna_tx) {
 413         case ANTENNA_A:
 414                 p_ofdm_tx->r_tx_antenna         = 0x1;
 415                 r_ofdm_tx_en_val                = 0x1;
 416                 p_ofdm_tx->r_ant_l              = 0x1;
 417                 p_ofdm_tx->r_ant_ht_s1          = 0x1;
 418                 p_ofdm_tx->r_ant_non_ht_s1      = 0x1;
 419                 p_cck_txrx->r_ccktx_enable      = 0x8;
 420                 chgTx = 1;
 421
 422                 /*  From SD3 Willis suggestion !!! Set RF A=TX and B as standby */
 423                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 424                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
 425                 r_ofdm_tx_en_val                = 0x3;
 426
 427                 /*  Power save */
 428
 429                 /*  We need to close RFB by SW control */
 430                 if (pHalData->rf_type == RF_2T2R) {
 431                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
 432                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
 433                         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
 434                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
 435                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
 436                 }
 437                 break;
 438         case ANTENNA_B:
 439                 p_ofdm_tx->r_tx_antenna         = 0x2;
 440                 r_ofdm_tx_en_val                = 0x2;
 441                 p_ofdm_tx->r_ant_l              = 0x2;
 442                 p_ofdm_tx->r_ant_ht_s1          = 0x2;
 443                 p_ofdm_tx->r_ant_non_ht_s1      = 0x2;
 444                 p_cck_txrx->r_ccktx_enable      = 0x4;
 445                 chgTx = 1;
 446                 /*  From SD3 Willis suggestion !!! Set RF A as standby */
 447                 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
 448                 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 449
 450                 /*  Power save */
 451                 /* cosa r_ant_select_ofdm_val = 0x22222222; */
 452
 453                 /*  2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
 454                 /*  2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
 455                 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
 456                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
 457                         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
 458                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
 459                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
 460                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
 461                 }
 462                 break;
 463         case ANTENNA_AB:        /*  For 8192S */
 464                 p_ofdm_tx->r_tx_antenna         = 0x3;
 465                 r_ofdm_tx_en_val                = 0x3;
 466                 p_ofdm_tx->r_ant_l              = 0x3;
 467                 p_ofdm_tx->r_ant_ht_s1          = 0x3;
 468                 p_ofdm_tx->r_ant_non_ht_s1      = 0x3;
 469                 p_cck_txrx->r_ccktx_enable      = 0xC;
 470                 chgTx = 1;
 471
 472                 /*  From SD3 Willis suggestion !!! Set RF B as standby */
 473                 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 474                 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 475
 476                 /*  Disable Power save */
 477                 /* cosa r_ant_select_ofdm_val = 0x3321333; */
 478                 /*  2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
 479                 if (pHalData->rf_type == RF_2T2R) {
 480                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
 481                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
 482                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
 483                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
 484                 }
 485                 break;
 486         default:
 487                 break;
 488         }
 489
 490         /*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
 491         /*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
 492         /*  r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
 493         switch (pAdapter->mppriv.antenna_rx) {
 494         case ANTENNA_A:
 495                 r_rx_antenna_ofdm               = 0x1;  /*  A */
 496                 p_cck_txrx->r_cckrx_enable      = 0x0;  /*  default: A */
 497                 p_cck_txrx->r_cckrx_enable_2    = 0x0;  /*  option: A */
 498                 chgRx = 1;
 499                 break;
 500         case ANTENNA_B:
 501                 r_rx_antenna_ofdm               = 0x2;  /*  B */
 502                 p_cck_txrx->r_cckrx_enable      = 0x1;  /*  default: B */
 503                 p_cck_txrx->r_cckrx_enable_2    = 0x1;  /*  option: B */
 504                 chgRx = 1;
 505                 break;
 506         case ANTENNA_AB:
 507                 r_rx_antenna_ofdm               = 0x3;  /*  AB */
 508                 p_cck_txrx->r_cckrx_enable      = 0x0;  /*  default:A */
 509                 p_cck_txrx->r_cckrx_enable_2    = 0x1;  /*  option:B */
 510                 chgRx = 1;
 511                 break;
 512         default:
 513                 break;
 514         }
 515
 516         if (chgTx && chgRx) {
 517                 switch (pHalData->rf_chip) {
 518                 case RF_8225:
 519                 case RF_8256:
 520                 case RF_6052:
 521                         /* r_ant_sel_cck_val = r_ant_select_cck_val; */
 522                         PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);       /* OFDM Tx */
 523                         PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);            /* OFDM Tx */
 524                         PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    /* OFDM Rx */
 525                         PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    /* OFDM Rx */
 526                         PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);     /* CCK TxRx */
 527
 528                         break;
 529                 default:
 530                         break;
 531                 }
 532         }
 533
 534         RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
 535 }
 536
 537 s32 Hal_SetThermalMeter(struct adapter *pAdapter, u8 target_ther)
 538 {
 539         struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
 540
 541         if (!netif_running(pAdapter->pnetdev)) {
 542                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
 543                 return _FAIL;
 544         }
 545
 546         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == false) {
 547                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
 548                 return _FAIL;
 549         }
 550
 551         target_ther &= 0xff;
 552         if (target_ther < 0x07)
 553                 target_ther = 0x07;
 554         else if (target_ther > 0x1d)
 555                 target_ther = 0x1d;
 556
 557         pHalData->EEPROMThermalMeter = target_ther;
 558
 559         return _SUCCESS;
 560 }
 561
 562 void Hal_TriggerRFThermalMeter(struct adapter *pAdapter)
 563 {
 564         _write_rfreg(pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 | BIT16 , 0x03);
 565 }
 566
 567 u8 Hal_ReadRFThermalMeter(struct adapter *pAdapter)
 568 {
 569         u32 ThermalValue = 0;
 570
 571         ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);
 572         return (u8)ThermalValue;
 573 }
 574
 575 void Hal_GetThermalMeter(struct adapter *pAdapter, u8 *value)
 576 {
 577         Hal_TriggerRFThermalMeter(pAdapter);
 578         rtw_msleep_os(1000);
 579         *value = Hal_ReadRFThermalMeter(pAdapter);
 580 }
 581
 582 void Hal_SetSingleCarrierTx(struct adapter *pAdapter, u8 bStart)
 583 {
 584         pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
 585         if (bStart) {
 586                 /*  Start Single Carrier. */
 587                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
 588                 /*  1. if OFDM block on? */
 589                 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 590                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
 591
 592                 /*  2. set CCK test mode off, set to CCK normal mode */
 593                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 594                 /*  3. turn on scramble setting */
 595                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 596                 /*  4. Turn On Single Carrier Tx and turn off the other test modes. */
 597                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 598                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
 599                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 600                 /* for dynamic set Power index. */
 601                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 602                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 603         } else {
 604                 /*  Stop Single Carrier. */
 605                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test stop\n"));
 606
 607                 /*  Turn off all test modes. */
 608                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 609                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 610                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 611                 rtw_msleep_os(10);
 612
 613                 /* BB Reset */
 614                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 615                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 616
 617                 /* Stop for dynamic set Power index. */
 618                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 619                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 620         }
 621 }
 622
 623 void Hal_SetSingleToneTx(struct adapter *pAdapter, u8 bStart)
 624 {
 625         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 626         bool            is92C = IS_92C_SERIAL(pHalData->VersionID);
 627
 628         u8 rfPath;
 629         u32              reg58 = 0x0;
 630         switch (pAdapter->mppriv.antenna_tx) {
 631         case ANTENNA_A:
 632         default:
 633                 rfPath = RF_PATH_A;
 634                 break;
 635         case ANTENNA_B:
 636                 rfPath = RF_PATH_B;
 637                 break;
 638         case ANTENNA_C:
 639                 rfPath = RF_PATH_C;
 640                 break;
 641         }
 642
 643         pAdapter->mppriv.MptCtx.bSingleTone = bStart;
 644         if (bStart) {
 645                 /*  Start Single Tone. */
 646                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test start\n"));
 647                 /*  <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
 648                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
 649                         reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
 650                         reg58 &= 0xFFFFFFF0;
 651                         reg58 += 2;
 652                         PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
 653                 }
 654                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
 655                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
 656
 657                 if (is92C) {
 658                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
 659                         rtw_usleep_os(100);
 660                         if (rfPath == RF_PATH_A)
 661                                 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); /*  PAD all on. */
 662                         else if (rfPath == RF_PATH_B)
 663                                 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /*  PAD all on. */
 664                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /*  PAD all on. */
 665                         rtw_usleep_os(100);
 666                 } else {
 667                         write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
 668                         rtw_usleep_os(100);
 669                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /*  PAD all on. */
 670                         rtw_usleep_os(100);
 671                 }
 672
 673                 /* for dynamic set Power index. */
 674                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 675                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 676
 677         } else {
 678                 /*  Stop Single Tone. */
 679                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test stop\n"));
 680
 681                 /*  <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
 682                 /*  <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
 683                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
 684                         reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
 685                         reg58 &= 0xFFFFFFF0;
 686                         PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
 687                 }
 688                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 689                 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 690                 if (is92C) {
 691                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
 692                         rtw_usleep_os(100);
 693                         write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); /*  PAD all on. */
 694                         write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); /*  PAD all on. */
 695                         rtw_usleep_os(100);
 696                 } else {
 697                         write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
 698                         rtw_usleep_os(100);
 699                         write_rfreg(pAdapter, rfPath, 0x00, 0x30000); /*  PAD all on. */
 700                         rtw_usleep_os(100);
 701                 }
 702
 703                 /* Stop for dynamic set Power index. */
 704                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 705                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 706         }
 707 }
 708
 709 void Hal_SetCarrierSuppressionTx(struct adapter *pAdapter, u8 bStart)
 710 {
 711         pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
 712         if (bStart) {
 713                 /*  Start Carrier Suppression. */
 714                 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
 715                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
 716                         /*  1. if CCK block on? */
 717                         if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
 718                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
 719
 720                         /* Turn Off All Test Mode */
 721                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 722                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 723                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 724
 725                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /* transmit mode */
 726                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /* turn off scramble setting */
 727
 728                         /* Set CCK Tx Test Rate */
 729                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /* Set FTxRate to 1Mbps */
 730                 }
 731
 732                 /* for dynamic set Power index. */
 733                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 734                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 735         } else {
 736                 /*  Stop Carrier Suppression. */
 737                 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
 738                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
 739                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /* normal mode */
 740                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /* turn on scramble setting */
 741
 742                         /* BB Reset */
 743                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 744                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 745                 }
 746
 747                 /* Stop for dynamic set Power index. */
 748                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 749                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 750         }
 751 }
 752
 753 void Hal_SetCCKContinuousTx(struct adapter *pAdapter, u8 bStart)
 754 {
 755         u32 cckrate;
 756
 757         if (bStart) {
 758                 RT_TRACE(_module_mp_, _drv_alert_,
 759                          ("SetCCKContinuousTx: test start\n"));
 760
 761                 /*  1. if CCK block on? */
 762                 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
 763                         write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
 764
 765                 /* Turn Off All Test Mode */
 766                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 767                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 768                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 769                 /* Set CCK Tx Test Rate */
 770                 cckrate  = pAdapter->mppriv.rateidx;
 771                 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
 772                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);   /* transmit mode */
 773                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     /* turn on scramble setting */
 774
 775                 /* for dynamic set Power index. */
 776                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 777                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 778         } else {
 779                 RT_TRACE(_module_mp_, _drv_info_,
 780                          ("SetCCKContinuousTx: test stop\n"));
 781
 782                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);   /* normal mode */
 783                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     /* turn on scramble setting */
 784
 785                 /* BB Reset */
 786                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 787                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 788
 789                 /* Stop for dynamic set Power index. */
 790                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 791                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 792         }
 793
 794         pAdapter->mppriv.MptCtx.bCckContTx = bStart;
 795         pAdapter->mppriv.MptCtx.bOfdmContTx = false;
 796 } /* mpt_StartCckContTx */
 797
 798 void Hal_SetOFDMContinuousTx(struct adapter *pAdapter, u8 bStart)
 799 {
 800         if (bStart) {
 801                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
 802                 /*  1. if OFDM block on? */
 803                 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 804                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
 805
 806                 /*  2. set CCK test mode off, set to CCK normal mode */
 807                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 808
 809                 /*  3. turn on scramble setting */
 810                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 811                 /*  4. Turn On Continue Tx and turn off the other test modes. */
 812                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
 813                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 814                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 815
 816                 /* for dynamic set Power index. */
 817                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 818                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 819
 820         } else {
 821                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
 822                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 823                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 824                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 825                 /* Delay 10 ms */
 826                 rtw_msleep_os(10);
 827                 /* BB Reset */
 828                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 829                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 830
 831                 /* Stop for dynamic set Power index. */
 832                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 833                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 834         }
 835
 836         pAdapter->mppriv.MptCtx.bCckContTx = false;
 837         pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
 838 } /* mpt_StartOfdmContTx */
 839
 840 void Hal_SetContinuousTx(struct adapter *pAdapter, u8 bStart)
 841 {
 842         RT_TRACE(_module_mp_, _drv_info_,
 843                  ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
 844
 845         pAdapter->mppriv.MptCtx.bStartContTx = bStart;
 846         if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
 847                 Hal_SetCCKContinuousTx(pAdapter, bStart);
 848         else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
 849                  (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
 850                 Hal_SetOFDMContinuousTx(pAdapter, bStart);
 851 }