1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
6 #include "../include/linux/firmware.h"
7 #include "../include/drv_types.h"
8 #include "../include/rtw_efuse.h"
9 #include "../include/rtl8188e_hal.h"
10 #include "../include/rtw_iol.h"
11 #include "../include/usb_ops.h"
13 static void iol_mode_enable(struct adapter *padapter, u8 enable)
18 /* Enable initial offload */
19 reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
20 rtw_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN);
22 if (!padapter->bFWReady) {
23 DBG_88E("bFWReady == false call reset 8051...\n");
24 _8051Reset88E(padapter);
28 /* disable initial offload */
29 reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
30 rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
34 static s32 iol_execute(struct adapter *padapter, u8 control)
38 u32 start = 0, passing_time = 0;
40 control = control&0x0f;
41 reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
42 rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88|control);
45 while ((reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0)) & control &&
46 (passing_time = rtw_get_passing_time_ms(start)) < 1000) {
50 reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
51 status = (reg_0x88 & control) ? _FAIL : _SUCCESS;
52 if (reg_0x88 & control<<4)
57 static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
60 iol_mode_enable(padapter, 1);
61 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
62 rst = iol_execute(padapter, CMD_INIT_LLT);
63 iol_mode_enable(padapter, 0);
68 efuse_phymap_to_logical(u8 *phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
75 u16 **eFuseWord = NULL;
76 u16 efuse_utilized = 0;
79 efuseTbl = (u8 *)rtw_zmalloc(EFUSE_MAP_LEN_88E);
80 if (efuseTbl == NULL) {
81 DBG_88E("%s: alloc efuseTbl fail!\n", __func__);
85 eFuseWord = (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
86 if (eFuseWord == NULL) {
87 DBG_88E("%s: alloc eFuseWord fail!\n", __func__);
91 /* 0. Refresh efuse init map as all oxFF. */
92 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
93 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
94 eFuseWord[i][j] = 0xFFFF;
97 /* 1. Read the first byte to check if efuse is empty!!! */
100 rtemp8 = *(phymap+eFuse_Addr);
101 if (rtemp8 != 0xFF) {
105 DBG_88E("EFUSE is empty efuse_Addr-%d efuse_data =%x\n", eFuse_Addr, rtemp8);
110 /* 2. Read real efuse content. Filter PG header and every section data. */
112 while ((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
113 /* Check PG header for section num. */
114 if ((rtemp8 & 0x1F) == 0x0F) { /* extended header */
115 u1temp = ((rtemp8 & 0xE0) >> 5);
116 rtemp8 = *(phymap+eFuse_Addr);
117 if ((rtemp8 & 0x0F) == 0x0F) {
119 rtemp8 = *(phymap+eFuse_Addr);
121 if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
125 offset = ((rtemp8 & 0xF0) >> 1) | u1temp;
126 wren = (rtemp8 & 0x0F);
130 offset = ((rtemp8 >> 4) & 0x0f);
131 wren = (rtemp8 & 0x0f);
134 if (offset < EFUSE_MAX_SECTION_88E) {
135 /* Get word enable value from PG header */
136 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
137 /* Check word enable condition in the section */
138 if (!(wren & 0x01)) {
139 rtemp8 = *(phymap+eFuse_Addr);
142 eFuseWord[offset][i] = (rtemp8 & 0xff);
143 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
145 rtemp8 = *(phymap+eFuse_Addr);
148 eFuseWord[offset][i] |= (((u16)rtemp8 << 8) & 0xff00);
150 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
156 /* Read next PG header */
157 rtemp8 = *(phymap+eFuse_Addr);
159 if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
166 /* 3. Collect 16 sections and 4 word unit into Efuse map. */
168 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) {
169 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
170 efuseTbl[(i*8)+(j*2)] = (eFuseWord[i][j] & 0xff);
171 efuseTbl[(i*8)+((j*2)+1)] = ((eFuseWord[i][j] >> 8) & 0xff);
176 /* 4. Copy from Efuse map to output pointer memory!!! */
178 for (i = 0; i < _size_byte; i++)
179 pbuf[i] = efuseTbl[_offset+i];
182 /* 5. Calculate Efuse utilization. */
190 static void efuse_read_phymap_from_txpktbuf(
191 struct adapter *adapter,
192 int bcnhead, /* beacon head, where FW store len(2-byte) and efuse physical map. */
193 u8 *content, /* buffer to store efuse physical map */
194 u16 *size /* for efuse content: the max byte to read. will update to byte read */
198 u32 start = 0, passing_time = 0;
200 __le32 lo32 = 0, hi32 = 0;
201 u16 len = 0, count = 0;
207 if (bcnhead < 0) /* if not valid */
208 bcnhead = rtw_read8(adapter, REG_TDECTRL+1);
210 DBG_88E("%s bcnhead:%d\n", __func__, bcnhead);
212 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
214 dbg_addr = bcnhead*128/8; /* 8-bytes addressing */
217 rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, dbg_addr+i);
219 rtw_write8(adapter, REG_TXPKTBUF_DBG, 0);
221 while (!(reg_0x143 = rtw_read8(adapter, REG_TXPKTBUF_DBG)) &&
222 (passing_time = rtw_get_passing_time_ms(start)) < 1000) {
223 DBG_88E("%s polling reg_0x143:0x%02x, reg_0x106:0x%02x\n", __func__, reg_0x143, rtw_read8(adapter, 0x106));
227 /* data from EEPROM needs to be in LE */
228 lo32 = cpu_to_le32(rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L));
229 hi32 = cpu_to_le32(rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H));
232 /* Although lenc is only used in a debug statement,
233 * do not remove it as the rtw_read16() call consumes
234 * 2 bytes from the EEPROM source.
236 u16 lenc = rtw_read16(adapter, REG_PKTBUF_DBG_DATA_L);
238 len = le32_to_cpu(lo32) & 0x0000ffff;
240 limit = (len-2 < limit) ? len-2 : limit;
242 DBG_88E("%s len:%u, lenc:%u\n", __func__, len, lenc);
244 memcpy(pos, ((u8 *)&lo32)+2, (limit >= count+2) ? 2 : limit-count);
245 count += (limit >= count+2) ? 2 : limit-count;
248 memcpy(pos, ((u8 *)&lo32), (limit >= count+4) ? 4 : limit-count);
249 count += (limit >= count+4) ? 4 : limit-count;
253 if (limit > count && len-2 > count) {
254 memcpy(pos, (u8 *)&hi32, (limit >= count+4) ? 4 : limit-count);
255 count += (limit >= count+4) ? 4 : limit-count;
259 if (limit <= count || len-2 <= count)
263 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
264 DBG_88E("%s read count:%u\n", __func__, count);
268 static s32 iol_read_efuse(struct adapter *padapter, u8 txpktbuf_bndy, u16 offset, u16 size_byte, u8 *logical_map)
271 u8 physical_map[512];
274 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
275 memset(physical_map, 0xFF, 512);
276 rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
277 status = iol_execute(padapter, CMD_READ_EFUSE_MAP);
278 if (status == _SUCCESS)
279 efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size);
280 efuse_phymap_to_logical(physical_map, offset, size_byte, logical_map);
284 s32 rtl8188e_iol_efuse_patch(struct adapter *padapter)
286 s32 result = _SUCCESS;
288 DBG_88E("==> %s\n", __func__);
289 if (rtw_IOL_applied(padapter)) {
290 iol_mode_enable(padapter, 1);
291 result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
292 if (result == _SUCCESS)
293 result = iol_execute(padapter, CMD_EFUSE_PATCH);
295 iol_mode_enable(padapter, 0);
300 static s32 iol_ioconfig(struct adapter *padapter, u8 iocfg_bndy)
304 rtw_write8(padapter, REG_TDECTRL+1, iocfg_bndy);
305 rst = iol_execute(padapter, CMD_IOCONFIG);
309 static int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
311 struct pkt_attrib *pattrib = &xmit_frame->attrib;
315 if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
317 if (rtw_usb_bulk_size_boundary(adapter, TXDESC_SIZE+pattrib->last_txcmdsz)) {
318 if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
322 dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
324 iol_mode_enable(adapter, 1);
325 for (i = 0; i < bndy_cnt; i++) {
328 ret = iol_ioconfig(adapter, page_no);
332 iol_mode_enable(adapter, 0);
334 /* restore BCN_HEAD */
335 rtw_write8(adapter, REG_TDECTRL+1, 0);
339 void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter, int data_len)
341 u32 fifo_data, reg_140;
342 u32 addr, rstatus, loop = 0;
343 u16 data_cnts = (data_len/8)+1;
344 u8 *pbuf = rtw_zvmalloc(data_len+10);
345 DBG_88E("###### %s ######\n", __func__);
347 rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
349 for (addr = 0; addr < data_cnts; addr++) {
350 rtw_write32(Adapter, 0x140, addr);
354 rstatus = (reg_140 = rtw_read32(Adapter, REG_PKTBUF_DBG_CTRL)&BIT24);
356 fifo_data = rtw_read32(Adapter, REG_PKTBUF_DBG_DATA_L);
357 memcpy(pbuf+(addr*8), &fifo_data, 4);
359 fifo_data = rtw_read32(Adapter, REG_PKTBUF_DBG_DATA_H);
360 memcpy(pbuf+(addr*8+4), &fifo_data, 4);
363 } while (!rstatus && (loop++ < 10));
365 rtw_IOL_cmd_buf_dump(Adapter, data_len, pbuf);
366 rtw_vmfree(pbuf, data_len+10);
368 DBG_88E("###### %s ######\n", __func__);
371 static void _FWDownloadEnable(struct adapter *padapter, bool enable)
376 /* MCU firmware download enable. */
377 tmp = rtw_read8(padapter, REG_MCUFWDL);
378 rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
381 tmp = rtw_read8(padapter, REG_MCUFWDL+2);
382 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
384 /* MCU firmware download disable. */
385 tmp = rtw_read8(padapter, REG_MCUFWDL);
386 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
388 /* Reserved for fw extension. */
389 rtw_write8(padapter, REG_MCUFWDL+1, 0x00);
393 #define MAX_REG_BOLCK_SIZE 196
395 static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)
398 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
399 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
400 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */
401 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
402 u32 remainSize_p1 = 0, remainSize_p2 = 0;
403 u8 *bufferPtr = (u8 *)buffer;
404 u32 i = 0, offset = 0;
406 blockSize_p1 = MAX_REG_BOLCK_SIZE;
409 blockCount_p1 = buffSize / blockSize_p1;
410 remainSize_p1 = buffSize % blockSize_p1;
413 RT_TRACE(_module_hal_init_c_, _drv_notice_,
414 ("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n",
415 buffSize, blockSize_p1, blockCount_p1, remainSize_p1));
418 for (i = 0; i < blockCount_p1; i++) {
419 ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
426 offset = blockCount_p1 * blockSize_p1;
428 blockCount_p2 = remainSize_p1/blockSize_p2;
429 remainSize_p2 = remainSize_p1%blockSize_p2;
432 RT_TRACE(_module_hal_init_c_, _drv_notice_,
433 ("_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n",
434 (buffSize-offset), blockSize_p2, blockCount_p2, remainSize_p2));
437 for (i = 0; i < blockCount_p2; i++) {
438 ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + offset + i*blockSize_p2), blockSize_p2, (bufferPtr + offset + i*blockSize_p2));
447 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
449 blockCount_p3 = remainSize_p2 / blockSize_p3;
451 RT_TRACE(_module_hal_init_c_, _drv_notice_,
452 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
453 (buffSize-offset), blockSize_p3, blockCount_p3));
455 for (i = 0; i < blockCount_p3; i++) {
456 ret = rtw_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
467 static int _PageWrite(struct adapter *padapter, u32 page, void *buffer, u32 size)
470 u8 u8Page = (u8)(page & 0x07);
472 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page;
473 rtw_write8(padapter, REG_MCUFWDL+2, value8);
475 return _BlockWrite(padapter, buffer, size);
478 static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)
480 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
481 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
483 u32 pageNums, remainSize;
485 u8 *bufferPtr = (u8 *)buffer;
487 pageNums = size / MAX_PAGE_SIZE;
488 remainSize = size % MAX_PAGE_SIZE;
490 for (page = 0; page < pageNums; page++) {
491 offset = page * MAX_PAGE_SIZE;
492 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_PAGE_SIZE);
498 offset = pageNums * MAX_PAGE_SIZE;
500 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
505 RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n"));
510 void _8051Reset88E(struct adapter *padapter)
514 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
515 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
516 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2));
517 DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n");
520 static s32 _FWFreeToGo(struct adapter *padapter)
525 /* polling CheckSum report */
527 value32 = rtw_read32(padapter, REG_MCUFWDL);
528 if (value32 & FWDL_ChkSum_rpt)
530 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
532 if (counter >= POLLING_READY_TIMEOUT_COUNT) {
533 DBG_88E("%s: chksum report fail! REG_MCUFWDL:0x%08x\n", __func__, value32);
536 DBG_88E("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__, value32);
538 value32 = rtw_read32(padapter, REG_MCUFWDL);
539 value32 |= MCUFWDL_RDY;
540 value32 &= ~WINTINI_RDY;
541 rtw_write32(padapter, REG_MCUFWDL, value32);
543 _8051Reset88E(padapter);
545 /* polling for FW ready */
548 value32 = rtw_read32(padapter, REG_MCUFWDL);
549 if (value32 & WINTINI_RDY) {
550 DBG_88E("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __func__, value32);
554 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
556 DBG_88E("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __func__, value32);
560 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
562 static int load_firmware(struct rt_firmware *pFirmware, struct device *device)
564 s32 rtStatus = _SUCCESS;
565 const struct firmware *fw;
566 const char *fw_name = "rtlwifi/rtl8188eufw.bin";
567 int err = request_firmware(&fw, fw_name, device);
570 pr_err("Request firmware failed with error 0x%x\n", err);
575 pr_err("Firmware %s not available\n", fw_name);
579 if (fw->size > FW_8188E_SIZE) {
581 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE));
585 pFirmware->szFwBuffer = kzalloc(FW_8188E_SIZE, GFP_KERNEL);
586 if (!pFirmware->szFwBuffer) {
587 pr_err("Failed to allocate pFirmware->szFwBuffer\n");
591 memcpy(pFirmware->szFwBuffer, fw->data, fw->size);
592 pFirmware->ulFwLength = fw->size;
593 release_firmware(fw);
594 DBG_88E_LEVEL(_drv_info_, "+%s: !bUsedWoWLANFw, FmrmwareLen:%d+\n", __func__, pFirmware->ulFwLength);
600 s32 rtl8188e_FirmwareDownload(struct adapter *padapter)
602 s32 rtStatus = _SUCCESS;
603 u8 writeFW_retry = 0;
605 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
606 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
607 struct device *device = dvobj_to_dev(dvobj);
608 struct rt_firmware_hdr *pFwHdr = NULL;
611 static int log_version;
613 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__));
614 if (!dvobj->firmware.szFwBuffer)
615 rtStatus = load_firmware(&dvobj->firmware, device);
616 if (rtStatus == _FAIL) {
617 dvobj->firmware.szFwBuffer = NULL;
620 pFirmwareBuf = dvobj->firmware.szFwBuffer;
621 FirmwareLen = dvobj->firmware.ulFwLength;
623 /* To Check Fw header. Added by tynli. 2009.12.04. */
624 pFwHdr = (struct rt_firmware_hdr *)dvobj->firmware.szFwBuffer;
626 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
627 pHalData->FirmwareSubVersion = pFwHdr->Subversion;
628 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
631 pr_info("%sFirmware Version %d, SubVersion %d, Signature 0x%x\n",
632 DRIVER_PREFIX, pHalData->FirmwareVersion,
633 pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);
635 if (IS_FW_HEADER_EXIST(pFwHdr)) {
636 /* Shift 32 bytes for FW header */
637 pFirmwareBuf = pFirmwareBuf + 32;
638 FirmwareLen = FirmwareLen - 32;
641 /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */
642 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
643 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */
644 rtw_write8(padapter, REG_MCUFWDL, 0x00);
645 _8051Reset88E(padapter);
648 _FWDownloadEnable(padapter, true);
649 fwdl_start_time = jiffies;
651 /* reset the FWDL chksum */
652 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt);
654 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
656 if (rtStatus == _SUCCESS ||
657 (rtw_get_passing_time_ms(fwdl_start_time) > 500 && writeFW_retry++ >= 3))
660 DBG_88E("%s writeFW_retry:%u, time after fwdl_start_time:%ums\n",
661 __func__, writeFW_retry, rtw_get_passing_time_ms(fwdl_start_time)
664 _FWDownloadEnable(padapter, false);
665 if (_SUCCESS != rtStatus) {
666 DBG_88E("DL Firmware failed!\n");
670 rtStatus = _FWFreeToGo(padapter);
671 if (_SUCCESS != rtStatus) {
672 DBG_88E("DL Firmware failed!\n");
675 RT_TRACE(_module_hal_init_c_, _drv_info_, ("Firmware is ready to run!\n"));
681 void rtl8188e_InitializeFirmwareVars(struct adapter *padapter)
683 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
685 /* Init Fw LPS related. */
686 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
688 /* Init H2C counter. by tynli. 2009.12.09. */
689 pHalData->LastHMEBoxNum = 0;
692 static void rtl8188e_free_hal_data(struct adapter *padapter)
695 kfree(padapter->HalData);
696 padapter->HalData = NULL;
701 /* Efuse related code */
709 hal_EfusePgPacketWrite2ByteHeader(
710 struct adapter *pAdapter,
713 struct pgpkt *pTargetPkt,
716 hal_EfusePgPacketWrite1ByteHeader(
717 struct adapter *pAdapter,
720 struct pgpkt *pTargetPkt,
723 hal_EfusePgPacketWriteData(
724 struct adapter *pAdapter,
727 struct pgpkt *pTargetPkt,
731 hal_EfusePowerSwitch_RTL8188E(
732 struct adapter *pAdapter,
740 rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
742 /* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid */
743 tmpV16 = rtw_read16(pAdapter, REG_SYS_ISO_CTRL);
744 if (!(tmpV16 & PWC_EV12V)) {
746 rtw_write16(pAdapter, REG_SYS_ISO_CTRL, tmpV16);
748 /* Reset: 0x0000h[28], default valid */
749 tmpV16 = rtw_read16(pAdapter, REG_SYS_FUNC_EN);
750 if (!(tmpV16 & FEN_ELDR)) {
752 rtw_write16(pAdapter, REG_SYS_FUNC_EN, tmpV16);
755 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
756 tmpV16 = rtw_read16(pAdapter, REG_SYS_CLKR);
757 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
758 tmpV16 |= (LOADER_CLK_EN | ANA8M);
759 rtw_write16(pAdapter, REG_SYS_CLKR, tmpV16);
763 /* Enable LDO 2.5V before read/write action */
764 tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
766 tempval |= (VOLTAGE_V25 << 4);
767 rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80));
770 rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
773 /* Disable LDO 2.5V after read/write action */
774 tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
775 rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F));
781 rtl8188e_EfusePowerSwitch(
782 struct adapter *pAdapter,
786 hal_EfusePowerSwitch_RTL8188E(pAdapter, bWrite, PwrState);
789 static void Hal_EfuseReadEFuse88E(struct adapter *Adapter,
801 u16 **eFuseWord = NULL;
802 u16 efuse_utilized = 0;
806 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
808 if ((_offset + _size_byte) > EFUSE_MAP_LEN_88E) {/* total E-Fuse table is 512bytes */
809 DBG_88E("Hal_EfuseReadEFuse88E(): Invalid offset(%#x) with read bytes(%#x)!!\n", _offset, _size_byte);
813 efuseTbl = (u8 *)rtw_zmalloc(EFUSE_MAP_LEN_88E);
814 if (efuseTbl == NULL) {
815 DBG_88E("%s: alloc efuseTbl fail!\n", __func__);
819 eFuseWord = (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
820 if (eFuseWord == NULL) {
821 DBG_88E("%s: alloc eFuseWord fail!\n", __func__);
825 /* 0. Refresh efuse init map as all oxFF. */
826 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
827 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
828 eFuseWord[i][j] = 0xFFFF;
831 /* 1. Read the first byte to check if efuse is empty!!! */
834 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
835 if (*rtemp8 != 0xFF) {
839 DBG_88E("EFUSE is empty efuse_Addr-%d efuse_data =%x\n", eFuse_Addr, *rtemp8);
844 /* 2. Read real efuse content. Filter PG header and every section data. */
846 while ((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
847 /* Check PG header for section num. */
848 if ((*rtemp8 & 0x1F) == 0x0F) { /* extended header */
849 u1temp = ((*rtemp8 & 0xE0) >> 5);
851 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
853 if ((*rtemp8 & 0x0F) == 0x0F) {
855 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
857 if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
861 offset = ((*rtemp8 & 0xF0) >> 1) | u1temp;
862 wren = (*rtemp8 & 0x0F);
866 offset = ((*rtemp8 >> 4) & 0x0f);
867 wren = (*rtemp8 & 0x0f);
870 if (offset < EFUSE_MAX_SECTION_88E) {
871 /* Get word enable value from PG header */
873 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
874 /* Check word enable condition in the section */
875 if (!(wren & 0x01)) {
876 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
879 eFuseWord[offset][i] = (*rtemp8 & 0xff);
880 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
882 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
885 eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00);
886 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
893 /* Read next PG header */
894 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
896 if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
902 /* 3. Collect 16 sections and 4 word unit into Efuse map. */
903 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) {
904 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
905 efuseTbl[(i*8)+(j*2)] = (eFuseWord[i][j] & 0xff);
906 efuseTbl[(i*8)+((j*2)+1)] = ((eFuseWord[i][j] >> 8) & 0xff);
910 /* 4. Copy from Efuse map to output pointer memory!!! */
911 for (i = 0; i < _size_byte; i++)
912 pbuf[i] = efuseTbl[_offset+i];
914 /* 5. Calculate Efuse utilization. */
915 rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr);
922 static void ReadEFuseByIC(struct adapter *Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest)
926 if (rtw_IOL_applied(Adapter)) {
927 rtw_hal_power_on(Adapter);
929 iol_mode_enable(Adapter, 1);
930 ret = iol_read_efuse(Adapter, 0, _offset, _size_byte, pbuf);
931 iol_mode_enable(Adapter, 0);
937 Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
943 static void ReadEFuse_Pseudo(struct adapter *Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest)
945 Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
948 static void rtl8188e_ReadEFuse(struct adapter *Adapter, u8 efuseType,
949 u16 _offset, u16 _size_byte, u8 *pbuf,
953 ReadEFuse_Pseudo (Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
955 ReadEFuseByIC(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
958 /* Do not support BT */
959 static void Hal_EFUSEGetEfuseDefinition88E(struct adapter *pAdapter, u8 efuseType, u8 type, void *pOut)
962 case TYPE_EFUSE_MAX_SECTION:
965 pMax_section = (u8 *)pOut;
966 *pMax_section = EFUSE_MAX_SECTION_88E;
969 case TYPE_EFUSE_REAL_CONTENT_LEN:
972 pu2Tmp = (u16 *)pOut;
973 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
976 case TYPE_EFUSE_CONTENT_LEN_BANK:
979 pu2Tmp = (u16 *)pOut;
980 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
983 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
986 pu2Tmp = (u16 *)pOut;
987 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
990 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
993 pu2Tmp = (u16 *)pOut;
994 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
997 case TYPE_EFUSE_MAP_LEN:
1000 pu2Tmp = (u16 *)pOut;
1001 *pu2Tmp = (u16)EFUSE_MAP_LEN_88E;
1004 case TYPE_EFUSE_PROTECT_BYTES_BANK:
1007 pu1Tmp = (u8 *)pOut;
1008 *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
1014 pu1Tmp = (u8 *)pOut;
1021 static void Hal_EFUSEGetEfuseDefinition_Pseudo88E(struct adapter *pAdapter, u8 efuseType, u8 type, void *pOut)
1024 case TYPE_EFUSE_MAX_SECTION:
1027 pMax_section = (u8 *)pOut;
1028 *pMax_section = EFUSE_MAX_SECTION_88E;
1031 case TYPE_EFUSE_REAL_CONTENT_LEN:
1034 pu2Tmp = (u16 *)pOut;
1035 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1038 case TYPE_EFUSE_CONTENT_LEN_BANK:
1041 pu2Tmp = (u16 *)pOut;
1042 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1045 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
1048 pu2Tmp = (u16 *)pOut;
1049 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1052 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
1055 pu2Tmp = (u16 *)pOut;
1056 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1059 case TYPE_EFUSE_MAP_LEN:
1062 pu2Tmp = (u16 *)pOut;
1063 *pu2Tmp = (u16)EFUSE_MAP_LEN_88E;
1066 case TYPE_EFUSE_PROTECT_BYTES_BANK:
1069 pu1Tmp = (u8 *)pOut;
1070 *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
1076 pu1Tmp = (u8 *)pOut;
1083 static void rtl8188e_EFUSE_GetEfuseDefinition(struct adapter *pAdapter, u8 efuseType, u8 type, void *pOut, bool bPseudoTest)
1086 Hal_EFUSEGetEfuseDefinition_Pseudo88E(pAdapter, efuseType, type, pOut);
1088 Hal_EFUSEGetEfuseDefinition88E(pAdapter, efuseType, type, pOut);
1091 static u8 Hal_EfuseWordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest)
1094 u16 start_addr = efuse_addr;
1095 u8 badworden = 0x0F;
1098 memset((void *)tmpdata, 0xff, PGPKT_DATA_SIZE);
1100 if (!(word_en&BIT0)) {
1101 tmpaddr = start_addr;
1102 efuse_OneByteWrite(pAdapter, start_addr++, data[0], bPseudoTest);
1103 efuse_OneByteWrite(pAdapter, start_addr++, data[1], bPseudoTest);
1105 efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[0], bPseudoTest);
1106 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[1], bPseudoTest);
1107 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
1108 badworden &= (~BIT0);
1110 if (!(word_en&BIT1)) {
1111 tmpaddr = start_addr;
1112 efuse_OneByteWrite(pAdapter, start_addr++, data[2], bPseudoTest);
1113 efuse_OneByteWrite(pAdapter, start_addr++, data[3], bPseudoTest);
1115 efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[2], bPseudoTest);
1116 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[3], bPseudoTest);
1117 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
1118 badworden &= (~BIT1);
1120 if (!(word_en&BIT2)) {
1121 tmpaddr = start_addr;
1122 efuse_OneByteWrite(pAdapter, start_addr++, data[4], bPseudoTest);
1123 efuse_OneByteWrite(pAdapter, start_addr++, data[5], bPseudoTest);
1125 efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[4], bPseudoTest);
1126 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[5], bPseudoTest);
1127 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
1128 badworden &= (~BIT2);
1130 if (!(word_en&BIT3)) {
1131 tmpaddr = start_addr;
1132 efuse_OneByteWrite(pAdapter, start_addr++, data[6], bPseudoTest);
1133 efuse_OneByteWrite(pAdapter, start_addr++, data[7], bPseudoTest);
1135 efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[6], bPseudoTest);
1136 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[7], bPseudoTest);
1137 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
1138 badworden &= (~BIT3);
1143 static u8 Hal_EfuseWordEnableDataWrite_Pseudo(struct adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest)
1147 ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
1151 static u8 rtl8188e_Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest)
1156 ret = Hal_EfuseWordEnableDataWrite_Pseudo (pAdapter, efuse_addr, word_en, data, bPseudoTest);
1158 ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
1162 static u16 hal_EfuseGetCurrentSize_8188e(struct adapter *pAdapter, bool bPseudoTest)
1164 int bContinual = true;
1166 u8 hoffset = 0, hworden = 0;
1167 u8 efuse_data, word_cnts = 0;
1170 efuse_addr = (u16)(fakeEfuseUsedBytes);
1172 rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1174 while (bContinual &&
1175 efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest) &&
1176 AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1177 if (efuse_data != 0xFF) {
1178 if ((efuse_data&0x1F) == 0x0F) { /* extended header */
1179 hoffset = efuse_data;
1181 efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest);
1182 if ((efuse_data & 0x0F) == 0x0F) {
1186 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1187 hworden = efuse_data & 0x0F;
1190 hoffset = (efuse_data>>4) & 0x0F;
1191 hworden = efuse_data & 0x0F;
1193 word_cnts = Efuse_CalculateWordCnts(hworden);
1194 /* read next header */
1195 efuse_addr = efuse_addr + (word_cnts*2)+1;
1202 fakeEfuseUsedBytes = efuse_addr;
1204 rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1209 static u16 Hal_EfuseGetCurrentSize_Pseudo(struct adapter *pAdapter, bool bPseudoTest)
1213 ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
1217 static u16 rtl8188e_EfuseGetCurrentSize(struct adapter *pAdapter, u8 efuseType, bool bPseudoTest)
1222 ret = Hal_EfuseGetCurrentSize_Pseudo(pAdapter, bPseudoTest);
1224 ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
1228 static int hal_EfusePgPacketRead_8188e(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1230 u8 ReadState = PG_STATE_HEADER;
1231 int bContinual = true;
1232 int bDataEmpty = true;
1233 u8 efuse_data, word_cnts = 0;
1235 u8 hoffset = 0, hworden = 0;
1241 EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, (void *)&max_section, bPseudoTest);
1245 if (offset > max_section)
1248 memset((void *)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
1249 memset((void *)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
1251 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */
1252 /* Skip dummy parts to prevent unexpected data read from Efuse. */
1253 /* By pass right now. 2009.02.19. */
1254 while (bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1255 /* Header Read ------------- */
1256 if (ReadState & PG_STATE_HEADER) {
1257 if (efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
1258 if (EXT_HEADER(efuse_data)) {
1259 tmp_header = efuse_data;
1261 efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest);
1262 if (!ALL_WORDS_DISABLED(efuse_data)) {
1263 hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1264 hworden = efuse_data & 0x0F;
1266 DBG_88E("Error, All words disabled\n");
1271 hoffset = (efuse_data>>4) & 0x0F;
1272 hworden = efuse_data & 0x0F;
1274 word_cnts = Efuse_CalculateWordCnts(hworden);
1277 if (hoffset == offset) {
1278 for (tmpidx = 0; tmpidx < word_cnts*2; tmpidx++) {
1279 if (efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx, &efuse_data, bPseudoTest)) {
1280 tmpdata[tmpidx] = efuse_data;
1281 if (efuse_data != 0xff)
1285 if (bDataEmpty == false) {
1286 ReadState = PG_STATE_DATA;
1287 } else {/* read next header */
1288 efuse_addr = efuse_addr + (word_cnts*2)+1;
1289 ReadState = PG_STATE_HEADER;
1291 } else {/* read next header */
1292 efuse_addr = efuse_addr + (word_cnts*2)+1;
1293 ReadState = PG_STATE_HEADER;
1298 } else if (ReadState & PG_STATE_DATA) {
1299 /* Data section Read ------------- */
1300 efuse_WordEnableDataRead(hworden, tmpdata, data);
1301 efuse_addr = efuse_addr + (word_cnts*2)+1;
1302 ReadState = PG_STATE_HEADER;
1307 if ((data[0] == 0xff) && (data[1] == 0xff) && (data[2] == 0xff) && (data[3] == 0xff) &&
1308 (data[4] == 0xff) && (data[5] == 0xff) && (data[6] == 0xff) && (data[7] == 0xff))
1314 static int Hal_EfusePgPacketRead(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1318 ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
1322 static int Hal_EfusePgPacketRead_Pseudo(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1326 ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
1330 static int rtl8188e_Efuse_PgPacketRead(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1335 ret = Hal_EfusePgPacketRead_Pseudo (pAdapter, offset, data, bPseudoTest);
1337 ret = Hal_EfusePgPacketRead(pAdapter, offset, data, bPseudoTest);
1341 static bool hal_EfuseFixHeaderProcess(struct adapter *pAdapter, u8 efuseType, struct pgpkt *pFixPkt, u16 *pAddr, bool bPseudoTest)
1343 u8 originaldata[8], badworden = 0;
1344 u16 efuse_addr = *pAddr;
1345 u32 PgWriteSuccess = 0;
1347 memset((void *)originaldata, 0xff, 8);
1349 if (Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) {
1350 /* check if data exist */
1351 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
1353 if (badworden != 0xf) { /* write fail */
1354 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
1356 if (!PgWriteSuccess)
1359 efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
1361 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) + 1;
1364 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) + 1;
1366 *pAddr = efuse_addr;
1370 static bool hal_EfusePgPacketWrite2ByteHeader(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1373 u16 efuse_addr = *pAddr, efuse_max_available_len = 0;
1374 u8 pg_header = 0, tmp_header = 0, pg_header_temp = 0;
1377 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (void *)&efuse_max_available_len, bPseudoTest);
1379 while (efuse_addr < efuse_max_available_len) {
1380 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
1381 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1382 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1384 while (tmp_header == 0xFF) {
1385 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
1388 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1389 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1392 /* to write ext_header */
1393 if (tmp_header == pg_header) {
1395 pg_header_temp = pg_header;
1396 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
1398 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1399 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1401 while (tmp_header == 0xFF) {
1402 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
1405 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1406 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1409 if ((tmp_header & 0x0F) == 0x0F) { /* word_en PG fail */
1410 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1416 } else if (pg_header != tmp_header) { /* offset PG fail */
1417 struct pgpkt fixPkt;
1418 fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
1419 fixPkt.word_en = tmp_header & 0x0F;
1420 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
1421 if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
1427 } else if ((tmp_header & 0x1F) == 0x0F) { /* wrong extended header */
1433 *pAddr = efuse_addr;
1437 static bool hal_EfusePgPacketWrite1ByteHeader(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1440 u8 pg_header = 0, tmp_header = 0;
1441 u16 efuse_addr = *pAddr;
1444 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
1446 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1447 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1449 while (tmp_header == 0xFF) {
1450 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
1452 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1453 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1456 if (pg_header == tmp_header) {
1459 struct pgpkt fixPkt;
1460 fixPkt.offset = (tmp_header>>4) & 0x0F;
1461 fixPkt.word_en = tmp_header & 0x0F;
1462 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
1463 if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
1467 *pAddr = efuse_addr;
1471 static bool hal_EfusePgPacketWriteData(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1473 u16 efuse_addr = *pAddr;
1475 u32 PgWriteSuccess = 0;
1478 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
1479 if (badworden == 0x0F) {
1483 /* reorganize other pg packet */
1484 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1485 if (!PgWriteSuccess)
1493 hal_EfusePgPacketWriteHeader(
1494 struct adapter *pAdapter,
1497 struct pgpkt *pTargetPkt,
1502 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
1503 bRet = hal_EfusePgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1505 bRet = hal_EfusePgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1510 static bool wordEnMatched(struct pgpkt *pTargetPkt, struct pgpkt *pCurPkt,
1513 u8 match_word_en = 0x0F; /* default all words are disabled */
1515 /* check if the same words are enabled both target and current PG packet */
1516 if (((pTargetPkt->word_en & BIT0) == 0) &&
1517 ((pCurPkt->word_en & BIT0) == 0))
1518 match_word_en &= ~BIT0; /* enable word 0 */
1519 if (((pTargetPkt->word_en & BIT1) == 0) &&
1520 ((pCurPkt->word_en & BIT1) == 0))
1521 match_word_en &= ~BIT1; /* enable word 1 */
1522 if (((pTargetPkt->word_en & BIT2) == 0) &&
1523 ((pCurPkt->word_en & BIT2) == 0))
1524 match_word_en &= ~BIT2; /* enable word 2 */
1525 if (((pTargetPkt->word_en & BIT3) == 0) &&
1526 ((pCurPkt->word_en & BIT3) == 0))
1527 match_word_en &= ~BIT3; /* enable word 3 */
1529 *pWden = match_word_en;
1531 if (match_word_en != 0xf)
1537 static bool hal_EfuseCheckIfDatafollowed(struct adapter *pAdapter, u8 word_cnts, u16 startAddr, bool bPseudoTest)
1542 for (i = 0; i < (word_cnts*2); i++) {
1543 if (efuse_OneByteRead(pAdapter, (startAddr+i), &efuse_data, bPseudoTest) && (efuse_data != 0xFF))
1549 static bool hal_EfusePartialWriteCheck(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1552 u8 i, efuse_data = 0, cur_header = 0;
1553 u8 matched_wden = 0, badworden = 0;
1554 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
1555 struct pgpkt curPkt;
1557 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (void *)&efuse_max_available_len, bPseudoTest);
1558 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&efuse_max, bPseudoTest);
1560 if (efuseType == EFUSE_WIFI) {
1562 startAddr = (u16)(fakeEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
1564 rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
1565 startAddr %= EFUSE_REAL_CONTENT_LEN;
1569 startAddr = (u16)(fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
1571 startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
1575 if (startAddr >= efuse_max_available_len) {
1580 if (efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
1581 if (EXT_HEADER(efuse_data)) {
1582 cur_header = efuse_data;
1584 efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest);
1585 if (ALL_WORDS_DISABLED(efuse_data)) {
1589 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1590 curPkt.word_en = efuse_data & 0x0F;
1593 cur_header = efuse_data;
1594 curPkt.offset = (cur_header>>4) & 0x0F;
1595 curPkt.word_en = cur_header & 0x0F;
1598 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
1599 /* if same header is found but no data followed */
1600 /* write some part of data followed by the header. */
1601 if ((curPkt.offset == pTargetPkt->offset) &&
1602 (!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) &&
1603 wordEnMatched(pTargetPkt, &curPkt, &matched_wden)) {
1604 /* Here to write partial data */
1605 badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest);
1606 if (badworden != 0x0F) {
1607 u32 PgWriteSuccess = 0;
1608 /* if write fail on some words, write these bad words again */
1610 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1612 if (!PgWriteSuccess) {
1613 bRet = false; /* write fail, return */
1617 /* partial write ok, update the target packet for later use */
1618 for (i = 0; i < 4; i++) {
1619 if ((matched_wden & (0x1<<i)) == 0) /* this word has been written */
1620 pTargetPkt->word_en |= (0x1<<i); /* disable the word */
1622 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1624 /* read from next header */
1625 startAddr = startAddr + (curPkt.word_cnts*2) + 1;
1627 /* not used header, 0xff */
1637 hal_EfusePgCheckAvailableAddr(
1638 struct adapter *pAdapter,
1643 u16 efuse_max_available_len = 0;
1645 /* Change to check TYPE_EFUSE_MAP_LEN , because 8188E raw 256, logic map over 256. */
1646 EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&efuse_max_available_len, false);
1648 if (Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len)
1653 static void hal_EfuseConstructPGPkt(u8 offset, u8 word_en, u8 *pData, struct pgpkt *pTargetPkt)
1655 memset((void *)pTargetPkt->data, 0xFF, sizeof(u8)*8);
1656 pTargetPkt->offset = offset;
1657 pTargetPkt->word_en = word_en;
1658 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
1659 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1662 static bool hal_EfusePgPacketWrite_8188e(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *pData, bool bPseudoTest)
1664 struct pgpkt targetPkt;
1666 u8 efuseType = EFUSE_WIFI;
1668 if (!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
1671 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
1673 if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1676 if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1679 if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1685 static int Hal_EfusePgPacketWrite_Pseudo(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest)
1689 ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
1693 static int Hal_EfusePgPacketWrite(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest)
1696 ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
1701 static int rtl8188e_Efuse_PgPacketWrite(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest)
1706 ret = Hal_EfusePgPacketWrite_Pseudo (pAdapter, offset, word_en, data, bPseudoTest);
1708 ret = Hal_EfusePgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
1712 static struct HAL_VERSION ReadChipVersion8188E(struct adapter *padapter)
1715 struct HAL_VERSION ChipVersion;
1716 struct hal_data_8188e *pHalData;
1718 pHalData = GET_HAL_DATA(padapter);
1720 value32 = rtw_read32(padapter, REG_SYS_CFG);
1721 ChipVersion.ICType = CHIP_8188E;
1722 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
1724 ChipVersion.RFType = RF_TYPE_1T1R;
1725 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
1726 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
1728 /* For regulator mode. by tynli. 2011.01.14 */
1729 pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
1731 ChipVersion.ROMVer = 0; /* ROM code version. */
1732 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
1734 dump_chip_info(ChipVersion);
1736 pHalData->VersionID = ChipVersion;
1738 if (IS_1T2R(ChipVersion)) {
1739 pHalData->rf_type = RF_1T2R;
1740 pHalData->NumTotalRFPath = 2;
1741 } else if (IS_2T2R(ChipVersion)) {
1742 pHalData->rf_type = RF_2T2R;
1743 pHalData->NumTotalRFPath = 2;
1745 pHalData->rf_type = RF_1T1R;
1746 pHalData->NumTotalRFPath = 1;
1749 MSG_88E("RF_Type is %x!!\n", pHalData->rf_type);
1754 static void rtl8188e_read_chip_version(struct adapter *padapter)
1756 ReadChipVersion8188E(padapter);
1759 static void rtl8188e_GetHalODMVar(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
1763 static void rtl8188e_SetHalODMVar(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
1765 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
1766 struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
1767 switch (eVariable) {
1768 case HAL_ODM_STA_INFO:
1770 struct sta_info *psta = (struct sta_info *)pValue1;
1772 DBG_88E("### Set STA_(%d) info\n", psta->mac_id);
1773 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
1774 ODM_RAInfo_Init(podmpriv, psta->mac_id);
1776 DBG_88E("### Clean STA_(%d) info\n", psta->mac_id);
1777 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
1781 case HAL_ODM_P2P_STATE:
1782 ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1784 case HAL_ODM_WIFI_DISPLAY_STATE:
1785 ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1792 void rtl8188e_clone_haldata(struct adapter *dst_adapter, struct adapter *src_adapter)
1794 memcpy(dst_adapter->HalData, src_adapter->HalData, dst_adapter->hal_data_sz);
1797 void rtl8188e_start_thread(struct adapter *padapter)
1801 void rtl8188e_stop_thread(struct adapter *padapter)
1805 static void hal_notch_filter_8188e(struct adapter *adapter, bool enable)
1808 DBG_88E("Enable notch filter\n");
1809 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
1811 DBG_88E("Disable notch filter\n");
1812 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
1815 void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc)
1817 pHalFunc->free_hal_data = &rtl8188e_free_hal_data;
1819 pHalFunc->dm_init = &rtl8188e_init_dm_priv;
1820 pHalFunc->dm_deinit = &rtl8188e_deinit_dm_priv;
1822 pHalFunc->read_chip_version = &rtl8188e_read_chip_version;
1824 pHalFunc->set_bwmode_handler = &PHY_SetBWMode8188E;
1825 pHalFunc->set_channel_handler = &PHY_SwChnl8188E;
1827 pHalFunc->hal_dm_watchdog = &rtl8188e_HalDmWatchDog;
1829 pHalFunc->Add_RateATid = &rtl8188e_Add_RateATid;
1830 pHalFunc->run_thread = &rtl8188e_start_thread;
1831 pHalFunc->cancel_thread = &rtl8188e_stop_thread;
1833 pHalFunc->AntDivBeforeLinkHandler = &AntDivBeforeLink8188E;
1834 pHalFunc->AntDivCompareHandler = &AntDivCompare8188E;
1835 pHalFunc->read_bbreg = &rtl8188e_PHY_QueryBBReg;
1836 pHalFunc->write_bbreg = &rtl8188e_PHY_SetBBReg;
1837 pHalFunc->read_rfreg = &rtl8188e_PHY_QueryRFReg;
1838 pHalFunc->write_rfreg = &rtl8188e_PHY_SetRFReg;
1840 /* Efuse related function */
1841 pHalFunc->EfusePowerSwitch = &rtl8188e_EfusePowerSwitch;
1842 pHalFunc->ReadEFuse = &rtl8188e_ReadEFuse;
1843 pHalFunc->EFUSEGetEfuseDefinition = &rtl8188e_EFUSE_GetEfuseDefinition;
1844 pHalFunc->EfuseGetCurrentSize = &rtl8188e_EfuseGetCurrentSize;
1845 pHalFunc->Efuse_PgPacketRead = &rtl8188e_Efuse_PgPacketRead;
1846 pHalFunc->Efuse_PgPacketWrite = &rtl8188e_Efuse_PgPacketWrite;
1847 pHalFunc->Efuse_WordEnableDataWrite = &rtl8188e_Efuse_WordEnableDataWrite;
1849 pHalFunc->sreset_init_value = &sreset_init_value;
1850 pHalFunc->sreset_reset_value = &sreset_reset_value;
1851 pHalFunc->silentreset = &rtl8188e_silentreset_for_specific_platform;
1852 pHalFunc->sreset_xmit_status_check = &rtl8188e_sreset_xmit_status_check;
1853 pHalFunc->sreset_linked_status_check = &rtl8188e_sreset_linked_status_check;
1854 pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status;
1856 pHalFunc->GetHalODMVarHandler = &rtl8188e_GetHalODMVar;
1857 pHalFunc->SetHalODMVarHandler = &rtl8188e_SetHalODMVar;
1859 pHalFunc->IOL_exec_cmds_sync = &rtl8188e_IOL_exec_cmds_sync;
1861 pHalFunc->hal_notch_filter = &hal_notch_filter_8188e;
1864 u8 GetEEPROMSize8188E(struct adapter *padapter)
1869 cr = rtw_read16(padapter, REG_9346CR);
1870 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1871 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1873 MSG_88E("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
1880 /* LLT R/W/Init function */
1883 static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data)
1885 s32 status = _SUCCESS;
1887 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
1888 u16 LLTReg = REG_LLT_INIT;
1890 rtw_write32(padapter, LLTReg, value);
1894 value = rtw_read32(padapter, LLTReg);
1895 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
1898 if (count > POLLING_LLT_THRESHOLD) {
1899 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling write LLT done at address %d!\n", address));
1908 s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
1912 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */
1914 if (rtw_IOL_applied(padapter)) {
1915 status = iol_InitLLTTable(padapter, txpktbuf_bndy);
1917 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
1918 status = _LLTWrite(padapter, i, i + 1);
1919 if (_SUCCESS != status)
1924 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
1925 if (_SUCCESS != status)
1928 /* Make the other pages as ring buffer */
1929 /* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */
1930 /* Otherwise used as local loopback buffer. */
1931 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
1932 status = _LLTWrite(padapter, i, (i + 1));
1933 if (_SUCCESS != status)
1937 /* Let last entry point to the start entry of ring buffer */
1938 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
1939 if (_SUCCESS != status) {
1948 Hal_InitPGData88E(struct adapter *padapter)
1950 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1952 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1953 if (!is_boot_from_eeprom(padapter)) {
1954 /* Read EFUSE real map to shadow. */
1955 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1957 } else {/* autoload fail */
1958 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
1959 /* update to default value 0xFF */
1960 if (!is_boot_from_eeprom(padapter))
1961 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1966 Hal_EfuseParseIDCode88E(
1967 struct adapter *padapter,
1971 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1974 /* Check 0x8129 again for making sure autoload status!! */
1975 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
1976 if (EEPROMId != RTL_EEPROM_ID) {
1977 pr_err("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
1978 pEEPROM->bautoload_fail_flag = true;
1980 pEEPROM->bautoload_fail_flag = false;
1983 pr_info("EEPROM ID = 0x%04x\n", EEPROMId);
1986 static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, u8 *PROMContent, bool AutoLoadFail)
1988 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_88E, group, TxCount = 0;
1990 memset(pwrInfo24G, 0, sizeof(struct txpowerinfo24g));
1993 for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
1994 /* 2.4G default value */
1995 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1996 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1997 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1999 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2001 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
2002 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2004 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2005 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2006 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2007 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2014 for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
2015 /* 2.4G default value */
2016 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
2017 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
2018 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
2019 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2021 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
2022 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
2023 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
2024 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2026 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2028 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
2029 if (PROMContent[eeAddr] == 0xFF) {
2030 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
2032 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2033 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2034 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2037 if (PROMContent[eeAddr] == 0xFF) {
2038 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2040 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2041 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2042 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2044 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
2047 if (PROMContent[eeAddr] == 0xFF) {
2048 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2050 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2051 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2052 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
2055 if (PROMContent[eeAddr] == 0xFF) {
2056 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2058 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2059 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2060 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2064 if (PROMContent[eeAddr] == 0xFF) {
2065 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2067 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2068 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2069 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2072 if (PROMContent[eeAddr] == 0xFF) {
2073 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2075 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2076 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2077 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
2085 static u8 Hal_GetChnlGroup88E(u8 chnl, u8 *pGroup)
2092 if (chnl < 3) /* Channel 1-2 */
2094 else if (chnl < 6) /* Channel 3-5 */
2096 else if (chnl < 9) /* Channel 6-8 */
2098 else if (chnl < 12) /* Channel 9-11 */
2100 else if (chnl < 14) /* Channel 12-13 */
2102 else if (chnl == 14) /* Channel 14 */
2109 else if (chnl <= 48)
2111 else if (chnl <= 56)
2113 else if (chnl <= 64)
2115 else if (chnl <= 104)
2117 else if (chnl <= 112)
2119 else if (chnl <= 120)
2121 else if (chnl <= 128)
2123 else if (chnl <= 136)
2125 else if (chnl <= 144)
2127 else if (chnl <= 153)
2129 else if (chnl <= 161)
2131 else if (chnl <= 177)
2137 void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2140 padapter->pwrctrlpriv.bHWPowerdown = false;
2141 padapter->pwrctrlpriv.bSupportRemoteWakeup = false;
2143 /* hw power down mode selection , 0:rf-off / 1:power down */
2145 if (padapter->registrypriv.hwpdn_mode == 2)
2146 padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4);
2148 padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode;
2150 /* decide hw if support remote wakeup function */
2151 /* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */
2152 padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1) ? true : false;
2154 DBG_88E("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) , bSupportRemoteWakeup(%x)\n", __func__,
2155 padapter->pwrctrlpriv.bHWPwrPindetect, padapter->pwrctrlpriv.bHWPowerdown, padapter->pwrctrlpriv.bSupportRemoteWakeup);
2157 DBG_88E("### PS params => power_mgnt(%x), usbss_enable(%x) ###\n", padapter->registrypriv.power_mgnt, padapter->registrypriv.usbss_enable);
2161 void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail)
2163 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
2164 struct txpowerinfo24g pwrInfo24G;
2165 u8 rfPath, ch, group;
2168 Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
2171 pHalData->bTXPowerDataReadFromEEPORM = true;
2173 for (rfPath = 0; rfPath < pHalData->NumTotalRFPath; rfPath++) {
2174 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
2175 bIn24G = Hal_GetChnlGroup88E(ch, &group);
2177 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
2179 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][4];
2181 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
2184 DBG_88E("======= Path %d, Channel %d =======\n", rfPath, ch);
2185 DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_CCK_Base[rfPath][ch]);
2186 DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch]);
2189 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2190 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
2191 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
2192 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
2193 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
2194 DBG_88E("======= TxCount %d =======\n", TxCount);
2195 DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]);
2196 DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]);
2197 DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]);
2198 DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]);
2202 /* 2010/10/19 MH Add Regulator recognize for CU. */
2203 if (!AutoLoadFail) {
2204 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); /* bit0~2 */
2205 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2206 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
2208 pHalData->EEPROMRegulatory = 0;
2210 DBG_88E("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
2213 void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
2215 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
2217 if (!AutoLoadFail) {
2218 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
2219 if (pHalData->CrystalCap == 0xFF)
2220 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
2222 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
2224 DBG_88E("CrystalCap: 0x%2x\n", pHalData->CrystalCap);
2227 void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
2229 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
2232 pHalData->BoardType = ((hwinfo[EEPROM_RF_BOARD_OPTION_88E]&0xE0)>>5);
2234 pHalData->BoardType = 0;
2235 DBG_88E("Board Type: 0x%2x\n", pHalData->BoardType);
2238 void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2240 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
2242 if (!AutoLoadFail) {
2243 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
2244 if (pHalData->EEPROMVersion == 0xFF)
2245 pHalData->EEPROMVersion = EEPROM_Default_Version;
2247 pHalData->EEPROMVersion = 1;
2249 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
2250 ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
2251 pHalData->EEPROMVersion));
2254 void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2256 padapter->mlmepriv.ChannelPlan =
2257 hal_com_get_channel_plan(padapter,
2258 hwinfo ? hwinfo[EEPROM_ChannelPlan_88E] : 0xFF,
2259 padapter->registrypriv.channel_plan,
2260 RT_CHANNEL_DOMAIN_WORLD_WIDE_13, AutoLoadFail);
2262 DBG_88E("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
2265 void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2267 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
2269 if (!AutoLoadFail) {
2270 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E];
2272 pHalData->EEPROMCustomerID = 0;
2273 pHalData->EEPROMSubCustomerID = 0;
2275 DBG_88E("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
2278 void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, bool AutoLoadFail)
2280 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
2281 struct registry_priv *registry_par = &pAdapter->registrypriv;
2283 if (!AutoLoadFail) {
2284 /* Antenna Diversity setting. */
2285 if (registry_par->antdiv_cfg == 2) { /* 2:By EFUSE */
2286 pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3;
2287 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2288 pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;;
2290 pHalData->AntDivCfg = registry_par->antdiv_cfg; /* 0:OFF , 1:ON, 2:By EFUSE */
2293 if (registry_par->antdiv_type == 0) {
2294 /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
2295 pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
2296 if (pHalData->TRxAntDivType == 0xFF)
2297 pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
2299 pHalData->TRxAntDivType = registry_par->antdiv_type;
2302 if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
2303 pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */
2305 pHalData->AntDivCfg = 0;
2306 pHalData->TRxAntDivType = pHalData->TRxAntDivType; /* The value in the driver setting of device manager. */
2308 DBG_88E("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n", pHalData->AntDivCfg, pHalData->TRxAntDivType);
2311 void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
2313 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
2315 /* ThermalMeter from EEPROM */
2317 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
2319 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
2321 if (pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) {
2322 pHalData->bAPKThermalMeterIgnore = true;
2323 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
2325 DBG_88E("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter);
2328 void Hal_InitChannelPlan(struct adapter *padapter)
2332 bool HalDetectPwrDownMode88E(struct adapter *Adapter)
2335 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
2336 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
2338 EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_FEATURE_OPTION_88E, (u32 *)&tmpvalue);
2340 /* 2010/08/25 MH INF priority > PDN Efuse value. */
2341 if (tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode)
2342 pHalData->pwrdown = true;
2344 pHalData->pwrdown = false;
2346 DBG_88E("HalDetectPwrDownMode(): PDN =%d\n", pHalData->pwrdown);
2348 return pHalData->pwrdown;
2349 } /* HalDetectPwrDownMode */
2351 /* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */
2352 /* We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate */
2353 /* the value of the register via atomic operation. */
2354 /* This prevents from race condition when setting this register. */
2355 /* The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function. */
2357 void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits)
2359 struct hal_data_8188e *pHalData;
2361 pHalData = GET_HAL_DATA(padapter);
2363 pHalData->RegBcnCtrlVal |= SetBits;
2364 pHalData->RegBcnCtrlVal &= ~ClearBits;
2366 rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);