drivers/staging/r8188eu/hal/odm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4 /*  include files */
   5
   6 #include "odm_precomp.h"
   7
   8 static const u16 dB_Invert_Table[8][12] = {
   9         {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
  10         {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
  11         {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
  12         {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
  13         {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
  14         {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  15         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
  16         {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
  17 };
  18
  19 /* avoid to warn in FreeBSD ==> To DO modify */
  20 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {
  21         /*  UL                  DL */
  22         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
  23         {0xa44f, 0x5ea44f, 0x5e431c}, /*  1:realtek AP */
  24         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  2:unknown AP => realtek_92SE */
  25         {0x5ea32b, 0x5ea42b, 0x5e4322}, /*  3:broadcom AP */
  26         {0x5ea422, 0x00a44f, 0x00a44f}, /*  4:ralink AP */
  27         {0x5ea322, 0x00a630, 0x00a44f}, /*  5:atheros AP */
  28         {0x5e4322, 0x5e4322, 0x5e4322},/*  6:cisco AP */
  29         {0x5ea44f, 0x00a44f, 0x5ea42b}, /*  8:marvell AP */
  30         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  10:unknown AP=> 92U AP */
  31         {0x5ea42b, 0xa630, 0x5e431c}, /*  11:airgocap AP */
  32 };
  33
  34 /*  Global var */
  35 u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
  36         0x7f8001fe, /*  0, +6.0dB */
  37         0x788001e2, /*  1, +5.5dB */
  38         0x71c001c7, /*  2, +5.0dB */
  39         0x6b8001ae, /*  3, +4.5dB */
  40         0x65400195, /*  4, +4.0dB */
  41         0x5fc0017f, /*  5, +3.5dB */
  42         0x5a400169, /*  6, +3.0dB */
  43         0x55400155, /*  7, +2.5dB */
  44         0x50800142, /*  8, +2.0dB */
  45         0x4c000130, /*  9, +1.5dB */
  46         0x47c0011f, /*  10, +1.0dB */
  47         0x43c0010f, /*  11, +0.5dB */
  48         0x40000100, /*  12, +0dB */
  49         0x3c8000f2, /*  13, -0.5dB */
  50         0x390000e4, /*  14, -1.0dB */
  51         0x35c000d7, /*  15, -1.5dB */
  52         0x32c000cb, /*  16, -2.0dB */
  53         0x300000c0, /*  17, -2.5dB */
  54         0x2d4000b5, /*  18, -3.0dB */
  55         0x2ac000ab, /*  19, -3.5dB */
  56         0x288000a2, /*  20, -4.0dB */
  57         0x26000098, /*  21, -4.5dB */
  58         0x24000090, /*  22, -5.0dB */
  59         0x22000088, /*  23, -5.5dB */
  60         0x20000080, /*  24, -6.0dB */
  61         0x1e400079, /*  25, -6.5dB */
  62         0x1c800072, /*  26, -7.0dB */
  63         0x1b00006c, /*  27. -7.5dB */
  64         0x19800066, /*  28, -8.0dB */
  65         0x18000060, /*  29, -8.5dB */
  66         0x16c0005b, /*  30, -9.0dB */
  67         0x15800056, /*  31, -9.5dB */
  68         0x14400051, /*  32, -10.0dB */
  69         0x1300004c, /*  33, -10.5dB */
  70         0x12000048, /*  34, -11.0dB */
  71         0x11000044, /*  35, -11.5dB */
  72         0x10000040, /*  36, -12.0dB */
  73         0x0f00003c,/*  37, -12.5dB */
  74         0x0e400039,/*  38, -13.0dB */
  75         0x0d800036,/*  39, -13.5dB */
  76         0x0cc00033,/*  40, -14.0dB */
  77         0x0c000030,/*  41, -14.5dB */
  78         0x0b40002d,/*  42, -15.0dB */
  79 };
  80
  81 u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
  82         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /*  0, +0dB */
  83         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  1, -0.5dB */
  84         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  2, -1.0dB */
  85         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  3, -1.5dB */
  86         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  4, -2.0dB */
  87         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  5, -2.5dB */
  88         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  6, -3.0dB */
  89         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  7, -3.5dB */
  90         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  8, -4.0dB */
  91         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  9, -4.5dB */
  92         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  10, -5.0dB */
  93         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  11, -5.5dB */
  94         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  12, -6.0dB */
  95         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  13, -6.5dB */
  96         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  14, -7.0dB */
  97         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  15, -7.5dB */
  98         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
  99         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  17, -8.5dB */
 100         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  18, -9.0dB */
 101         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  19, -9.5dB */
 102         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  20, -10.0dB */
 103         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  21, -10.5dB */
 104         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  22, -11.0dB */
 105         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*  23, -11.5dB */
 106         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*  24, -12.0dB */
 107         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*  25, -12.5dB */
 108         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*  26, -13.0dB */
 109         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  27, -13.5dB */
 110         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  28, -14.0dB */
 111         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  29, -14.5dB */
 112         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  30, -15.0dB */
 113         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*  31, -15.5dB */
 114         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /*  32, -16.0dB */
 115 };
 116
 117 u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
 118         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /*  0, +0dB */
 119         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /*  1, -0.5dB */
 120         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /*  2, -1.0dB */
 121         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*  3, -1.5dB */
 122         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /*  4, -2.0dB */
 123         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*  5, -2.5dB */
 124         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /*  6, -3.0dB */
 125         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /*  7, -3.5dB */
 126         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /*  8, -4.0dB */
 127         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*  9, -4.5dB */
 128         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /*  10, -5.0dB */
 129         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  11, -5.5dB */
 130         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  12, -6.0dB */
 131         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /*  13, -6.5dB */
 132         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /*  14, -7.0dB */
 133         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  15, -7.5dB */
 134         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  16, -8.0dB */
 135         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  17, -8.5dB */
 136         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  18, -9.0dB */
 137         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  19, -9.5dB */
 138         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  20, -10.0dB */
 139         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  21, -10.5dB */
 140         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  22, -11.0dB */
 141         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  23, -11.5dB */
 142         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  24, -12.0dB */
 143         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  25, -12.5dB */
 144         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  26, -13.0dB */
 145         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  27, -13.5dB */
 146         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  28, -14.0dB */
 147         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  29, -14.5dB */
 148         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  30, -15.0dB */
 149         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  31, -15.5dB */
 150         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}  /*  32, -16.0dB */
 151 };
 152
 153 #define         RxDefaultAnt1           0x65a9
 154 #define RxDefaultAnt2           0x569a
 155
 156 /* 3 Export Interface */
 157
 158 /*  2011/09/21 MH Add to describe different team necessary resource allocate?? */
 159 void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
 160 {
 161         /* 2012.05.03 Luke: For all IC series */
 162         odm_CommonInfoSelfInit(pDM_Odm);
 163         odm_CmnInfoInit_Debug(pDM_Odm);
 164         odm_DIGInit(pDM_Odm);
 165         odm_RateAdaptiveMaskInit(pDM_Odm);
 166
 167         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
 168                 ;
 169         } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
 170                 odm_PrimaryCCA_Init(pDM_Odm);    /*  Gary */
 171                 odm_DynamicBBPowerSavingInit(pDM_Odm);
 172                 odm_DynamicTxPowerInit(pDM_Odm);
 173                 odm_TXPowerTrackingInit(pDM_Odm);
 174                 ODM_EdcaTurboInit(pDM_Odm);
 175                 ODM_RAInfo_Init_all(pDM_Odm);
 176                 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)   ||
 177                     (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
 178                     (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
 179                         odm_InitHybridAntDiv(pDM_Odm);
 180                 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 181                         odm_SwAntDivInit(pDM_Odm);
 182         }
 183 }
 184
 185 /*  2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
 186 /*  You can not add any dummy function here, be care, you can only use DM structure */
 187 /*  to perform any new ODM_DM. */
 188 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
 189 {
 190         /* 2012.05.03 Luke: For all IC series */
 191         odm_GlobalAdapterCheck();
 192         odm_CmnInfoHook_Debug(pDM_Odm);
 193         odm_CmnInfoUpdate_Debug(pDM_Odm);
 194         odm_CommonInfoSelfUpdate(pDM_Odm);
 195         odm_FalseAlarmCounterStatistics(pDM_Odm);
 196         odm_RSSIMonitorCheck(pDM_Odm);
 197
 198         /* For CE Platform(SPRD or Tablet) */
 199         /* 8723A or 8189ES platform */
 200         /* NeilChen--2012--08--24-- */
 201         /* Fix Leave LPS issue */
 202         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/*  in LPS mode */
 203             ((pDM_Odm->SupportICType & (ODM_RTL8723A)) ||
 204             (pDM_Odm->SupportICType & (ODM_RTL8188E) &&
 205             ((pDM_Odm->SupportInterface  == ODM_ITRF_SDIO))))) {
 206                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n"));
 207                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 208                 odm_DIGbyRSSI_LPS(pDM_Odm);
 209         } else {
 210                 odm_DIG(pDM_Odm);
 211         }
 212         odm_CCKPacketDetectionThresh(pDM_Odm);
 213
 214         if (*(pDM_Odm->pbPowerSaving))
 215                 return;
 216
 217         odm_RefreshRateAdaptiveMask(pDM_Odm);
 218
 219         odm_DynamicBBPowerSaving(pDM_Odm);
 220         odm_DynamicPrimaryCCA(pDM_Odm);
 221         if ((pDM_Odm->AntDivType ==  CG_TRX_HW_ANTDIV)  ||
 222             (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)  ||
 223             (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
 224                 odm_HwAntDiv(pDM_Odm);
 225         else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 226                 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
 227
 228         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
 229                 ;
 230         } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
 231                 ODM_TXPowerTrackingCheck(pDM_Odm);
 232               odm_EdcaTurboCheck(pDM_Odm);
 233                 odm_DynamicTxPower(pDM_Odm);
 234         }
 235         odm_dtc(pDM_Odm);
 236 }
 237
 238 /*  Init /.. Fixed HW value. Only init time. */
 239 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value)
 240 {
 241         /*  This section is used for init value */
 242         switch  (CmnInfo) {
 243         /*  Fixed ODM value. */
 244         case    ODM_CMNINFO_ABILITY:
 245                 pDM_Odm->SupportAbility = (u32)Value;
 246                 break;
 247         case    ODM_CMNINFO_PLATFORM:
 248                 pDM_Odm->SupportPlatform = (u8)Value;
 249                 break;
 250         case    ODM_CMNINFO_INTERFACE:
 251                 pDM_Odm->SupportInterface = (u8)Value;
 252                 break;
 253         case    ODM_CMNINFO_MP_TEST_CHIP:
 254                 pDM_Odm->bIsMPChip = (u8)Value;
 255                 break;
 256         case    ODM_CMNINFO_IC_TYPE:
 257                 pDM_Odm->SupportICType = Value;
 258                 break;
 259         case    ODM_CMNINFO_CUT_VER:
 260                 pDM_Odm->CutVersion = (u8)Value;
 261                 break;
 262         case    ODM_CMNINFO_FAB_VER:
 263                 pDM_Odm->FabVersion = (u8)Value;
 264                 break;
 265         case    ODM_CMNINFO_RF_TYPE:
 266                 pDM_Odm->RFType = (u8)Value;
 267                 break;
 268         case    ODM_CMNINFO_RF_ANTENNA_TYPE:
 269                 pDM_Odm->AntDivType = (u8)Value;
 270                 break;
 271         case    ODM_CMNINFO_BOARD_TYPE:
 272                 pDM_Odm->BoardType = (u8)Value;
 273                 break;
 274         case    ODM_CMNINFO_EXT_LNA:
 275                 pDM_Odm->ExtLNA = (u8)Value;
 276                 break;
 277         case    ODM_CMNINFO_EXT_PA:
 278                 pDM_Odm->ExtPA = (u8)Value;
 279                 break;
 280         case    ODM_CMNINFO_EXT_TRSW:
 281                 pDM_Odm->ExtTRSW = (u8)Value;
 282                 break;
 283         case    ODM_CMNINFO_PATCH_ID:
 284                 pDM_Odm->PatchID = (u8)Value;
 285                 break;
 286         case    ODM_CMNINFO_BINHCT_TEST:
 287                 pDM_Odm->bInHctTest = (bool)Value;
 288                 break;
 289         case    ODM_CMNINFO_BWIFI_TEST:
 290                 pDM_Odm->bWIFITest = (bool)Value;
 291                 break;
 292         case    ODM_CMNINFO_SMART_CONCURRENT:
 293                 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
 294                 break;
 295         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 296         default:
 297                 /* do nothing */
 298                 break;
 299         }
 300
 301         /*  Tx power tracking BB swing table. */
 302         /*  The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
 303         pDM_Odm->BbSwingIdxOfdm                 = 12; /*  Set defalut value as index 12. */
 304         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 305         pDM_Odm->BbSwingFlagOfdm                = false;
 306 }
 307
 308 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue)
 309 {
 310         /*  */
 311         /*  Hook call by reference pointer. */
 312         /*  */
 313         switch  (CmnInfo) {
 314         /*  Dynamic call by reference pointer. */
 315         case    ODM_CMNINFO_MAC_PHY_MODE:
 316                 pDM_Odm->pMacPhyMode = (u8 *)pValue;
 317                 break;
 318         case    ODM_CMNINFO_TX_UNI:
 319                 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue;
 320                 break;
 321         case    ODM_CMNINFO_RX_UNI:
 322                 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue;
 323                 break;
 324         case    ODM_CMNINFO_WM_MODE:
 325                 pDM_Odm->pWirelessMode = (u8 *)pValue;
 326                 break;
 327         case    ODM_CMNINFO_BAND:
 328                 pDM_Odm->pBandType = (u8 *)pValue;
 329                 break;
 330         case    ODM_CMNINFO_SEC_CHNL_OFFSET:
 331                 pDM_Odm->pSecChOffset = (u8 *)pValue;
 332                 break;
 333         case    ODM_CMNINFO_SEC_MODE:
 334                 pDM_Odm->pSecurity = (u8 *)pValue;
 335                 break;
 336         case    ODM_CMNINFO_BW:
 337                 pDM_Odm->pBandWidth = (u8 *)pValue;
 338                 break;
 339         case    ODM_CMNINFO_CHNL:
 340                 pDM_Odm->pChannel = (u8 *)pValue;
 341                 break;
 342         case    ODM_CMNINFO_DMSP_GET_VALUE:
 343                 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue;
 344                 break;
 345         case    ODM_CMNINFO_BUDDY_ADAPTOR:
 346                 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue;
 347                 break;
 348         case    ODM_CMNINFO_DMSP_IS_MASTER:
 349                 pDM_Odm->pbMasterOfDMSP = (bool *)pValue;
 350                 break;
 351         case    ODM_CMNINFO_SCAN:
 352                 pDM_Odm->pbScanInProcess = (bool *)pValue;
 353                 break;
 354         case    ODM_CMNINFO_POWER_SAVING:
 355                 pDM_Odm->pbPowerSaving = (bool *)pValue;
 356                 break;
 357         case    ODM_CMNINFO_ONE_PATH_CCA:
 358                 pDM_Odm->pOnePathCCA = (u8 *)pValue;
 359                 break;
 360         case    ODM_CMNINFO_DRV_STOP:
 361                 pDM_Odm->pbDriverStopped =  (bool *)pValue;
 362                 break;
 363         case    ODM_CMNINFO_PNP_IN:
 364                 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep =  (bool *)pValue;
 365                 break;
 366         case    ODM_CMNINFO_INIT_ON:
 367                 pDM_Odm->pinit_adpt_in_progress =  (bool *)pValue;
 368                 break;
 369         case    ODM_CMNINFO_ANT_TEST:
 370                 pDM_Odm->pAntennaTest =  (u8 *)pValue;
 371                 break;
 372         case    ODM_CMNINFO_NET_CLOSED:
 373                 pDM_Odm->pbNet_closed = (bool *)pValue;
 374                 break;
 375         case    ODM_CMNINFO_MP_MODE:
 376                 pDM_Odm->mp_mode = (u8 *)pValue;
 377                 break;
 378         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 379         default:
 380                 /* do nothing */
 381                 break;
 382         }
 383 }
 384
 385 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue)
 386 {
 387         /*  Hook call by reference pointer. */
 388         switch  (CmnInfo) {
 389         /*  Dynamic call by reference pointer. */
 390         case    ODM_CMNINFO_STA_STATUS:
 391                 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
 392                 break;
 393         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 394         default:
 395                 /* do nothing */
 396                 break;
 397         }
 398 }
 399
 400 /*  Update Band/CHannel/.. The values are dynamic but non-per-packet. */
 401 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value)
 402 {
 403         /*  */
 404         /*  This init variable may be changed in run time. */
 405         /*  */
 406         switch  (CmnInfo) {
 407         case    ODM_CMNINFO_ABILITY:
 408                 pDM_Odm->SupportAbility = (u32)Value;
 409                 break;
 410         case    ODM_CMNINFO_RF_TYPE:
 411                 pDM_Odm->RFType = (u8)Value;
 412                 break;
 413         case    ODM_CMNINFO_WIFI_DIRECT:
 414                 pDM_Odm->bWIFI_Direct = (bool)Value;
 415                 break;
 416         case    ODM_CMNINFO_WIFI_DISPLAY:
 417                 pDM_Odm->bWIFI_Display = (bool)Value;
 418                 break;
 419         case    ODM_CMNINFO_LINK:
 420                 pDM_Odm->bLinked = (bool)Value;
 421                 break;
 422         case    ODM_CMNINFO_RSSI_MIN:
 423                 pDM_Odm->RSSI_Min = (u8)Value;
 424                 break;
 425         case    ODM_CMNINFO_DBG_COMP:
 426                 pDM_Odm->DebugComponents = Value;
 427                 break;
 428         case    ODM_CMNINFO_DBG_LEVEL:
 429                 pDM_Odm->DebugLevel = (u32)Value;
 430                 break;
 431         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 432                 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 433                 break;
 434         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 435                 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 436                 break;
 437         }
 438 }
 439
 440 void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
 441 {
 442         pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
 443         pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
 444         if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
 445                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
 446         if (pDM_Odm->SupportICType & (ODM_RTL8723A))
 447                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
 448
 449         ODM_InitDebugSetting(pDM_Odm);
 450 }
 451
 452 void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
 453 {
 454         u8 EntryCnt = 0;
 455         u8 i;
 456         struct sta_info *pEntry;
 457
 458         if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
 459                 if (*(pDM_Odm->pSecChOffset) == 1)
 460                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
 461                 else if (*(pDM_Odm->pSecChOffset) == 2)
 462                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
 463         } else {
 464                 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
 465         }
 466
 467         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 468                 pEntry = pDM_Odm->pODM_StaInfo[i];
 469                 if (IS_STA_VALID(pEntry))
 470                         EntryCnt++;
 471         }
 472         if (EntryCnt == 1)
 473                 pDM_Odm->bOneEntryOnly = true;
 474         else
 475                 pDM_Odm->bOneEntryOnly = false;
 476 }
 477
 478 void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm)
 479 {
 480         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n"));
 481         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform));
 482         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility));
 483         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface));
 484         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType));
 485         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion));
 486         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion));
 487         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType));
 488         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType));
 489         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA));
 490         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA));
 491         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW));
 492         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID));
 493         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest));
 494         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest));
 495         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent));
 496 }
 497
 498 void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm)
 499 {
 500         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n"));
 501         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast)));
 502         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast)));
 503         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode)));
 504         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset)));
 505         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity)));
 506         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth)));
 507         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel)));
 508
 509         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess)));
 510         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving)));
 511
 512         if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
 513                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n", *(pDM_Odm->pOnePathCCA)));
 514 }
 515
 516 void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm)
 517 {
 518         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n"));
 519         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct));
 520         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display));
 521         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked));
 522         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min));
 523 }
 524
 525 static int getIGIForDiff(int value_IGI)
 526 {
 527         #define ONERCCA_LOW_TH          0x30
 528         #define ONERCCA_LOW_DIFF        8
 529
 530         if (value_IGI < ONERCCA_LOW_TH) {
 531                 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
 532                         return ONERCCA_LOW_TH;
 533                 else
 534                         return value_IGI + ONERCCA_LOW_DIFF;
 535         } else {
 536                 return value_IGI;
 537         }
 538 }
 539
 540 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
 541 {
 542         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
 543
 544         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 545                      ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n",
 546                      ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
 547
 548         if (pDM_DigTable->CurIGValue != CurrentIGI) {
 549                 if (pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) {
 550                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 551                                 if (pDM_Odm->SupportICType != ODM_RTL8188E)
 552                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 553                 } else if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
 554                         switch (*(pDM_Odm->pOnePathCCA)) {
 555                         case ODM_CCA_2R:
 556                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 557                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
 558                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 559                                 break;
 560                         case ODM_CCA_1R_A:
 561                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 562                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
 563                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI));
 564                                 break;
 565                         case ODM_CCA_1R_B:
 566                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI));
 567                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
 568                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 569                                         break;
 570                                 }
 571                 }
 572                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI));
 573                 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */
 574                 pDM_DigTable->CurIGValue = CurrentIGI;
 575         }
 576         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI));
 577
 578 /*  Add by Neil Chen to enable edcca to MP Platform */
 579 }
 580
 581 /* Need LPS mode for CE platform --2012--08--24--- */
 582 /* 8723AS/8189ES */
 583 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm)
 584 {
 585         struct adapter *pAdapter = pDM_Odm->Adapter;
 586         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 587
 588         u8 RSSI_Lower = DM_DIG_MIN_NIC;   /* 0x1E or 0x1C */
 589         u8 bFwCurrentInPSMode = false;
 590         u8 CurrentIGI = pDM_Odm->RSSI_Min;
 591
 592         if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8188E)))
 593                 return;
 594
 595         CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG;
 596         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
 597
 598         /*  Using FW PS mode to make IGI */
 599         if (bFwCurrentInPSMode) {
 600                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n"));
 601                 /* Adjust by  FA in LPS MODE */
 602                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
 603                         CurrentIGI = CurrentIGI+2;
 604                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
 605                         CurrentIGI = CurrentIGI+1;
 606                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
 607                         CurrentIGI = CurrentIGI-1;
 608         } else {
 609                 CurrentIGI = RSSI_Lower;
 610         }
 611
 612         /* Lower bound checking */
 613
 614         /* RSSI Lower bound check */
 615         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
 616                 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
 617         else
 618                 RSSI_Lower = DM_DIG_MIN_NIC;
 619
 620         /* Upper and Lower Bound checking */
 621          if (CurrentIGI > DM_DIG_MAX_NIC)
 622                 CurrentIGI = DM_DIG_MAX_NIC;
 623          else if (CurrentIGI < RSSI_Lower)
 624                 CurrentIGI = RSSI_Lower;
 625
 626         ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
 627 }
 628
 629 void odm_DIGInit(struct odm_dm_struct *pDM_Odm)
 630 {
 631         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
 632
 633         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
 634         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 635         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 636         pDM_DigTable->FALowThresh       = DM_false_ALARM_THRESH_LOW;
 637         pDM_DigTable->FAHighThresh      = DM_false_ALARM_THRESH_HIGH;
 638         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
 639                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 640                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 641         } else {
 642                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 643                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 644         }
 645         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 646         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 647         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 648         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 649         pDM_DigTable->CurCCK_CCAThres = 0x83;
 650         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 651         pDM_DigTable->LargeFAHit = 0;
 652         pDM_DigTable->Recover_cnt = 0;
 653         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 654         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 655         pDM_DigTable->bMediaConnect_0 = false;
 656         pDM_DigTable->bMediaConnect_1 = false;
 657
 658         /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
 659         pDM_Odm->bDMInitialGainEnable = true;
 660 }
 661
 662 void odm_DIG(struct odm_dm_struct *pDM_Odm)
 663 {
 664         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
 665         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 666         u8 DIG_Dynamic_MIN;
 667         u8 DIG_MaxOfMin;
 668         bool FirstConnect, FirstDisConnect;
 669         u8 dm_dig_max, dm_dig_min;
 670         u8 CurrentIGI = pDM_DigTable->CurIGValue;
 671
 672         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
 673         if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
 674                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 675                              ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
 676                 return;
 677         }
 678
 679         if (*(pDM_Odm->pbScanInProcess)) {
 680                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n"));
 681                 return;
 682         }
 683
 684         /* add by Neil Chen to avoid PSD is processing */
 685         if (pDM_Odm->bDMInitialGainEnable == false) {
 686                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n"));
 687                 return;
 688         }
 689
 690         if (pDM_Odm->SupportICType == ODM_RTL8192D) {
 691                 if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP) {
 692                         if (*(pDM_Odm->pbMasterOfDMSP)) {
 693                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 694                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 695                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 696                         } else {
 697                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
 698                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
 699                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
 700                         }
 701                 } else {
 702                         if (*(pDM_Odm->pBandType) == ODM_BAND_5G) {
 703                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 704                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 705                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 706                         } else {
 707                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
 708                                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
 709                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
 710                         }
 711                 }
 712         } else {
 713                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 714                 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 715                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 716         }
 717
 718         /* 1 Boundary Decision */
 719         if ((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) &&
 720             ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
 721                 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
 722                         dm_dig_max = DM_DIG_MAX_AP_HP;
 723                         dm_dig_min = DM_DIG_MIN_AP_HP;
 724                 } else {
 725                         dm_dig_max = DM_DIG_MAX_NIC_HP;
 726                         dm_dig_min = DM_DIG_MIN_NIC_HP;
 727                 }
 728                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
 729         } else {
 730                 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
 731                         dm_dig_max = DM_DIG_MAX_AP;
 732                         dm_dig_min = DM_DIG_MIN_AP;
 733                         DIG_MaxOfMin = dm_dig_max;
 734                 } else {
 735                         dm_dig_max = DM_DIG_MAX_NIC;
 736                         dm_dig_min = DM_DIG_MIN_NIC;
 737                         DIG_MaxOfMin = DM_DIG_MAX_AP;
 738                 }
 739         }
 740         if (pDM_Odm->bLinked) {
 741               /* 2 8723A Series, offset need to be 10 */
 742                 if (pDM_Odm->SupportICType == (ODM_RTL8723A)) {
 743                         /* 2 Upper Bound */
 744                         if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
 745                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 746                         else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
 747                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
 748                         else
 749                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
 750                         /* 2 If BT is Concurrent, need to set Lower Bound */
 751                         DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
 752                 } else {
 753                         /* 2 Modify DIG upper bound */
 754                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
 755                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 756                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
 757                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
 758                         else
 759                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
 760                         /* 2 Modify DIG lower bound */
 761                         if (pDM_Odm->bOneEntryOnly) {
 762                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
 763                                         DIG_Dynamic_MIN = dm_dig_min;
 764                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
 765                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
 766                                 else
 767                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
 768                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 769                                              ("odm_DIG() : bOneEntryOnly=true,  DIG_Dynamic_MIN=0x%x\n",
 770                                              DIG_Dynamic_MIN));
 771                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 772                                              ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",
 773                                              pDM_Odm->RSSI_Min));
 774                         } else if ((pDM_Odm->SupportICType == ODM_RTL8188E) &&
 775                                    (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
 776                                 /* 1 Lower Bound for 88E AntDiv */
 777                                 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
 778                                         DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max;
 779                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
 780                                                      ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n",
 781                                                      pDM_DigTable->AntDiv_RSSI_max));
 782                                 }
 783                         } else {
 784                                 DIG_Dynamic_MIN = dm_dig_min;
 785                         }
 786                 }
 787         } else {
 788                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 789                 DIG_Dynamic_MIN = dm_dig_min;
 790                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n"));
 791         }
 792
 793         /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
 794         if (pFalseAlmCnt->Cnt_all > 10000) {
 795                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n"));
 796
 797                 if (pDM_DigTable->LargeFAHit != 3)
 798                         pDM_DigTable->LargeFAHit++;
 799                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
 800                         pDM_DigTable->ForbiddenIGI = CurrentIGI;
 801                         pDM_DigTable->LargeFAHit = 1;
 802                 }
 803
 804                 if (pDM_DigTable->LargeFAHit >= 3) {
 805                         if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
 806                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
 807                         else
 808                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 809                         pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */
 810                 }
 811
 812         } else {
 813                 /* Recovery mechanism for IGI lower bound */
 814                 if (pDM_DigTable->Recover_cnt != 0) {
 815                         pDM_DigTable->Recover_cnt--;
 816                 } else {
 817                         if (pDM_DigTable->LargeFAHit < 3) {
 818                                 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */
 819                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 820                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 821                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
 822                                 } else {
 823                                         pDM_DigTable->ForbiddenIGI--;
 824                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 825                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
 826                                 }
 827                         } else {
 828                                 pDM_DigTable->LargeFAHit = 0;
 829                         }
 830                 }
 831         }
 832         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 833                      ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",
 834                      pDM_DigTable->LargeFAHit));
 835
 836         /* 1 Adjust initial gain by false alarm */
 837         if (pDM_Odm->bLinked) {
 838                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n"));
 839                 if (FirstConnect) {
 840                         CurrentIGI = pDM_Odm->RSSI_Min;
 841                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
 842                 } else {
 843                         if (pDM_Odm->SupportICType == ODM_RTL8192D) {
 844                                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
 845                                         CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 846                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
 847                                         CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 848                                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
 849                                         CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
 850                         } else {
 851                                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
 852                                                 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 853                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
 854                                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 855                                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
 856                                                 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
 857                         }
 858                 }
 859         } else {
 860                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
 861                 if (FirstDisConnect) {
 862                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
 863                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n"));
 864                 } else {
 865                         /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
 866                         if (pFalseAlmCnt->Cnt_all > 10000)
 867                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 868                         else if (pFalseAlmCnt->Cnt_all > 8000)
 869                                 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 870                         else if (pFalseAlmCnt->Cnt_all < 500)
 871                                 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
 872                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n"));
 873                 }
 874         }
 875         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
 876         /* 1 Check initial gain by upper/lower bound */
 877         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
 878                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 879         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
 880                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
 881
 882         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 883                      ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
 884                      pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
 885         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
 886         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
 887
 888         /* 2 High power RSSI threshold */
 889
 890         ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
 891         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
 892         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
 893 }
 894
 895 /* 3============================================================ */
 896 /* 3 FASLE ALARM CHECK */
 897 /* 3============================================================ */
 898
 899 void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
 900 {
 901         u32 ret_value;
 902         struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
 903
 904         if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
 905                 return;
 906
 907         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
 908                 /* hold ofdm counter */
 909                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */
 910                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */
 911
 912                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
 913                 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
 914                 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
 915                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
 916                 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
 917                 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
 918                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
 919                 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
 920                 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
 921                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
 922                 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
 923
 924                 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
 925                                              FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
 926                                              FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
 927
 928                 if (pDM_Odm->SupportICType == ODM_RTL8188E) {
 929                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
 930                         FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
 931                         FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
 932                 }
 933
 934                 /* hold cck counter */
 935                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
 936                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
 937
 938                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
 939                 FalseAlmCnt->Cnt_Cck_fail = ret_value;
 940                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
 941                 FalseAlmCnt->Cnt_Cck_fail +=  (ret_value & 0xff)<<8;
 942
 943                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
 944                 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
 945
 946                 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
 947                                         FalseAlmCnt->Cnt_SB_Search_fail +
 948                                         FalseAlmCnt->Cnt_Parity_Fail +
 949                                         FalseAlmCnt->Cnt_Rate_Illegal +
 950                                         FalseAlmCnt->Cnt_Crc8_fail +
 951                                         FalseAlmCnt->Cnt_Mcs_fail +
 952                                         FalseAlmCnt->Cnt_Cck_fail);
 953
 954                 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
 955
 956                 if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
 957                         /* reset false alarm counter registers */
 958                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
 959                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
 960                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
 961                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
 962                         /* update ofdm counter */
 963                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */
 964                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */
 965
 966                         /* reset CCK CCA counter */
 967                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
 968                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
 969                         /* reset CCK FA counter */
 970                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
 971                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
 972                 }
 973
 974                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
 975                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 976                              ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
 977                              FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
 978                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 979                              ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
 980                              FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
 981                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 982                              ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
 983                              FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
 984         } else { /* FOR ODM_IC_11AC_SERIES */
 985                 /* read OFDM FA counter */
 986                 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
 987                 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
 988                 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
 989
 990                 /*  reset OFDM FA coutner */
 991                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
 992                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
 993                 /*  reset CCK FA counter */
 994                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
 995                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
 996         }
 997         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail));
 998         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
 999         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all));
1000 }
1001
1002 /* 3============================================================ */
1003 /* 3 CCK Packet Detect Threshold */
1004 /* 3============================================================ */
1005
1006 void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
1007 {
1008         u8 CurCCK_CCAThres;
1009         struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
1010
1011         if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
1012                 return;
1013         if (pDM_Odm->ExtLNA)
1014                 return;
1015         if (pDM_Odm->bLinked) {
1016                 if (pDM_Odm->RSSI_Min > 25) {
1017                         CurCCK_CCAThres = 0xcd;
1018                 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
1019                         CurCCK_CCAThres = 0x83;
1020                 } else {
1021                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
1022                                 CurCCK_CCAThres = 0x83;
1023                         else
1024                                 CurCCK_CCAThres = 0x40;
1025                 }
1026         } else {
1027                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
1028                         CurCCK_CCAThres = 0x83;
1029                 else
1030                         CurCCK_CCAThres = 0x40;
1031         }
1032         ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
1033 }
1034
1035 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
1036 {
1037         struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
1038
1039         if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)           /* modify by Guo.Mingzhi 2012-01-03 */
1040                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
1041         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
1042         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
1043 }
1044
1045 /* 3============================================================ */
1046 /* 3 BB Power Save */
1047 /* 3============================================================ */
1048 void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm)
1049 {
1050         struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
1051
1052         pDM_PSTable->PreCCAState = CCA_MAX;
1053         pDM_PSTable->CurCCAState = CCA_MAX;
1054         pDM_PSTable->PreRFState = RF_MAX;
1055         pDM_PSTable->CurRFState = RF_MAX;
1056         pDM_PSTable->Rssi_val_min = 0;
1057         pDM_PSTable->initialize = 0;
1058 }
1059
1060 void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm)
1061 {
1062         if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A))
1063                 return;
1064         if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
1065                 return;
1066         if (!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE)))
1067                 return;
1068
1069         /* 1 2.Power Saving for 92C */
1070         if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->RFType == ODM_2T2R)) {
1071                 odm_1R_CCA(pDM_Odm);
1072         } else {
1073         /*  20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */
1074         /*  20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */
1075         /* 1 3.Power Saving for 88C */
1076                 ODM_RF_Saving(pDM_Odm, false);
1077         }
1078 }
1079
1080 void odm_1R_CCA(struct odm_dm_struct *pDM_Odm)
1081 {
1082         struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
1083
1084         if (pDM_Odm->RSSI_Min != 0xFF) {
1085                 if (pDM_PSTable->PreCCAState == CCA_2R) {
1086                         if (pDM_Odm->RSSI_Min >= 35)
1087                                 pDM_PSTable->CurCCAState = CCA_1R;
1088                         else
1089                                 pDM_PSTable->CurCCAState = CCA_2R;
1090                 } else {
1091                         if (pDM_Odm->RSSI_Min <= 30)
1092                                 pDM_PSTable->CurCCAState = CCA_2R;
1093                         else
1094                                 pDM_PSTable->CurCCAState = CCA_1R;
1095                 }
1096         } else {
1097                 pDM_PSTable->CurCCAState = CCA_MAX;
1098         }
1099
1100         if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) {
1101                 if (pDM_PSTable->CurCCAState == CCA_1R) {
1102                         if (pDM_Odm->RFType == ODM_2T2R)
1103                                 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
1104                         else
1105                                 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
1106                 } else {
1107                         ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
1108                 }
1109                 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
1110         }
1111 }
1112
1113 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
1114 {
1115         struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
1116         u8 Rssi_Up_bound = 30;
1117         u8 Rssi_Low_bound = 25;
1118
1119         if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
1120                 Rssi_Up_bound = 50;
1121                 Rssi_Low_bound = 45;
1122         }
1123         if (pDM_PSTable->initialize == 0) {
1124                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
1125                 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
1126                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
1127                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
1128                 pDM_PSTable->initialize = 1;
1129         }
1130
1131         if (!bForceInNormal) {
1132                 if (pDM_Odm->RSSI_Min != 0xFF) {
1133                         if (pDM_PSTable->PreRFState == RF_Normal) {
1134                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1135                                         pDM_PSTable->CurRFState = RF_Save;
1136                                 else
1137                                         pDM_PSTable->CurRFState = RF_Normal;
1138                         } else {
1139                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1140                                         pDM_PSTable->CurRFState = RF_Normal;
1141                                 else
1142                                         pDM_PSTable->CurRFState = RF_Save;
1143                         }
1144                 } else {
1145                         pDM_PSTable->CurRFState = RF_MAX;
1146                 }
1147         } else {
1148                 pDM_PSTable->CurRFState = RF_Normal;
1149         }
1150
1151         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
1152                 if (pDM_PSTable->CurRFState == RF_Save) {
1153                         /*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */
1154                         /*  Suggested by SD3 Yu-Nan. 2011.01.20. */
1155                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
1156                                 ODM_SetBBReg(pDM_Odm, 0x874  , BIT5, 0x1); /* Reg874[5]=1b'1 */
1157                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
1158                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */
1159                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
1160                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
1161                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
1162                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */
1163                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */
1164                 } else {
1165                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1CC000, pDM_PSTable->Reg874);
1166                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
1167                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
1168                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
1169                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
1170
1171                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
1172                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x0); /* Reg874[5]=1b'0 */
1173                 }
1174                 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
1175         }
1176 }
1177
1178 /* 3============================================================ */
1179 /* 3 RATR MASK */
1180 /* 3============================================================ */
1181 /* 3============================================================ */
1182 /* 3 Rate Adaptive */
1183 /* 3============================================================ */
1184
1185 void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm)
1186 {
1187         struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1188
1189         pOdmRA->Type = DM_Type_ByDriver;
1190         if (pOdmRA->Type == DM_Type_ByDriver)
1191                 pDM_Odm->bUseRAMask = true;
1192         else
1193                 pDM_Odm->bUseRAMask = false;
1194
1195         pOdmRA->RATRState = DM_RATR_STA_INIT;
1196         pOdmRA->HighRSSIThresh = 50;
1197         pOdmRA->LowRSSIThresh = 20;
1198 }
1199
1200 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level)
1201 {
1202         struct sta_info *pEntry;
1203         u32 rate_bitmap = 0x0fffffff;
1204         u8 WirelessMode;
1205
1206         pEntry = pDM_Odm->pODM_StaInfo[macid];
1207         if (!IS_STA_VALID(pEntry))
1208                 return ra_mask;
1209
1210         WirelessMode = pEntry->wireless_mode;
1211
1212         switch (WirelessMode) {
1213         case ODM_WM_B:
1214                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
1215                         rate_bitmap = 0x0000000d;
1216                 else
1217                         rate_bitmap = 0x0000000f;
1218                 break;
1219         case (ODM_WM_A|ODM_WM_G):
1220                 if (rssi_level == DM_RATR_STA_HIGH)
1221                         rate_bitmap = 0x00000f00;
1222                 else
1223                         rate_bitmap = 0x00000ff0;
1224                 break;
1225         case (ODM_WM_B|ODM_WM_G):
1226                 if (rssi_level == DM_RATR_STA_HIGH)
1227                         rate_bitmap = 0x00000f00;
1228                 else if (rssi_level == DM_RATR_STA_MIDDLE)
1229                         rate_bitmap = 0x00000ff0;
1230                 else
1231                         rate_bitmap = 0x00000ff5;
1232                 break;
1233         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1234         case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1235                 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1236                         if (rssi_level == DM_RATR_STA_HIGH) {
1237                                 rate_bitmap = 0x000f0000;
1238                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1239                                 rate_bitmap = 0x000ff000;
1240                         } else {
1241                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1242                                         rate_bitmap = 0x000ff015;
1243                                 else
1244                                         rate_bitmap = 0x000ff005;
1245                         }
1246                 } else {
1247                         if (rssi_level == DM_RATR_STA_HIGH) {
1248                                 rate_bitmap = 0x0f8f0000;
1249                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1250                                 rate_bitmap = 0x0f8ff000;
1251                         } else {
1252                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1253                                         rate_bitmap = 0x0f8ff015;
1254                                 else
1255                                         rate_bitmap = 0x0f8ff005;
1256                         }
1257                 }
1258                 break;
1259         default:
1260                 /* case WIRELESS_11_24N: */
1261                 /* case WIRELESS_11_5N: */
1262                 if (pDM_Odm->RFType == RF_1T2R)
1263                         rate_bitmap = 0x000fffff;
1264                 else
1265                         rate_bitmap = 0x0fffffff;
1266                 break;
1267         }
1268
1269         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1270                      (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n",
1271                      rssi_level, WirelessMode, rate_bitmap));
1272
1273         return rate_bitmap;
1274 }
1275
1276 /*-----------------------------------------------------------------------------
1277  * Function:    odm_RefreshRateAdaptiveMask()
1278  *
1279  * Overview:    Update rate table mask according to rssi
1280  *
1281  * Input:               NONE
1282  *
1283  * Output:              NONE
1284  *
1285  * Return:              NONE
1286  *
1287  * Revised History:
1288  *      When            Who             Remark
1289  *      05/27/2009      hpfan   Create Version 0.
1290  *
1291  *---------------------------------------------------------------------------*/
1292 void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm)
1293 {
1294         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1295                 return;
1296         /*  */
1297         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1298         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1299         /*  HW dynamic mechanism. */
1300         /*  */
1301         switch  (pDM_Odm->SupportPlatform) {
1302         case    ODM_MP:
1303                 odm_RefreshRateAdaptiveMaskMP(pDM_Odm);
1304                 break;
1305         case    ODM_CE:
1306                 odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
1307                 break;
1308         case    ODM_AP:
1309         case    ODM_ADSL:
1310                 odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm);
1311                 break;
1312         }
1313 }
1314
1315 void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm)
1316 {
1317 }
1318
1319 void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm)
1320 {
1321         u8 i;
1322         struct adapter *pAdapter = pDM_Odm->Adapter;
1323
1324         if (pAdapter->bDriverStopped) {
1325                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
1326                 return;
1327         }
1328
1329         if (!pDM_Odm->bUseRAMask) {
1330                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
1331                 return;
1332         }
1333
1334         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1335                 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1336                 if (IS_STA_VALID(pstat)) {
1337                         if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) {
1338                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1339                                              ("RSSI:%d, RSSI_LEVEL:%d\n",
1340                                              pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
1341                                 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level);
1342                         }
1343                 }
1344         }
1345 }
1346
1347 void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm)
1348 {
1349 }
1350
1351 /*  Return Value: bool */
1352 /*  - true: RATRState is changed. */
1353 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState)
1354 {
1355         struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1356         const u8 GoUpGap = 5;
1357         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1358         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1359         u8 RATRState;
1360
1361         /*  Threshold Adjustment: */
1362         /*  when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1363         /*  Here GoUpGap is added to solve the boundary's level alternation issue. */
1364         switch (*pRATRState) {
1365         case DM_RATR_STA_INIT:
1366         case DM_RATR_STA_HIGH:
1367                 break;
1368         case DM_RATR_STA_MIDDLE:
1369                 HighRSSIThreshForRA += GoUpGap;
1370                 break;
1371         case DM_RATR_STA_LOW:
1372                 HighRSSIThreshForRA += GoUpGap;
1373                 LowRSSIThreshForRA += GoUpGap;
1374                 break;
1375         default:
1376                 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1377                 break;
1378         }
1379
1380         /*  Decide RATRState by RSSI. */
1381         if (RSSI > HighRSSIThreshForRA)
1382                 RATRState = DM_RATR_STA_HIGH;
1383         else if (RSSI > LowRSSIThreshForRA)
1384                 RATRState = DM_RATR_STA_MIDDLE;
1385         else
1386                 RATRState = DM_RATR_STA_LOW;
1387
1388         if (*pRATRState != RATRState || bForceUpdate) {
1389                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1390                 *pRATRState = RATRState;
1391                 return true;
1392         }
1393         return false;
1394 }
1395
1396 /* 3============================================================ */
1397 /* 3 Dynamic Tx Power */
1398 /* 3============================================================ */
1399
1400 void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
1401 {
1402         struct adapter *Adapter = pDM_Odm->Adapter;
1403         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
1404         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1405         pdmpriv->bDynamicTxPowerEnable = false;
1406         pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
1407         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1408 }
1409
1410 void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm)
1411 {
1412         /*  For AP/ADSL use struct rtl8192cd_priv * */
1413         /*  For CE/NIC use struct adapter * */
1414
1415         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
1416                 return;
1417
1418         /*  2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */
1419         if (!pDM_Odm->ExtPA)
1420                 return;
1421
1422         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1423         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1424         /*  HW dynamic mechanism. */
1425         switch  (pDM_Odm->SupportPlatform) {
1426         case    ODM_MP:
1427         case    ODM_CE:
1428                 odm_DynamicTxPowerNIC(pDM_Odm);
1429                 break;
1430         case    ODM_AP:
1431                 odm_DynamicTxPowerAP(pDM_Odm);
1432                 break;
1433         case    ODM_ADSL:
1434                 break;
1435         }
1436 }
1437
1438 void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm)
1439 {
1440         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
1441                 return;
1442
1443         if (pDM_Odm->SupportICType == ODM_RTL8188E) {
1444                 /*  ??? */
1445                 /*  This part need to be redefined. */
1446         }
1447 }
1448
1449 void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm)
1450 {
1451 }
1452
1453 /* 3============================================================ */
1454 /* 3 RSSI Monitor */
1455 /* 3============================================================ */
1456
1457 void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
1458 {
1459         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1460                 return;
1461
1462         /*  */
1463         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1464         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1465         /*  HW dynamic mechanism. */
1466         /*  */
1467         switch  (pDM_Odm->SupportPlatform) {
1468         case    ODM_MP:
1469                 odm_RSSIMonitorCheckMP(pDM_Odm);
1470                 break;
1471         case    ODM_CE:
1472                 odm_RSSIMonitorCheckCE(pDM_Odm);
1473                 break;
1474         case    ODM_AP:
1475                 odm_RSSIMonitorCheckAP(pDM_Odm);
1476                 break;
1477         case    ODM_ADSL:
1478                 /* odm_DIGAP(pDM_Odm); */
1479                 break;
1480         }
1481
1482 }       /*  odm_RSSIMonitorCheck */
1483
1484 void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm)
1485 {
1486 }
1487
1488 static void FindMinimumRSSI(struct adapter *pAdapter)
1489 {
1490         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
1491         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1492         struct mlme_priv        *pmlmepriv = &pAdapter->mlmepriv;
1493
1494         /* 1 1.Determine the minimum RSSI */
1495         if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) &&
1496             (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1497                 pdmpriv->MinUndecoratedPWDBForDM = 0;
1498         if (check_fwstate(pmlmepriv, _FW_LINKED) == true)       /*  Default port */
1499                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1500         else /*  associated entry pwdb */
1501                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1502 }
1503
1504 void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm)
1505 {
1506         struct adapter *Adapter = pDM_Odm->Adapter;
1507         struct hal_data_8188e   *pHalData = GET_HAL_DATA(Adapter);
1508         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1509         int     i;
1510         int     tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1511         u8      sta_cnt = 0;
1512         u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1513         struct sta_info *psta;
1514         u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1515
1516         if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
1517                 return;
1518
1519         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1520                 psta = pDM_Odm->pODM_StaInfo[i];
1521                 if (IS_STA_VALID(psta) &&
1522                     (psta->state & WIFI_ASOC_STATE) &&
1523                     memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) &&
1524                     memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) {
1525                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1526                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1527
1528                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1529                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1530                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1531                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1532                 }
1533         }
1534
1535         for (i = 0; i < sta_cnt; i++) {
1536                 if (PWDB_rssi[i] != (0)) {
1537                         if (pHalData->fw_ractrl) {
1538                                 /*  Report every sta's RSSI to FW */
1539                         } else {
1540                                 ODM_RA_SetRSSI_8188E(
1541                                 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF));
1542                         }
1543                 }
1544         }
1545
1546         if (tmpEntryMaxPWDB != 0)       /*  If associated entry is found */
1547                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1548         else
1549                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1550
1551         if (tmpEntryMinPWDB != 0xff) /*  If associated entry is found */
1552                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1553         else
1554                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1555
1556         FindMinimumRSSI(Adapter);
1557         ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1558 }
1559
1560 void odm_RSSIMonitorCheckAP(struct odm_dm_struct *pDM_Odm)
1561 {
1562 }
1563
1564 void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm)
1565 {
1566         timer_setup(&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, odm_SwAntDivChkAntSwitchCallback, 0);
1567 }
1568
1569 void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm)
1570 {
1571         ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1572 }
1573
1574 void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm)
1575 {
1576         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1577
1578         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->FastAntTrainingTimer);
1579 }
1580
1581 /* 3============================================================ */
1582 /* 3 Tx Power Tracking */
1583 /* 3============================================================ */
1584
1585 void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm)
1586 {
1587         odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
1588 }
1589
1590 void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm)
1591 {
1592         pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
1593         pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
1594         pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
1595         if (*(pDM_Odm->mp_mode) != 1)
1596                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1597         MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
1598
1599         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1600 }
1601
1602 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm)
1603 {
1604         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1605         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1606         /*  HW dynamic mechanism. */
1607         switch  (pDM_Odm->SupportPlatform) {
1608         case    ODM_MP:
1609                 odm_TXPowerTrackingCheckMP(pDM_Odm);
1610                 break;
1611         case    ODM_CE:
1612                 odm_TXPowerTrackingCheckCE(pDM_Odm);
1613                 break;
1614         case    ODM_AP:
1615                 odm_TXPowerTrackingCheckAP(pDM_Odm);
1616                 break;
1617         case    ODM_ADSL:
1618                 break;
1619         }
1620 }
1621
1622 void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm)
1623 {
1624         struct adapter *Adapter = pDM_Odm->Adapter;
1625
1626         if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
1627                 return;
1628
1629         if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) {             /* at least delay 1 sec */
1630                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
1631
1632                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
1633                 return;
1634         } else {
1635                 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter);
1636                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
1637         }
1638 }
1639
1640 void odm_TXPowerTrackingCheckMP(struct odm_dm_struct *pDM_Odm)
1641 {
1642 }
1643
1644 void odm_TXPowerTrackingCheckAP(struct odm_dm_struct *pDM_Odm)
1645 {
1646 }
1647
1648 /* antenna mapping info */
1649 /*  1: right-side antenna */
1650 /*  2/0: left-side antenna */
1651 /* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt:  for right-side antenna:   Ant:1    RxDefaultAnt1 */
1652 /* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt:  for left-side antenna:     Ant:0    RxDefaultAnt2 */
1653 /*  We select left antenna as default antenna in initial process, modify it as needed */
1654 /*  */
1655
1656 /* 3============================================================ */
1657 /* 3 SW Antenna Diversity */
1658 /* 3============================================================ */
1659 void odm_SwAntDivInit(struct odm_dm_struct *pDM_Odm)
1660 {
1661 }
1662
1663 void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, struct odm_phy_status_info *pPhyInfo)
1664 {
1665 }
1666
1667 void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step)
1668 {
1669 }
1670
1671 void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm)
1672 {
1673 }
1674
1675 void odm_SwAntDivChkAntSwitchCallback(struct timer_list *t)
1676 {
1677 }
1678
1679 /* 3============================================================ */
1680 /* 3 SW Antenna Diversity */
1681 /* 3============================================================ */
1682
1683 void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
1684 {
1685         if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
1686                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
1687                 return;
1688         }
1689
1690         if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
1691                 ;
1692         else if (pDM_Odm->SupportICType == ODM_RTL8188E)
1693                 ODM_AntennaDiversityInit_88E(pDM_Odm);
1694 }
1695
1696 void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate)
1697 {
1698         struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1699
1700         if (pDM_SWAT_Table->antsel == 1) {
1701                 if (isCCKrate) {
1702                         pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++;
1703                 } else {
1704                         pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++;
1705                         pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll;
1706                 }
1707         } else {
1708                 if (isCCKrate) {
1709                         pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++;
1710                 } else {
1711                         pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++;
1712                         pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll;
1713                 }
1714         }
1715 }
1716
1717 void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
1718 {
1719         if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
1720                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
1721                 return;
1722         }
1723
1724         if (pDM_Odm->SupportICType == ODM_RTL8188E)
1725                 ODM_AntennaDiversity_88E(pDM_Odm);
1726 }
1727
1728 /* EDCA Turbo */
1729 void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
1730 {
1731         struct adapter *Adapter = pDM_Odm->Adapter;
1732         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1733         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1734         Adapter->recvpriv.bIsAnyNonBEPkts = false;
1735
1736         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1737         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1738         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1739         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1740 }       /*  ODM_InitEdcaTurbo */
1741
1742 void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
1743 {
1744         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1745         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1746         /*  HW dynamic mechanism. */
1747         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n"));
1748
1749         if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1750                 return;
1751
1752         switch  (pDM_Odm->SupportPlatform) {
1753         case    ODM_MP:
1754                 break;
1755         case    ODM_CE:
1756                 odm_EdcaTurboCheckCE(pDM_Odm);
1757                 break;
1758         case    ODM_AP:
1759         case    ODM_ADSL:
1760                 break;
1761         }
1762         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n"));
1763 }       /*  odm_CheckEdcaTurbo */
1764
1765 void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm)
1766 {
1767         struct adapter *Adapter = pDM_Odm->Adapter;
1768         u32     trafficIndex;
1769         u32     edca_param;
1770         u64     cur_tx_bytes = 0;
1771         u64     cur_rx_bytes = 0;
1772         u8      bbtchange = false;
1773         struct hal_data_8188e           *pHalData = GET_HAL_DATA(Adapter);
1774         struct xmit_priv                *pxmitpriv = &(Adapter->xmitpriv);
1775         struct recv_priv                *precvpriv = &(Adapter->recvpriv);
1776         struct registry_priv    *pregpriv = &Adapter->registrypriv;
1777         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
1778         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1779
1780         if ((pregpriv->wifi_spec == 1))/*  (pmlmeinfo->HT_enable == 0)) */
1781                 goto dm_CheckEdcaTurbo_EXIT;
1782
1783         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
1784                 goto dm_CheckEdcaTurbo_EXIT;
1785
1786         /*  Check if the status needs to be changed. */
1787         if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1788                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1789                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1790
1791                 /* traffic, TX or RX */
1792                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1793                     (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1794                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1795                                 /*  Uplink TP is present. */
1796                                 trafficIndex = UP_LINK;
1797                         } else {
1798                                 /*  Balance TP is present. */
1799                                 trafficIndex = DOWN_LINK;
1800                         }
1801                 } else {
1802                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1803                                 /*  Downlink TP is present. */
1804                                 trafficIndex = DOWN_LINK;
1805                         } else {
1806                                 /*  Balance TP is present. */
1807                                 trafficIndex = UP_LINK;
1808                         }
1809                 }
1810
1811                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1812                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1813                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1814                         else
1815                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1816
1817                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
1818
1819                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1820                 }
1821
1822                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1823         } else {
1824                 /*  Turn Off EDCA turbo here. */
1825                 /*  Restore original EDCA according to the declaration of AP. */
1826                  if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1827                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
1828                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1829                 }
1830         }
1831
1832 dm_CheckEdcaTurbo_EXIT:
1833         /*  Set variables for next time. */
1834         precvpriv->bIsAnyNonBEPkts = false;
1835         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1836         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1837 }
1838
1839 /*  need to ODM CE Platform */
1840 /* move to here for ANT detection mechanism using */
1841
1842 u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1843 {
1844         u32 psd_report;
1845
1846         /* Set DCO frequency index, offset=(40MHz/SamplePts)*point */
1847         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1848
1849         /* Start PSD calculation, Reg808[22]=0->1 */
1850         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
1851         /* Need to wait for HW PSD report */
1852         ODM_StallExecution(30);
1853         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
1854         /* Read PSD report, Reg8B4[15:0] */
1855         psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1856
1857         psd_report = (u32) (ConvertTo_dB(psd_report))+(u32)(initial_gain_psd-0x1c);
1858
1859         return psd_report;
1860 }
1861
1862 u32 ConvertTo_dB(u32 Value)
1863 {
1864         u8 i;
1865         u8 j;
1866         u32 dB;
1867
1868         Value = Value & 0xFFFF;
1869         for (i = 0; i < 8; i++) {
1870                 if (Value <= dB_Invert_Table[i][11])
1871                         break;
1872         }
1873
1874         if (i >= 8)
1875                 return 96;      /*  maximum 96 dB */
1876
1877         for (j = 0; j < 12; j++) {
1878                 if (Value <= dB_Invert_Table[i][j])
1879                         break;
1880         }
1881
1882         dB = i*12 + j + 1;
1883
1884         return dB;
1885 }
1886
1887 /*  2011/09/22 MH Add for 92D global spin lock utilization. */
1888 void odm_GlobalAdapterCheck(void)
1889 {
1890 }       /*  odm_GlobalAdapterCheck */
1891
1892 /*  Description: */
1893 /*      Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1894 /*  Added by Joseph, 2012.03.22 */
1895 void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm)
1896 {
1897         struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1898
1899         pDM_SWAT_Table->ANTA_ON = true;
1900         pDM_SWAT_Table->ANTB_ON = true;
1901 }
1902
1903 /* 2 8723A ANT DETECT */
1904
1905 static void odm_PHY_SaveAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegisterNum)
1906 {
1907         u32 i;
1908
1909         /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1910         for (i = 0; i < RegisterNum; i++)
1911                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1912 }
1913
1914 static void odm_PHY_ReloadAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegiesterNum)
1915 {
1916         u32 i;
1917
1918         for (i = 0; i < RegiesterNum; i++)
1919                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1920 }
1921
1922 /* 2 8723A ANT DETECT */
1923 /*  Description: */
1924 /*      Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1925 /*      This function is cooperated with BB team Neil. */
1926 bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode)
1927 {
1928         struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1929         u32 CurrentChannel, RfLoopReg;
1930         u8 n;
1931         u32 Reg88c, Regc08, Reg874, Regc50;
1932         u8 initial_gain = 0x5a;
1933         u32 PSD_report_tmp;
1934         u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1935         bool bResult = true;
1936         u32 AFE_Backup[16];
1937         u32 AFE_REG_8723A[16] = {
1938                 rRx_Wait_CCA, rTx_CCK_RFON,
1939                 rTx_CCK_BBON, rTx_OFDM_RFON,
1940                 rTx_OFDM_BBON, rTx_To_Rx,
1941                 rTx_To_Tx, rRx_CCK,
1942                 rRx_OFDM, rRx_Wait_RIFS,
1943                 rRx_TO_Rx, rStandby,
1944                 rSleep, rPMPD_ANAEN,
1945                 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1946
1947         if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C)))
1948                 return bResult;
1949
1950         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1951                 return bResult;
1952
1953         if (pDM_Odm->SupportICType == ODM_RTL8192C) {
1954                 /* Which path in ADC/DAC is turnned on for PSD: both I/Q */
1955                 ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3);
1956                 /* Ageraged number: 8 */
1957                 ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1);
1958                 /* pts = 128; */
1959                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
1960         }
1961
1962         /* 1 Backup Current RF/BB Settings */
1963
1964         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1965         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1966         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  /*  change to Antenna A */
1967         /*  Step 1: USE IQK to transmitter single tone */
1968
1969         ODM_StallExecution(10);
1970
1971         /* Store A Path Register 88c, c08, 874, c50 */
1972         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1973         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1974         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1975         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1976
1977         /*  Store AFE Registers */
1978         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1979
1980         /* Set PSD 128 pts */
1981         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  /* 128 pts */
1982
1983         /*  To SET CH1 to do */
1984         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
1985
1986         /*  AFE all on step */
1987         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1988         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1989         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1990         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1991         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1992         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1993         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1994         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1995         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1996         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1997         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1998         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1999         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
2000         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
2001         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
2002         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
2003
2004         /*  3 wire Disable */
2005         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
2006
2007         /* BB IQK Setting */
2008         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
2009         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
2010
2011         /* IQK setting tone@ 4.34Mhz */
2012         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
2013         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
2014
2015         /* Page B init */
2016         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
2017         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
2018         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
2019         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
2020         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
2021         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
2022         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
2023
2024         /* RF loop Setting */
2025         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
2026
2027         /* IQK Single tone start */
2028         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
2029         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
2030         ODM_StallExecution(1000);
2031         PSD_report_tmp = 0x0;
2032
2033         for (n = 0; n < 2; n++) {
2034                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
2035                 if (PSD_report_tmp > AntA_report)
2036                         AntA_report = PSD_report_tmp;
2037         }
2038
2039         PSD_report_tmp = 0x0;
2040
2041         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  /*  change to Antenna B */
2042         ODM_StallExecution(10);
2043
2044         for (n = 0; n < 2; n++) {
2045                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
2046                 if (PSD_report_tmp > AntB_report)
2047                         AntB_report = PSD_report_tmp;
2048         }
2049
2050         /*  change to open case */
2051         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  /*  change to Ant A and B all open case */
2052         ODM_StallExecution(10);
2053
2054         for (n = 0; n < 2; n++) {
2055                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
2056                 if (PSD_report_tmp > AntO_report)
2057                         AntO_report = PSD_report_tmp;
2058         }
2059
2060         /* Close IQK Single Tone function */
2061         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
2062         PSD_report_tmp = 0x0;
2063
2064         /* 1 Return to antanna A */
2065         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
2066         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
2067         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
2068         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
2069         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
2070         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
2071         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
2072         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
2073
2074         /* Reload AFE Registers */
2075         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
2076
2077         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report));
2078         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report));
2079         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d\n", 2416, AntO_report));
2080
2081         if (pDM_Odm->SupportICType == ODM_RTL8723A) {
2082         /* 2 Test Ant B based on Ant A is ON */
2083                 if (mode == ANTTESTB) {
2084                         if (AntA_report >= 100) {
2085                                 if (AntB_report > (AntA_report+1)) {
2086                                         pDM_SWAT_Table->ANTB_ON = false;
2087                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
2088                                 } else {
2089                                         pDM_SWAT_Table->ANTB_ON = true;
2090                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
2091                                 }
2092                         } else {
2093                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
2094                                 pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
2095                                 bResult = false;
2096                         }
2097                 } else if (mode == ANTTESTALL) {
2098                         /* 2 Test Ant A and B based on DPDT Open */
2099                         if ((AntO_report >= 100)&(AntO_report < 118)) {
2100                                 if (AntA_report > (AntO_report+1)) {
2101                                         pDM_SWAT_Table->ANTA_ON = false;
2102                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
2103                                 } else {
2104                                         pDM_SWAT_Table->ANTA_ON = true;
2105                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
2106                                 }
2107
2108                                 if (AntB_report > (AntO_report+2)) {
2109                                         pDM_SWAT_Table->ANTB_ON = false;
2110                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
2111                                 } else {
2112                                         pDM_SWAT_Table->ANTB_ON = true;
2113                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
2114                                 }
2115                         }
2116                 }
2117         } else if (pDM_Odm->SupportICType == ODM_RTL8192C) {
2118                 if (AntA_report >= 100) {
2119                         if (AntB_report > (AntA_report+2)) {
2120                                 pDM_SWAT_Table->ANTA_ON = false;
2121                                 pDM_SWAT_Table->ANTB_ON = true;
2122                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
2123                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n"));
2124                         } else if (AntA_report > (AntB_report+2)) {
2125                                 pDM_SWAT_Table->ANTA_ON = true;
2126                                 pDM_SWAT_Table->ANTB_ON = false;
2127                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
2128                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
2129                         } else {
2130                                 pDM_SWAT_Table->ANTA_ON = true;
2131                                 pDM_SWAT_Table->ANTB_ON = true;
2132                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
2133                                              ("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
2134                         }
2135                 } else {
2136                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
2137                         pDM_SWAT_Table->ANTA_ON = true; /*  Set Antenna A on as default */
2138                         pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
2139                         bResult = false;
2140                 }
2141         }
2142         return bResult;
2143 }
2144
2145 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
2146 void odm_dtc(struct odm_dm_struct *pDM_Odm)
2147 {
2148 }