drivers/staging/octeon/octeon-stubs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE        512
   3
   4 #ifndef XKPHYS_TO_PHYS
   5 # define XKPHYS_TO_PHYS(p)                      (p)
   6 #endif
   7
   8 #define OCTEON_IRQ_WORKQ0 0
   9 #define OCTEON_IRQ_RML 0
  10 #define OCTEON_IRQ_TIMER1 0
  11 #define OCTEON_IS_MODEL(x) 0
  12 #define octeon_has_feature(x)   0
  13 #define octeon_get_clock_rate() 0
  14
  15 #define CVMX_SYNCIOBDMA         do { } while (0)
  16
  17 #define CVMX_HELPER_INPUT_TAG_TYPE      0
  18 #define CVMX_HELPER_FIRST_MBUFF_SKIP    7
  19 #define CVMX_FAU_REG_END                (2048)
  20 #define CVMX_FPA_OUTPUT_BUFFER_POOL         (2)
  21 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    16
  22 #define CVMX_FPA_PACKET_POOL                (0)
  23 #define CVMX_FPA_PACKET_POOL_SIZE           16
  24 #define CVMX_FPA_WQE_POOL                   (1)
  25 #define CVMX_FPA_WQE_POOL_SIZE              16
  26 #define CVMX_GMXX_RXX_ADR_CAM_EN(a, b)  ((a) + (b))
  27 #define CVMX_GMXX_RXX_ADR_CTL(a, b)     ((a) + (b))
  28 #define CVMX_GMXX_PRTX_CFG(a, b)        ((a) + (b))
  29 #define CVMX_GMXX_RXX_FRM_MAX(a, b)     ((a) + (b))
  30 #define CVMX_GMXX_RXX_JABBER(a, b)      ((a) + (b))
  31 #define CVMX_IPD_CTL_STATUS             0
  32 #define CVMX_PIP_FRM_LEN_CHKX(a)        (a)
  33 #define CVMX_PIP_NUM_INPUT_PORTS        1
  34 #define CVMX_SCR_SCRATCH                0
  35 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0     2
  36 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1     2
  37 #define CVMX_IPD_SUB_PORT_FCS           0
  38 #define CVMX_SSO_WQ_IQ_DIS              0
  39 #define CVMX_SSO_WQ_INT                 0
  40 #define CVMX_POW_WQ_INT                 0
  41 #define CVMX_SSO_WQ_INT_PC              0
  42 #define CVMX_NPI_RSL_INT_BLOCKS         0
  43 #define CVMX_POW_WQ_INT_PC              0
  44
  45 union cvmx_pip_wqe_word2 {
  46         uint64_t u64;
  47         struct {
  48                 uint64_t bufs:8;
  49                 uint64_t ip_offset:8;
  50                 uint64_t vlan_valid:1;
  51                 uint64_t vlan_stacked:1;
  52                 uint64_t unassigned:1;
  53                 uint64_t vlan_cfi:1;
  54                 uint64_t vlan_id:12;
  55                 uint64_t pr:4;
  56                 uint64_t unassigned2:8;
  57                 uint64_t dec_ipcomp:1;
  58                 uint64_t tcp_or_udp:1;
  59                 uint64_t dec_ipsec:1;
  60                 uint64_t is_v6:1;
  61                 uint64_t software:1;
  62                 uint64_t L4_error:1;
  63                 uint64_t is_frag:1;
  64                 uint64_t IP_exc:1;
  65                 uint64_t is_bcast:1;
  66                 uint64_t is_mcast:1;
  67                 uint64_t not_IP:1;
  68                 uint64_t rcv_error:1;
  69                 uint64_t err_code:8;
  70         } s;
  71         struct {
  72                 uint64_t bufs:8;
  73                 uint64_t ip_offset:8;
  74                 uint64_t vlan_valid:1;
  75                 uint64_t vlan_stacked:1;
  76                 uint64_t unassigned:1;
  77                 uint64_t vlan_cfi:1;
  78                 uint64_t vlan_id:12;
  79                 uint64_t port:12;
  80                 uint64_t dec_ipcomp:1;
  81                 uint64_t tcp_or_udp:1;
  82                 uint64_t dec_ipsec:1;
  83                 uint64_t is_v6:1;
  84                 uint64_t software:1;
  85                 uint64_t L4_error:1;
  86                 uint64_t is_frag:1;
  87                 uint64_t IP_exc:1;
  88                 uint64_t is_bcast:1;
  89                 uint64_t is_mcast:1;
  90                 uint64_t not_IP:1;
  91                 uint64_t rcv_error:1;
  92                 uint64_t err_code:8;
  93         } s_cn68xx;
  94
  95         struct {
  96                 uint64_t unused1:16;
  97                 uint64_t vlan:16;
  98                 uint64_t unused2:32;
  99         } svlan;
 100         struct {
 101                 uint64_t bufs:8;
 102                 uint64_t unused:8;
 103                 uint64_t vlan_valid:1;
 104                 uint64_t vlan_stacked:1;
 105                 uint64_t unassigned:1;
 106                 uint64_t vlan_cfi:1;
 107                 uint64_t vlan_id:12;
 108                 uint64_t pr:4;
 109                 uint64_t unassigned2:12;
 110                 uint64_t software:1;
 111                 uint64_t unassigned3:1;
 112                 uint64_t is_rarp:1;
 113                 uint64_t is_arp:1;
 114                 uint64_t is_bcast:1;
 115                 uint64_t is_mcast:1;
 116                 uint64_t not_IP:1;
 117                 uint64_t rcv_error:1;
 118                 uint64_t err_code:8;
 119         } snoip;
 120
 121 };
 122
 123 union cvmx_pip_wqe_word0 {
 124         struct {
 125                 uint64_t next_ptr:40;
 126                 uint8_t unused;
 127                 __wsum hw_chksum;
 128         } cn38xx;
 129         struct {
 130                 uint64_t pknd:6;        /* 0..5 */
 131                 uint64_t unused2:2;     /* 6..7 */
 132                 uint64_t bpid:6;        /* 8..13 */
 133                 uint64_t unused1:18;    /* 14..31 */
 134                 uint64_t l2ptr:8;       /* 32..39 */
 135                 uint64_t l3ptr:8;       /* 40..47 */
 136                 uint64_t unused0:8;     /* 48..55 */
 137                 uint64_t l4ptr:8;       /* 56..63 */
 138         } cn68xx;
 139 };
 140
 141 union cvmx_wqe_word0 {
 142         uint64_t u64;
 143         union cvmx_pip_wqe_word0 pip;
 144 };
 145
 146 union cvmx_wqe_word1 {
 147         uint64_t u64;
 148         struct {
 149                 uint64_t tag:32;
 150                 uint64_t tag_type:2;
 151                 uint64_t varies:14;
 152                 uint64_t len:16;
 153         };
 154         struct {
 155                 uint64_t tag:32;
 156                 uint64_t tag_type:2;
 157                 uint64_t zero_2:3;
 158                 uint64_t grp:6;
 159                 uint64_t zero_1:1;
 160                 uint64_t qos:3;
 161                 uint64_t zero_0:1;
 162                 uint64_t len:16;
 163         } cn68xx;
 164         struct {
 165                 uint64_t tag:32;
 166                 uint64_t tag_type:2;
 167                 uint64_t zero_2:1;
 168                 uint64_t grp:4;
 169                 uint64_t qos:3;
 170                 uint64_t ipprt:6;
 171                 uint64_t len:16;
 172         } cn38xx;
 173 };
 174
 175 union cvmx_buf_ptr {
 176         void *ptr;
 177         uint64_t u64;
 178         struct {
 179                 uint64_t i:1;
 180                 uint64_t back:4;
 181                 uint64_t pool:3;
 182                 uint64_t size:16;
 183                 uint64_t addr:40;
 184         } s;
 185 };
 186
 187 struct cvmx_wqe {
 188         union cvmx_wqe_word0 word0;
 189         union cvmx_wqe_word1 word1;
 190         union cvmx_pip_wqe_word2 word2;
 191         union cvmx_buf_ptr packet_ptr;
 192         uint8_t packet_data[96];
 193 };
 194
 195 union cvmx_helper_link_info {
 196         uint64_t u64;
 197         struct {
 198                 uint64_t reserved_20_63:44;
 199                 uint64_t link_up:1;         /**< Is the physical link up? */
 200                 uint64_t full_duplex:1;     /**< 1 if the link is full duplex */
 201                 uint64_t speed:18;          /**< Speed of the link in Mbps */
 202         } s;
 203 };
 204
 205 enum cvmx_fau_reg_32 {
 206         CVMX_FAU_REG_32_START   = 0,
 207 };
 208
 209 enum cvmx_fau_op_size {
 210         CVMX_FAU_OP_SIZE_8 = 0,
 211         CVMX_FAU_OP_SIZE_16 = 1,
 212         CVMX_FAU_OP_SIZE_32 = 2,
 213         CVMX_FAU_OP_SIZE_64 = 3
 214 };
 215
 216 typedef enum {
 217         CVMX_SPI_MODE_UNKNOWN = 0,
 218         CVMX_SPI_MODE_TX_HALFPLEX = 1,
 219         CVMX_SPI_MODE_RX_HALFPLEX = 2,
 220         CVMX_SPI_MODE_DUPLEX = 3
 221 } cvmx_spi_mode_t;
 222
 223 typedef enum {
 224         CVMX_HELPER_INTERFACE_MODE_DISABLED,
 225         CVMX_HELPER_INTERFACE_MODE_RGMII,
 226         CVMX_HELPER_INTERFACE_MODE_GMII,
 227         CVMX_HELPER_INTERFACE_MODE_SPI,
 228         CVMX_HELPER_INTERFACE_MODE_PCIE,
 229         CVMX_HELPER_INTERFACE_MODE_XAUI,
 230         CVMX_HELPER_INTERFACE_MODE_SGMII,
 231         CVMX_HELPER_INTERFACE_MODE_PICMG,
 232         CVMX_HELPER_INTERFACE_MODE_NPI,
 233         CVMX_HELPER_INTERFACE_MODE_LOOP,
 234 } cvmx_helper_interface_mode_t;
 235
 236 typedef enum {
 237         CVMX_POW_WAIT = 1,
 238         CVMX_POW_NO_WAIT = 0,
 239 } cvmx_pow_wait_t;
 240
 241 typedef enum {
 242         CVMX_PKO_LOCK_NONE = 0,
 243         CVMX_PKO_LOCK_ATOMIC_TAG = 1,
 244         CVMX_PKO_LOCK_CMD_QUEUE = 2,
 245 } cvmx_pko_lock_t;
 246
 247 typedef enum {
 248         CVMX_PKO_SUCCESS,
 249         CVMX_PKO_INVALID_PORT,
 250         CVMX_PKO_INVALID_QUEUE,
 251         CVMX_PKO_INVALID_PRIORITY,
 252         CVMX_PKO_NO_MEMORY,
 253         CVMX_PKO_PORT_ALREADY_SETUP,
 254         CVMX_PKO_CMD_QUEUE_INIT_ERROR
 255 } cvmx_pko_status_t;
 256
 257 enum cvmx_pow_tag_type {
 258         CVMX_POW_TAG_TYPE_ORDERED   = 0L,
 259         CVMX_POW_TAG_TYPE_ATOMIC    = 1L,
 260         CVMX_POW_TAG_TYPE_NULL      = 2L,
 261         CVMX_POW_TAG_TYPE_NULL_NULL = 3L
 262 };
 263
 264 union cvmx_ipd_ctl_status {
 265         uint64_t u64;
 266         struct cvmx_ipd_ctl_status_s {
 267                 uint64_t reserved_18_63:46;
 268                 uint64_t use_sop:1;
 269                 uint64_t rst_done:1;
 270                 uint64_t clken:1;
 271                 uint64_t no_wptr:1;
 272                 uint64_t pq_apkt:1;
 273                 uint64_t pq_nabuf:1;
 274                 uint64_t ipd_full:1;
 275                 uint64_t pkt_off:1;
 276                 uint64_t len_m8:1;
 277                 uint64_t reset:1;
 278                 uint64_t addpkt:1;
 279                 uint64_t naddbuf:1;
 280                 uint64_t pkt_lend:1;
 281                 uint64_t wqe_lend:1;
 282                 uint64_t pbp_en:1;
 283                 uint64_t opc_mode:2;
 284                 uint64_t ipd_en:1;
 285         } s;
 286         struct cvmx_ipd_ctl_status_cn30xx {
 287                 uint64_t reserved_10_63:54;
 288                 uint64_t len_m8:1;
 289                 uint64_t reset:1;
 290                 uint64_t addpkt:1;
 291                 uint64_t naddbuf:1;
 292                 uint64_t pkt_lend:1;
 293                 uint64_t wqe_lend:1;
 294                 uint64_t pbp_en:1;
 295                 uint64_t opc_mode:2;
 296                 uint64_t ipd_en:1;
 297         } cn30xx;
 298         struct cvmx_ipd_ctl_status_cn38xxp2 {
 299                 uint64_t reserved_9_63:55;
 300                 uint64_t reset:1;
 301                 uint64_t addpkt:1;
 302                 uint64_t naddbuf:1;
 303                 uint64_t pkt_lend:1;
 304                 uint64_t wqe_lend:1;
 305                 uint64_t pbp_en:1;
 306                 uint64_t opc_mode:2;
 307                 uint64_t ipd_en:1;
 308         } cn38xxp2;
 309         struct cvmx_ipd_ctl_status_cn50xx {
 310                 uint64_t reserved_15_63:49;
 311                 uint64_t no_wptr:1;
 312                 uint64_t pq_apkt:1;
 313                 uint64_t pq_nabuf:1;
 314                 uint64_t ipd_full:1;
 315                 uint64_t pkt_off:1;
 316                 uint64_t len_m8:1;
 317                 uint64_t reset:1;
 318                 uint64_t addpkt:1;
 319                 uint64_t naddbuf:1;
 320                 uint64_t pkt_lend:1;
 321                 uint64_t wqe_lend:1;
 322                 uint64_t pbp_en:1;
 323                 uint64_t opc_mode:2;
 324                 uint64_t ipd_en:1;
 325         } cn50xx;
 326         struct cvmx_ipd_ctl_status_cn58xx {
 327                 uint64_t reserved_12_63:52;
 328                 uint64_t ipd_full:1;
 329                 uint64_t pkt_off:1;
 330                 uint64_t len_m8:1;
 331                 uint64_t reset:1;
 332                 uint64_t addpkt:1;
 333                 uint64_t naddbuf:1;
 334                 uint64_t pkt_lend:1;
 335                 uint64_t wqe_lend:1;
 336                 uint64_t pbp_en:1;
 337                 uint64_t opc_mode:2;
 338                 uint64_t ipd_en:1;
 339         } cn58xx;
 340         struct cvmx_ipd_ctl_status_cn63xxp1 {
 341                 uint64_t reserved_16_63:48;
 342                 uint64_t clken:1;
 343                 uint64_t no_wptr:1;
 344                 uint64_t pq_apkt:1;
 345                 uint64_t pq_nabuf:1;
 346                 uint64_t ipd_full:1;
 347                 uint64_t pkt_off:1;
 348                 uint64_t len_m8:1;
 349                 uint64_t reset:1;
 350                 uint64_t addpkt:1;
 351                 uint64_t naddbuf:1;
 352                 uint64_t pkt_lend:1;
 353                 uint64_t wqe_lend:1;
 354                 uint64_t pbp_en:1;
 355                 uint64_t opc_mode:2;
 356                 uint64_t ipd_en:1;
 357         } cn63xxp1;
 358 };
 359
 360 union cvmx_ipd_sub_port_fcs {
 361         uint64_t u64;
 362         struct cvmx_ipd_sub_port_fcs_s {
 363                 uint64_t port_bit:32;
 364                 uint64_t reserved_32_35:4;
 365                 uint64_t port_bit2:4;
 366                 uint64_t reserved_40_63:24;
 367         } s;
 368         struct cvmx_ipd_sub_port_fcs_cn30xx {
 369                 uint64_t port_bit:3;
 370                 uint64_t reserved_3_63:61;
 371         } cn30xx;
 372         struct cvmx_ipd_sub_port_fcs_cn38xx {
 373                 uint64_t port_bit:32;
 374                 uint64_t reserved_32_63:32;
 375         } cn38xx;
 376 };
 377
 378 union cvmx_ipd_sub_port_qos_cnt {
 379         uint64_t u64;
 380         struct cvmx_ipd_sub_port_qos_cnt_s {
 381                 uint64_t cnt:32;
 382                 uint64_t port_qos:9;
 383                 uint64_t reserved_41_63:23;
 384         } s;
 385 };
 386
 387 typedef struct {
 388         uint32_t dropped_octets;
 389         uint32_t dropped_packets;
 390         uint32_t pci_raw_packets;
 391         uint32_t octets;
 392         uint32_t packets;
 393         uint32_t multicast_packets;
 394         uint32_t broadcast_packets;
 395         uint32_t len_64_packets;
 396         uint32_t len_65_127_packets;
 397         uint32_t len_128_255_packets;
 398         uint32_t len_256_511_packets;
 399         uint32_t len_512_1023_packets;
 400         uint32_t len_1024_1518_packets;
 401         uint32_t len_1519_max_packets;
 402         uint32_t fcs_align_err_packets;
 403         uint32_t runt_packets;
 404         uint32_t runt_crc_packets;
 405         uint32_t oversize_packets;
 406         uint32_t oversize_crc_packets;
 407         uint32_t inb_packets;
 408         uint64_t inb_octets;
 409         uint16_t inb_errors;
 410 } cvmx_pip_port_status_t;
 411
 412 typedef struct {
 413         uint32_t packets;
 414         uint64_t octets;
 415         uint64_t doorbell;
 416 } cvmx_pko_port_status_t;
 417
 418 union cvmx_pip_frm_len_chkx {
 419         uint64_t u64;
 420         struct cvmx_pip_frm_len_chkx_s {
 421                 uint64_t reserved_32_63:32;
 422                 uint64_t maxlen:16;
 423                 uint64_t minlen:16;
 424         } s;
 425 };
 426
 427 union cvmx_gmxx_rxx_frm_ctl {
 428         uint64_t u64;
 429         struct cvmx_gmxx_rxx_frm_ctl_s {
 430                 uint64_t pre_chk:1;
 431                 uint64_t pre_strp:1;
 432                 uint64_t ctl_drp:1;
 433                 uint64_t ctl_bck:1;
 434                 uint64_t ctl_mcst:1;
 435                 uint64_t ctl_smac:1;
 436                 uint64_t pre_free:1;
 437                 uint64_t vlan_len:1;
 438                 uint64_t pad_len:1;
 439                 uint64_t pre_align:1;
 440                 uint64_t null_dis:1;
 441                 uint64_t reserved_11_11:1;
 442                 uint64_t ptp_mode:1;
 443                 uint64_t reserved_13_63:51;
 444         } s;
 445         struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
 446                 uint64_t pre_chk:1;
 447                 uint64_t pre_strp:1;
 448                 uint64_t ctl_drp:1;
 449                 uint64_t ctl_bck:1;
 450                 uint64_t ctl_mcst:1;
 451                 uint64_t ctl_smac:1;
 452                 uint64_t pre_free:1;
 453                 uint64_t vlan_len:1;
 454                 uint64_t pad_len:1;
 455                 uint64_t reserved_9_63:55;
 456         } cn30xx;
 457         struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
 458                 uint64_t pre_chk:1;
 459                 uint64_t pre_strp:1;
 460                 uint64_t ctl_drp:1;
 461                 uint64_t ctl_bck:1;
 462                 uint64_t ctl_mcst:1;
 463                 uint64_t ctl_smac:1;
 464                 uint64_t pre_free:1;
 465                 uint64_t vlan_len:1;
 466                 uint64_t reserved_8_63:56;
 467         } cn31xx;
 468         struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
 469                 uint64_t pre_chk:1;
 470                 uint64_t pre_strp:1;
 471                 uint64_t ctl_drp:1;
 472                 uint64_t ctl_bck:1;
 473                 uint64_t ctl_mcst:1;
 474                 uint64_t ctl_smac:1;
 475                 uint64_t pre_free:1;
 476                 uint64_t reserved_7_8:2;
 477                 uint64_t pre_align:1;
 478                 uint64_t null_dis:1;
 479                 uint64_t reserved_11_63:53;
 480         } cn50xx;
 481         struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
 482                 uint64_t pre_chk:1;
 483                 uint64_t pre_strp:1;
 484                 uint64_t ctl_drp:1;
 485                 uint64_t ctl_bck:1;
 486                 uint64_t ctl_mcst:1;
 487                 uint64_t ctl_smac:1;
 488                 uint64_t pre_free:1;
 489                 uint64_t reserved_7_8:2;
 490                 uint64_t pre_align:1;
 491                 uint64_t reserved_10_63:54;
 492         } cn56xxp1;
 493         struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
 494                 uint64_t pre_chk:1;
 495                 uint64_t pre_strp:1;
 496                 uint64_t ctl_drp:1;
 497                 uint64_t ctl_bck:1;
 498                 uint64_t ctl_mcst:1;
 499                 uint64_t ctl_smac:1;
 500                 uint64_t pre_free:1;
 501                 uint64_t vlan_len:1;
 502                 uint64_t pad_len:1;
 503                 uint64_t pre_align:1;
 504                 uint64_t null_dis:1;
 505                 uint64_t reserved_11_63:53;
 506         } cn58xx;
 507         struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
 508                 uint64_t pre_chk:1;
 509                 uint64_t pre_strp:1;
 510                 uint64_t ctl_drp:1;
 511                 uint64_t ctl_bck:1;
 512                 uint64_t ctl_mcst:1;
 513                 uint64_t ctl_smac:1;
 514                 uint64_t pre_free:1;
 515                 uint64_t reserved_7_8:2;
 516                 uint64_t pre_align:1;
 517                 uint64_t null_dis:1;
 518                 uint64_t reserved_11_11:1;
 519                 uint64_t ptp_mode:1;
 520                 uint64_t reserved_13_63:51;
 521         } cn61xx;
 522 };
 523
 524 union cvmx_gmxx_rxx_int_reg {
 525         uint64_t u64;
 526         struct cvmx_gmxx_rxx_int_reg_s {
 527                 uint64_t minerr:1;
 528                 uint64_t carext:1;
 529                 uint64_t maxerr:1;
 530                 uint64_t jabber:1;
 531                 uint64_t fcserr:1;
 532                 uint64_t alnerr:1;
 533                 uint64_t lenerr:1;
 534                 uint64_t rcverr:1;
 535                 uint64_t skperr:1;
 536                 uint64_t niberr:1;
 537                 uint64_t ovrerr:1;
 538                 uint64_t pcterr:1;
 539                 uint64_t rsverr:1;
 540                 uint64_t falerr:1;
 541                 uint64_t coldet:1;
 542                 uint64_t ifgerr:1;
 543                 uint64_t phy_link:1;
 544                 uint64_t phy_spd:1;
 545                 uint64_t phy_dupx:1;
 546                 uint64_t pause_drp:1;
 547                 uint64_t loc_fault:1;
 548                 uint64_t rem_fault:1;
 549                 uint64_t bad_seq:1;
 550                 uint64_t bad_term:1;
 551                 uint64_t unsop:1;
 552                 uint64_t uneop:1;
 553                 uint64_t undat:1;
 554                 uint64_t hg2fld:1;
 555                 uint64_t hg2cc:1;
 556                 uint64_t reserved_29_63:35;
 557         } s;
 558         struct cvmx_gmxx_rxx_int_reg_cn30xx {
 559                 uint64_t minerr:1;
 560                 uint64_t carext:1;
 561                 uint64_t maxerr:1;
 562                 uint64_t jabber:1;
 563                 uint64_t fcserr:1;
 564                 uint64_t alnerr:1;
 565                 uint64_t lenerr:1;
 566                 uint64_t rcverr:1;
 567                 uint64_t skperr:1;
 568                 uint64_t niberr:1;
 569                 uint64_t ovrerr:1;
 570                 uint64_t pcterr:1;
 571                 uint64_t rsverr:1;
 572                 uint64_t falerr:1;
 573                 uint64_t coldet:1;
 574                 uint64_t ifgerr:1;
 575                 uint64_t phy_link:1;
 576                 uint64_t phy_spd:1;
 577                 uint64_t phy_dupx:1;
 578                 uint64_t reserved_19_63:45;
 579         } cn30xx;
 580         struct cvmx_gmxx_rxx_int_reg_cn50xx {
 581                 uint64_t reserved_0_0:1;
 582                 uint64_t carext:1;
 583                 uint64_t reserved_2_2:1;
 584                 uint64_t jabber:1;
 585                 uint64_t fcserr:1;
 586                 uint64_t alnerr:1;
 587                 uint64_t reserved_6_6:1;
 588                 uint64_t rcverr:1;
 589                 uint64_t skperr:1;
 590                 uint64_t niberr:1;
 591                 uint64_t ovrerr:1;
 592                 uint64_t pcterr:1;
 593                 uint64_t rsverr:1;
 594                 uint64_t falerr:1;
 595                 uint64_t coldet:1;
 596                 uint64_t ifgerr:1;
 597                 uint64_t phy_link:1;
 598                 uint64_t phy_spd:1;
 599                 uint64_t phy_dupx:1;
 600                 uint64_t pause_drp:1;
 601                 uint64_t reserved_20_63:44;
 602         } cn50xx;
 603         struct cvmx_gmxx_rxx_int_reg_cn52xx {
 604                 uint64_t reserved_0_0:1;
 605                 uint64_t carext:1;
 606                 uint64_t reserved_2_2:1;
 607                 uint64_t jabber:1;
 608                 uint64_t fcserr:1;
 609                 uint64_t reserved_5_6:2;
 610                 uint64_t rcverr:1;
 611                 uint64_t skperr:1;
 612                 uint64_t reserved_9_9:1;
 613                 uint64_t ovrerr:1;
 614                 uint64_t pcterr:1;
 615                 uint64_t rsverr:1;
 616                 uint64_t falerr:1;
 617                 uint64_t coldet:1;
 618                 uint64_t ifgerr:1;
 619                 uint64_t reserved_16_18:3;
 620                 uint64_t pause_drp:1;
 621                 uint64_t loc_fault:1;
 622                 uint64_t rem_fault:1;
 623                 uint64_t bad_seq:1;
 624                 uint64_t bad_term:1;
 625                 uint64_t unsop:1;
 626                 uint64_t uneop:1;
 627                 uint64_t undat:1;
 628                 uint64_t hg2fld:1;
 629                 uint64_t hg2cc:1;
 630                 uint64_t reserved_29_63:35;
 631         } cn52xx;
 632         struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
 633                 uint64_t reserved_0_0:1;
 634                 uint64_t carext:1;
 635                 uint64_t reserved_2_2:1;
 636                 uint64_t jabber:1;
 637                 uint64_t fcserr:1;
 638                 uint64_t reserved_5_6:2;
 639                 uint64_t rcverr:1;
 640                 uint64_t skperr:1;
 641                 uint64_t reserved_9_9:1;
 642                 uint64_t ovrerr:1;
 643                 uint64_t pcterr:1;
 644                 uint64_t rsverr:1;
 645                 uint64_t falerr:1;
 646                 uint64_t coldet:1;
 647                 uint64_t ifgerr:1;
 648                 uint64_t reserved_16_18:3;
 649                 uint64_t pause_drp:1;
 650                 uint64_t loc_fault:1;
 651                 uint64_t rem_fault:1;
 652                 uint64_t bad_seq:1;
 653                 uint64_t bad_term:1;
 654                 uint64_t unsop:1;
 655                 uint64_t uneop:1;
 656                 uint64_t undat:1;
 657                 uint64_t reserved_27_63:37;
 658         } cn56xxp1;
 659         struct cvmx_gmxx_rxx_int_reg_cn58xx {
 660                 uint64_t minerr:1;
 661                 uint64_t carext:1;
 662                 uint64_t maxerr:1;
 663                 uint64_t jabber:1;
 664                 uint64_t fcserr:1;
 665                 uint64_t alnerr:1;
 666                 uint64_t lenerr:1;
 667                 uint64_t rcverr:1;
 668                 uint64_t skperr:1;
 669                 uint64_t niberr:1;
 670                 uint64_t ovrerr:1;
 671                 uint64_t pcterr:1;
 672                 uint64_t rsverr:1;
 673                 uint64_t falerr:1;
 674                 uint64_t coldet:1;
 675                 uint64_t ifgerr:1;
 676                 uint64_t phy_link:1;
 677                 uint64_t phy_spd:1;
 678                 uint64_t phy_dupx:1;
 679                 uint64_t pause_drp:1;
 680                 uint64_t reserved_20_63:44;
 681         } cn58xx;
 682         struct cvmx_gmxx_rxx_int_reg_cn61xx {
 683                 uint64_t minerr:1;
 684                 uint64_t carext:1;
 685                 uint64_t reserved_2_2:1;
 686                 uint64_t jabber:1;
 687                 uint64_t fcserr:1;
 688                 uint64_t reserved_5_6:2;
 689                 uint64_t rcverr:1;
 690                 uint64_t skperr:1;
 691                 uint64_t reserved_9_9:1;
 692                 uint64_t ovrerr:1;
 693                 uint64_t pcterr:1;
 694                 uint64_t rsverr:1;
 695                 uint64_t falerr:1;
 696                 uint64_t coldet:1;
 697                 uint64_t ifgerr:1;
 698                 uint64_t reserved_16_18:3;
 699                 uint64_t pause_drp:1;
 700                 uint64_t loc_fault:1;
 701                 uint64_t rem_fault:1;
 702                 uint64_t bad_seq:1;
 703                 uint64_t bad_term:1;
 704                 uint64_t unsop:1;
 705                 uint64_t uneop:1;
 706                 uint64_t undat:1;
 707                 uint64_t hg2fld:1;
 708                 uint64_t hg2cc:1;
 709                 uint64_t reserved_29_63:35;
 710         } cn61xx;
 711 };
 712
 713 union cvmx_gmxx_prtx_cfg {
 714         uint64_t u64;
 715         struct cvmx_gmxx_prtx_cfg_s {
 716                 uint64_t reserved_22_63:42;
 717                 uint64_t pknd:6;
 718                 uint64_t reserved_14_15:2;
 719                 uint64_t tx_idle:1;
 720                 uint64_t rx_idle:1;
 721                 uint64_t reserved_9_11:3;
 722                 uint64_t speed_msb:1;
 723                 uint64_t reserved_4_7:4;
 724                 uint64_t slottime:1;
 725                 uint64_t duplex:1;
 726                 uint64_t speed:1;
 727                 uint64_t en:1;
 728         } s;
 729         struct cvmx_gmxx_prtx_cfg_cn30xx {
 730                 uint64_t reserved_4_63:60;
 731                 uint64_t slottime:1;
 732                 uint64_t duplex:1;
 733                 uint64_t speed:1;
 734                 uint64_t en:1;
 735         } cn30xx;
 736         struct cvmx_gmxx_prtx_cfg_cn52xx {
 737                 uint64_t reserved_14_63:50;
 738                 uint64_t tx_idle:1;
 739                 uint64_t rx_idle:1;
 740                 uint64_t reserved_9_11:3;
 741                 uint64_t speed_msb:1;
 742                 uint64_t reserved_4_7:4;
 743                 uint64_t slottime:1;
 744                 uint64_t duplex:1;
 745                 uint64_t speed:1;
 746                 uint64_t en:1;
 747         } cn52xx;
 748 };
 749
 750 union cvmx_gmxx_rxx_adr_ctl {
 751         uint64_t u64;
 752         struct cvmx_gmxx_rxx_adr_ctl_s {
 753                 uint64_t reserved_4_63:60;
 754                 uint64_t cam_mode:1;
 755                 uint64_t mcst:2;
 756                 uint64_t bcst:1;
 757         } s;
 758 };
 759
 760 union cvmx_pip_prt_tagx {
 761         uint64_t u64;
 762         struct cvmx_pip_prt_tagx_s {
 763                 uint64_t reserved_54_63:10;
 764                 uint64_t portadd_en:1;
 765                 uint64_t inc_hwchk:1;
 766                 uint64_t reserved_50_51:2;
 767                 uint64_t grptagbase_msb:2;
 768                 uint64_t reserved_46_47:2;
 769                 uint64_t grptagmask_msb:2;
 770                 uint64_t reserved_42_43:2;
 771                 uint64_t grp_msb:2;
 772                 uint64_t grptagbase:4;
 773                 uint64_t grptagmask:4;
 774                 uint64_t grptag:1;
 775                 uint64_t grptag_mskip:1;
 776                 uint64_t tag_mode:2;
 777                 uint64_t inc_vs:2;
 778                 uint64_t inc_vlan:1;
 779                 uint64_t inc_prt_flag:1;
 780                 uint64_t ip6_dprt_flag:1;
 781                 uint64_t ip4_dprt_flag:1;
 782                 uint64_t ip6_sprt_flag:1;
 783                 uint64_t ip4_sprt_flag:1;
 784                 uint64_t ip6_nxth_flag:1;
 785                 uint64_t ip4_pctl_flag:1;
 786                 uint64_t ip6_dst_flag:1;
 787                 uint64_t ip4_dst_flag:1;
 788                 uint64_t ip6_src_flag:1;
 789                 uint64_t ip4_src_flag:1;
 790                 uint64_t tcp6_tag_type:2;
 791                 uint64_t tcp4_tag_type:2;
 792                 uint64_t ip6_tag_type:2;
 793                 uint64_t ip4_tag_type:2;
 794                 uint64_t non_tag_type:2;
 795                 uint64_t grp:4;
 796         } s;
 797         struct cvmx_pip_prt_tagx_cn30xx {
 798                 uint64_t reserved_40_63:24;
 799                 uint64_t grptagbase:4;
 800                 uint64_t grptagmask:4;
 801                 uint64_t grptag:1;
 802                 uint64_t reserved_30_30:1;
 803                 uint64_t tag_mode:2;
 804                 uint64_t inc_vs:2;
 805                 uint64_t inc_vlan:1;
 806                 uint64_t inc_prt_flag:1;
 807                 uint64_t ip6_dprt_flag:1;
 808                 uint64_t ip4_dprt_flag:1;
 809                 uint64_t ip6_sprt_flag:1;
 810                 uint64_t ip4_sprt_flag:1;
 811                 uint64_t ip6_nxth_flag:1;
 812                 uint64_t ip4_pctl_flag:1;
 813                 uint64_t ip6_dst_flag:1;
 814                 uint64_t ip4_dst_flag:1;
 815                 uint64_t ip6_src_flag:1;
 816                 uint64_t ip4_src_flag:1;
 817                 uint64_t tcp6_tag_type:2;
 818                 uint64_t tcp4_tag_type:2;
 819                 uint64_t ip6_tag_type:2;
 820                 uint64_t ip4_tag_type:2;
 821                 uint64_t non_tag_type:2;
 822                 uint64_t grp:4;
 823         } cn30xx;
 824         struct cvmx_pip_prt_tagx_cn50xx {
 825                 uint64_t reserved_40_63:24;
 826                 uint64_t grptagbase:4;
 827                 uint64_t grptagmask:4;
 828                 uint64_t grptag:1;
 829                 uint64_t grptag_mskip:1;
 830                 uint64_t tag_mode:2;
 831                 uint64_t inc_vs:2;
 832                 uint64_t inc_vlan:1;
 833                 uint64_t inc_prt_flag:1;
 834                 uint64_t ip6_dprt_flag:1;
 835                 uint64_t ip4_dprt_flag:1;
 836                 uint64_t ip6_sprt_flag:1;
 837                 uint64_t ip4_sprt_flag:1;
 838                 uint64_t ip6_nxth_flag:1;
 839                 uint64_t ip4_pctl_flag:1;
 840                 uint64_t ip6_dst_flag:1;
 841                 uint64_t ip4_dst_flag:1;
 842                 uint64_t ip6_src_flag:1;
 843                 uint64_t ip4_src_flag:1;
 844                 uint64_t tcp6_tag_type:2;
 845                 uint64_t tcp4_tag_type:2;
 846                 uint64_t ip6_tag_type:2;
 847                 uint64_t ip4_tag_type:2;
 848                 uint64_t non_tag_type:2;
 849                 uint64_t grp:4;
 850         } cn50xx;
 851 };
 852
 853 union cvmx_spxx_int_reg {
 854         uint64_t u64;
 855         struct cvmx_spxx_int_reg_s {
 856                 uint64_t reserved_32_63:32;
 857                 uint64_t spf:1;
 858                 uint64_t reserved_12_30:19;
 859                 uint64_t calerr:1;
 860                 uint64_t syncerr:1;
 861                 uint64_t diperr:1;
 862                 uint64_t tpaovr:1;
 863                 uint64_t rsverr:1;
 864                 uint64_t drwnng:1;
 865                 uint64_t clserr:1;
 866                 uint64_t spiovr:1;
 867                 uint64_t reserved_2_3:2;
 868                 uint64_t abnorm:1;
 869                 uint64_t prtnxa:1;
 870         } s;
 871 };
 872
 873 union cvmx_spxx_int_msk {
 874         uint64_t u64;
 875         struct cvmx_spxx_int_msk_s {
 876                 uint64_t reserved_12_63:52;
 877                 uint64_t calerr:1;
 878                 uint64_t syncerr:1;
 879                 uint64_t diperr:1;
 880                 uint64_t tpaovr:1;
 881                 uint64_t rsverr:1;
 882                 uint64_t drwnng:1;
 883                 uint64_t clserr:1;
 884                 uint64_t spiovr:1;
 885                 uint64_t reserved_2_3:2;
 886                 uint64_t abnorm:1;
 887                 uint64_t prtnxa:1;
 888         } s;
 889 };
 890
 891 union cvmx_pow_wq_int {
 892         uint64_t u64;
 893         struct cvmx_pow_wq_int_s {
 894                 uint64_t wq_int:16;
 895                 uint64_t iq_dis:16;
 896                 uint64_t reserved_32_63:32;
 897         } s;
 898 };
 899
 900 union cvmx_sso_wq_int_thrx {
 901         uint64_t u64;
 902         struct {
 903                 uint64_t iq_thr:12;
 904                 uint64_t reserved_12_13:2;
 905                 uint64_t ds_thr:12;
 906                 uint64_t reserved_26_27:2;
 907                 uint64_t tc_thr:4;
 908                 uint64_t tc_en:1;
 909                 uint64_t reserved_33_63:31;
 910         } s;
 911 };
 912
 913 union cvmx_stxx_int_reg {
 914         uint64_t u64;
 915         struct cvmx_stxx_int_reg_s {
 916                 uint64_t reserved_9_63:55;
 917                 uint64_t syncerr:1;
 918                 uint64_t frmerr:1;
 919                 uint64_t unxfrm:1;
 920                 uint64_t nosync:1;
 921                 uint64_t diperr:1;
 922                 uint64_t datovr:1;
 923                 uint64_t ovrbst:1;
 924                 uint64_t calpar1:1;
 925                 uint64_t calpar0:1;
 926         } s;
 927 };
 928
 929 union cvmx_stxx_int_msk {
 930         uint64_t u64;
 931         struct cvmx_stxx_int_msk_s {
 932                 uint64_t reserved_8_63:56;
 933                 uint64_t frmerr:1;
 934                 uint64_t unxfrm:1;
 935                 uint64_t nosync:1;
 936                 uint64_t diperr:1;
 937                 uint64_t datovr:1;
 938                 uint64_t ovrbst:1;
 939                 uint64_t calpar1:1;
 940                 uint64_t calpar0:1;
 941         } s;
 942 };
 943
 944 union cvmx_pow_wq_int_pc {
 945         uint64_t u64;
 946         struct cvmx_pow_wq_int_pc_s {
 947                 uint64_t reserved_0_7:8;
 948                 uint64_t pc_thr:20;
 949                 uint64_t reserved_28_31:4;
 950                 uint64_t pc:28;
 951                 uint64_t reserved_60_63:4;
 952         } s;
 953 };
 954
 955 union cvmx_pow_wq_int_thrx {
 956         uint64_t u64;
 957         struct cvmx_pow_wq_int_thrx_s {
 958                 uint64_t reserved_29_63:35;
 959                 uint64_t tc_en:1;
 960                 uint64_t tc_thr:4;
 961                 uint64_t reserved_23_23:1;
 962                 uint64_t ds_thr:11;
 963                 uint64_t reserved_11_11:1;
 964                 uint64_t iq_thr:11;
 965         } s;
 966         struct cvmx_pow_wq_int_thrx_cn30xx {
 967                 uint64_t reserved_29_63:35;
 968                 uint64_t tc_en:1;
 969                 uint64_t tc_thr:4;
 970                 uint64_t reserved_18_23:6;
 971                 uint64_t ds_thr:6;
 972                 uint64_t reserved_6_11:6;
 973                 uint64_t iq_thr:6;
 974         } cn30xx;
 975         struct cvmx_pow_wq_int_thrx_cn31xx {
 976                 uint64_t reserved_29_63:35;
 977                 uint64_t tc_en:1;
 978                 uint64_t tc_thr:4;
 979                 uint64_t reserved_20_23:4;
 980                 uint64_t ds_thr:8;
 981                 uint64_t reserved_8_11:4;
 982                 uint64_t iq_thr:8;
 983         } cn31xx;
 984         struct cvmx_pow_wq_int_thrx_cn52xx {
 985                 uint64_t reserved_29_63:35;
 986                 uint64_t tc_en:1;
 987                 uint64_t tc_thr:4;
 988                 uint64_t reserved_21_23:3;
 989                 uint64_t ds_thr:9;
 990                 uint64_t reserved_9_11:3;
 991                 uint64_t iq_thr:9;
 992         } cn52xx;
 993         struct cvmx_pow_wq_int_thrx_cn63xx {
 994                 uint64_t reserved_29_63:35;
 995                 uint64_t tc_en:1;
 996                 uint64_t tc_thr:4;
 997                 uint64_t reserved_22_23:2;
 998                 uint64_t ds_thr:10;
 999                 uint64_t reserved_10_11:2;
1000                 uint64_t iq_thr:10;
1001         } cn63xx;
1002 };
1003
1004 union cvmx_npi_rsl_int_blocks {
1005         uint64_t u64;
1006         struct cvmx_npi_rsl_int_blocks_s {
1007                 uint64_t reserved_32_63:32;
1008                 uint64_t rint_31:1;
1009                 uint64_t iob:1;
1010                 uint64_t reserved_28_29:2;
1011                 uint64_t rint_27:1;
1012                 uint64_t rint_26:1;
1013                 uint64_t rint_25:1;
1014                 uint64_t rint_24:1;
1015                 uint64_t asx1:1;
1016                 uint64_t asx0:1;
1017                 uint64_t rint_21:1;
1018                 uint64_t pip:1;
1019                 uint64_t spx1:1;
1020                 uint64_t spx0:1;
1021                 uint64_t lmc:1;
1022                 uint64_t l2c:1;
1023                 uint64_t rint_15:1;
1024                 uint64_t reserved_13_14:2;
1025                 uint64_t pow:1;
1026                 uint64_t tim:1;
1027                 uint64_t pko:1;
1028                 uint64_t ipd:1;
1029                 uint64_t rint_8:1;
1030                 uint64_t zip:1;
1031                 uint64_t dfa:1;
1032                 uint64_t fpa:1;
1033                 uint64_t key:1;
1034                 uint64_t npi:1;
1035                 uint64_t gmx1:1;
1036                 uint64_t gmx0:1;
1037                 uint64_t mio:1;
1038         } s;
1039         struct cvmx_npi_rsl_int_blocks_cn30xx {
1040                 uint64_t reserved_32_63:32;
1041                 uint64_t rint_31:1;
1042                 uint64_t iob:1;
1043                 uint64_t rint_29:1;
1044                 uint64_t rint_28:1;
1045                 uint64_t rint_27:1;
1046                 uint64_t rint_26:1;
1047                 uint64_t rint_25:1;
1048                 uint64_t rint_24:1;
1049                 uint64_t asx1:1;
1050                 uint64_t asx0:1;
1051                 uint64_t rint_21:1;
1052                 uint64_t pip:1;
1053                 uint64_t spx1:1;
1054                 uint64_t spx0:1;
1055                 uint64_t lmc:1;
1056                 uint64_t l2c:1;
1057                 uint64_t rint_15:1;
1058                 uint64_t rint_14:1;
1059                 uint64_t usb:1;
1060                 uint64_t pow:1;
1061                 uint64_t tim:1;
1062                 uint64_t pko:1;
1063                 uint64_t ipd:1;
1064                 uint64_t rint_8:1;
1065                 uint64_t zip:1;
1066                 uint64_t dfa:1;
1067                 uint64_t fpa:1;
1068                 uint64_t key:1;
1069                 uint64_t npi:1;
1070                 uint64_t gmx1:1;
1071                 uint64_t gmx0:1;
1072                 uint64_t mio:1;
1073         } cn30xx;
1074         struct cvmx_npi_rsl_int_blocks_cn38xx {
1075                 uint64_t reserved_32_63:32;
1076                 uint64_t rint_31:1;
1077                 uint64_t iob:1;
1078                 uint64_t rint_29:1;
1079                 uint64_t rint_28:1;
1080                 uint64_t rint_27:1;
1081                 uint64_t rint_26:1;
1082                 uint64_t rint_25:1;
1083                 uint64_t rint_24:1;
1084                 uint64_t asx1:1;
1085                 uint64_t asx0:1;
1086                 uint64_t rint_21:1;
1087                 uint64_t pip:1;
1088                 uint64_t spx1:1;
1089                 uint64_t spx0:1;
1090                 uint64_t lmc:1;
1091                 uint64_t l2c:1;
1092                 uint64_t rint_15:1;
1093                 uint64_t rint_14:1;
1094                 uint64_t rint_13:1;
1095                 uint64_t pow:1;
1096                 uint64_t tim:1;
1097                 uint64_t pko:1;
1098                 uint64_t ipd:1;
1099                 uint64_t rint_8:1;
1100                 uint64_t zip:1;
1101                 uint64_t dfa:1;
1102                 uint64_t fpa:1;
1103                 uint64_t key:1;
1104                 uint64_t npi:1;
1105                 uint64_t gmx1:1;
1106                 uint64_t gmx0:1;
1107                 uint64_t mio:1;
1108         } cn38xx;
1109         struct cvmx_npi_rsl_int_blocks_cn50xx {
1110                 uint64_t reserved_31_63:33;
1111                 uint64_t iob:1;
1112                 uint64_t lmc1:1;
1113                 uint64_t agl:1;
1114                 uint64_t reserved_24_27:4;
1115                 uint64_t asx1:1;
1116                 uint64_t asx0:1;
1117                 uint64_t reserved_21_21:1;
1118                 uint64_t pip:1;
1119                 uint64_t spx1:1;
1120                 uint64_t spx0:1;
1121                 uint64_t lmc:1;
1122                 uint64_t l2c:1;
1123                 uint64_t reserved_15_15:1;
1124                 uint64_t rad:1;
1125                 uint64_t usb:1;
1126                 uint64_t pow:1;
1127                 uint64_t tim:1;
1128                 uint64_t pko:1;
1129                 uint64_t ipd:1;
1130                 uint64_t reserved_8_8:1;
1131                 uint64_t zip:1;
1132                 uint64_t dfa:1;
1133                 uint64_t fpa:1;
1134                 uint64_t key:1;
1135                 uint64_t npi:1;
1136                 uint64_t gmx1:1;
1137                 uint64_t gmx0:1;
1138                 uint64_t mio:1;
1139         } cn50xx;
1140 };
1141
1142 union cvmx_pko_command_word0 {
1143         uint64_t u64;
1144         struct {
1145                 uint64_t total_bytes:16;
1146                 uint64_t segs:6;
1147                 uint64_t dontfree:1;
1148                 uint64_t ignore_i:1;
1149                 uint64_t ipoffp1:7;
1150                 uint64_t gather:1;
1151                 uint64_t rsp:1;
1152                 uint64_t wqp:1;
1153                 uint64_t n2:1;
1154                 uint64_t le:1;
1155                 uint64_t reg0:11;
1156                 uint64_t subone0:1;
1157                 uint64_t reg1:11;
1158                 uint64_t subone1:1;
1159                 uint64_t size0:2;
1160                 uint64_t size1:2;
1161         } s;
1162 };
1163
1164 union cvmx_ciu_timx {
1165         uint64_t u64;
1166         struct cvmx_ciu_timx_s {
1167                 uint64_t reserved_37_63:27;
1168                 uint64_t one_shot:1;
1169                 uint64_t len:36;
1170         } s;
1171 };
1172
1173 union cvmx_gmxx_rxx_rx_inbnd {
1174         uint64_t u64;
1175         struct cvmx_gmxx_rxx_rx_inbnd_s {
1176                 uint64_t status:1;
1177                 uint64_t speed:2;
1178                 uint64_t duplex:1;
1179                 uint64_t reserved_4_63:60;
1180         } s;
1181 };
1182
1183 static inline int32_t cvmx_fau_fetch_and_add32(enum cvmx_fau_reg_32 reg,
1184                                                int32_t value)
1185 {
1186         return value;
1187 }
1188
1189 static inline void cvmx_fau_atomic_add32(enum cvmx_fau_reg_32 reg,
1190                                          int32_t value)
1191 { }
1192
1193 static inline void cvmx_fau_atomic_write32(enum cvmx_fau_reg_32 reg,
1194                                            int32_t value)
1195 { }
1196
1197 static inline uint64_t cvmx_scratch_read64(uint64_t address)
1198 {
1199         return 0;
1200 }
1201
1202 static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
1203 { }
1204
1205 static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work)
1206 {
1207         return 0;
1208 }
1209
1210 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
1211 {
1212         return (void *)(uintptr_t)(physical_address);
1213 }
1214
1215 static inline uint64_t cvmx_ptr_to_phys(void *ptr)
1216 {
1217         return (unsigned long)ptr;
1218 }
1219
1220 static inline int cvmx_helper_get_interface_num(int ipd_port)
1221 {
1222         return ipd_port;
1223 }
1224
1225 static inline int cvmx_helper_get_interface_index_num(int ipd_port)
1226 {
1227         return ipd_port;
1228 }
1229
1230 static inline void cvmx_fpa_enable(void)
1231 { }
1232
1233 static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
1234 {
1235         return 0;
1236 }
1237
1238 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
1239 { }
1240
1241 static inline int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1242 {
1243         return 0;
1244 }
1245
1246 static inline void *cvmx_fpa_alloc(uint64_t pool)
1247 {
1248         return NULL;
1249 }
1250
1251 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
1252                                  uint64_t num_cache_lines)
1253 { }
1254
1255 static inline int octeon_is_simulation(void)
1256 {
1257         return 1;
1258 }
1259
1260 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
1261                                             cvmx_pip_port_status_t *status)
1262 { }
1263
1264 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
1265                                             cvmx_pko_port_status_t *status)
1266 { }
1267
1268 static inline cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
1269                                                                    interface)
1270 {
1271         return 0;
1272 }
1273
1274 static inline union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port)
1275 {
1276         union cvmx_helper_link_info ret = { .u64 = 0 };
1277
1278         return ret;
1279 }
1280
1281 static inline int cvmx_helper_link_set(int ipd_port,
1282                                        union cvmx_helper_link_info link_info)
1283 {
1284         return 0;
1285 }
1286
1287 static inline int cvmx_helper_initialize_packet_io_global(void)
1288 {
1289         return 0;
1290 }
1291
1292 static inline int cvmx_helper_get_number_of_interfaces(void)
1293 {
1294         return 2;
1295 }
1296
1297 static inline int cvmx_helper_ports_on_interface(int interface)
1298 {
1299         return 1;
1300 }
1301
1302 static inline int cvmx_helper_get_ipd_port(int interface, int port)
1303 {
1304         return 0;
1305 }
1306
1307 static inline int cvmx_helper_ipd_and_packet_input_enable(void)
1308 {
1309         return 0;
1310 }
1311
1312 static inline void cvmx_ipd_disable(void)
1313 { }
1314
1315 static inline void cvmx_ipd_free_ptr(void)
1316 { }
1317
1318 static inline void cvmx_pko_disable(void)
1319 { }
1320
1321 static inline void cvmx_pko_shutdown(void)
1322 { }
1323
1324 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
1325 {
1326         return port;
1327 }
1328
1329 static inline int cvmx_pko_get_base_queue(int port)
1330 {
1331         return port;
1332 }
1333
1334 static inline int cvmx_pko_get_num_queues(int port)
1335 {
1336         return port;
1337 }
1338
1339 static inline unsigned int cvmx_get_core_num(void)
1340 {
1341         return 0;
1342 }
1343
1344 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1345                                                        cvmx_pow_wait_t wait)
1346 { }
1347
1348 static inline void cvmx_pow_work_request_async(int scr_addr,
1349                                                cvmx_pow_wait_t wait)
1350 { }
1351
1352 static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
1353 {
1354         struct cvmx_wqe *wqe = (void *)(unsigned long)scr_addr;
1355
1356         return wqe;
1357 }
1358
1359 static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1360 {
1361         return (void *)(unsigned long)wait;
1362 }
1363
1364 static inline int cvmx_spi_restart_interface(int interface,
1365                                         cvmx_spi_mode_t mode, int timeout)
1366 {
1367         return 0;
1368 }
1369
1370 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
1371                                                   enum cvmx_fau_reg_32 reg,
1372                                                   int32_t value)
1373 { }
1374
1375 static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
1376         int interface,
1377         int port)
1378 {
1379         union cvmx_gmxx_rxx_rx_inbnd r;
1380
1381         r.u64 = 0;
1382         return r;
1383 }
1384
1385 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
1386                                                 cvmx_pko_lock_t use_locking)
1387 { }
1388
1389 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port,
1390                 uint64_t queue, union cvmx_pko_command_word0 pko_command,
1391                 union cvmx_buf_ptr packet, cvmx_pko_lock_t use_locking)
1392 {
1393         return 0;
1394 }
1395
1396 static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port)
1397 { }
1398
1399 static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos)
1400 { }
1401
1402 static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work)
1403 {
1404         return 0;
1405 }
1406
1407 static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp)
1408 { }
1409
1410 static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, uint32_t tag,
1411                                         enum cvmx_pow_tag_type tag_type,
1412                                         uint64_t qos, uint64_t grp)
1413 { }
1414
1415 #define CVMX_ASXX_RX_CLK_SETX(a, b)     ((a) + (b))
1416 #define CVMX_ASXX_TX_CLK_SETX(a, b)     ((a) + (b))
1417 #define CVMX_CIU_TIMX(a)                (a)
1418 #define CVMX_GMXX_RXX_ADR_CAM0(a, b)    ((a) + (b))
1419 #define CVMX_GMXX_RXX_ADR_CAM1(a, b)    ((a) + (b))
1420 #define CVMX_GMXX_RXX_ADR_CAM2(a, b)    ((a) + (b))
1421 #define CVMX_GMXX_RXX_ADR_CAM3(a, b)    ((a) + (b))
1422 #define CVMX_GMXX_RXX_ADR_CAM4(a, b)    ((a) + (b))
1423 #define CVMX_GMXX_RXX_ADR_CAM5(a, b)    ((a) + (b))
1424 #define CVMX_GMXX_RXX_FRM_CTL(a, b)     ((a) + (b))
1425 #define CVMX_GMXX_RXX_INT_REG(a, b)     ((a) + (b))
1426 #define CVMX_GMXX_SMACX(a, b)           ((a) + (b))
1427 #define CVMX_PIP_PRT_TAGX(a)            (a)
1428 #define CVMX_POW_PP_GRP_MSKX(a)         (a)
1429 #define CVMX_POW_WQ_INT_THRX(a)         (a)
1430 #define CVMX_SPXX_INT_MSK(a)            (a)
1431 #define CVMX_SPXX_INT_REG(a)            (a)
1432 #define CVMX_SSO_PPX_GRP_MSK(a)         (a)
1433 #define CVMX_SSO_WQ_INT_THRX(a)         (a)
1434 #define CVMX_STXX_INT_MSK(a)            (a)
1435 #define CVMX_STXX_INT_REG(a)            (a)