drivers/staging/netlogic/xlr_net.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2003-2012 Broadcom Corporation
   4  * All Rights Reserved
   5  */
   6
   7 #include <linux/phy.h>
   8 #include <linux/delay.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/smp.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/module.h>
  13 #include <linux/etherdevice.h>
  14 #include <linux/skbuff.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <asm/mipsregs.h>
  20 /*
  21  * fmn.h - For FMN credit configuration and registering fmn_handler.
  22  * FMN is communication mechanism that allows processing agents within
  23  * XLR/XLS to communicate each other.
  24  */
  25 #include <asm/netlogic/xlr/fmn.h>
  26
  27 #include "platform_net.h"
  28 #include "xlr_net.h"
  29
  30 /*
  31  * The readl/writel implementation byteswaps on XLR/XLS, so
  32  * we need to use __raw_ IO to read the NAE registers
  33  * because they are in the big-endian MMIO area on the SoC.
  34  */
  35 static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
  36 {
  37         __raw_writel(val, base + reg);
  38 }
  39
  40 static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
  41 {
  42         return __raw_readl(base + reg);
  43 }
  44
  45 static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
  46 {
  47         u32 tmp;
  48
  49         tmp = xlr_nae_rdreg(base_addr, off);
  50         xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
  51 }
  52
  53 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
  54
  55 static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
  56 {
  57         struct nlm_fmn_msg msg;
  58         int ret = 0, num_try = 0, stnid;
  59         unsigned long paddr, mflags;
  60
  61         paddr = virt_to_bus(addr);
  62         msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
  63         msg.msg1 = 0;
  64         msg.msg2 = 0;
  65         msg.msg3 = 0;
  66         stnid = priv->nd->rfr_station;
  67         do {
  68                 mflags = nlm_cop2_enable_irqsave();
  69                 ret = nlm_fmn_send(1, 0, stnid, &msg);
  70                 nlm_cop2_disable_irqrestore(mflags);
  71                 if (ret == 0)
  72                         return 0;
  73         } while (++num_try < 10000);
  74
  75         netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
  76         return ret;
  77 }
  78
  79 static inline unsigned char *xlr_alloc_skb(void)
  80 {
  81         struct sk_buff *skb;
  82         int buf_len = sizeof(struct sk_buff *);
  83         unsigned char *skb_data;
  84
  85         /* skb->data is cache aligned */
  86         skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
  87         if (!skb)
  88                 return NULL;
  89         skb_data = skb->data;
  90         skb_reserve(skb, MAC_SKB_BACK_PTR_SIZE);
  91         memcpy(skb_data, &skb, buf_len);
  92
  93         return skb->data;
  94 }
  95
  96 static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
  97                                 struct nlm_fmn_msg *msg, void *arg)
  98 {
  99         struct sk_buff *skb;
 100         void *skb_data = NULL;
 101         struct net_device *ndev;
 102         struct xlr_net_priv *priv;
 103         u32 port, length;
 104         unsigned char *addr;
 105         struct xlr_adapter *adapter = arg;
 106
 107         length = (msg->msg0 >> 40) & 0x3fff;
 108         if (length == 0) {
 109                 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
 110                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
 111                 skb = (struct sk_buff *)(*(unsigned long *)addr);
 112                 dev_kfree_skb_any((struct sk_buff *)addr);
 113         } else {
 114                 addr = (unsigned char *)
 115                         bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
 116                 length = length - BYTE_OFFSET - MAC_CRC_LEN;
 117                 port = ((int)msg->msg0) & 0x0f;
 118                 addr = addr - MAC_SKB_BACK_PTR_SIZE;
 119                 skb = (struct sk_buff *)(*(unsigned long *)addr);
 120                 skb->dev = adapter->netdev[port];
 121                 if (!skb->dev)
 122                         return;
 123                 ndev = skb->dev;
 124                 priv = netdev_priv(ndev);
 125
 126                 /* 16 byte IP header align */
 127                 skb_reserve(skb, BYTE_OFFSET);
 128                 skb_put(skb, length);
 129                 skb->protocol = eth_type_trans(skb, skb->dev);
 130                 netif_rx(skb);
 131                 /* Fill rx ring */
 132                 skb_data = xlr_alloc_skb();
 133                 if (skb_data)
 134                         send_to_rfr_fifo(priv, skb_data);
 135         }
 136 }
 137
 138 static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
 139 {
 140         return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
 141 }
 142
 143 /*
 144  * Ethtool operation
 145  */
 146 static int xlr_get_link_ksettings(struct net_device *ndev,
 147                                   struct ethtool_link_ksettings *ecmd)
 148 {
 149         struct xlr_net_priv *priv = netdev_priv(ndev);
 150         struct phy_device *phydev = xlr_get_phydev(priv);
 151
 152         if (!phydev)
 153                 return -ENODEV;
 154
 155         phy_ethtool_ksettings_get(phydev, ecmd);
 156
 157         return 0;
 158 }
 159
 160 static int xlr_set_link_ksettings(struct net_device *ndev,
 161                                   const struct ethtool_link_ksettings *ecmd)
 162 {
 163         struct xlr_net_priv *priv = netdev_priv(ndev);
 164         struct phy_device *phydev = xlr_get_phydev(priv);
 165
 166         if (!phydev)
 167                 return -ENODEV;
 168         return phy_ethtool_ksettings_set(phydev, ecmd);
 169 }
 170
 171 static const struct ethtool_ops xlr_ethtool_ops = {
 172         .get_link_ksettings = xlr_get_link_ksettings,
 173         .set_link_ksettings = xlr_set_link_ksettings,
 174 };
 175
 176 /*
 177  * Net operations
 178  */
 179 static int xlr_net_fill_rx_ring(struct net_device *ndev)
 180 {
 181         void *skb_data;
 182         struct xlr_net_priv *priv = netdev_priv(ndev);
 183         int i;
 184
 185         for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
 186                 skb_data = xlr_alloc_skb();
 187                 if (!skb_data)
 188                         return -ENOMEM;
 189                 send_to_rfr_fifo(priv, skb_data);
 190         }
 191         netdev_info(ndev, "Rx ring setup done\n");
 192         return 0;
 193 }
 194
 195 static int xlr_net_open(struct net_device *ndev)
 196 {
 197         u32 err;
 198         struct xlr_net_priv *priv = netdev_priv(ndev);
 199         struct phy_device *phydev = xlr_get_phydev(priv);
 200
 201         /* schedule a link state check */
 202         phy_start(phydev);
 203
 204         err = phy_start_aneg(phydev);
 205         if (err) {
 206                 pr_err("Autoneg failed\n");
 207                 return err;
 208         }
 209         /* Setup the speed from PHY to internal reg*/
 210         xlr_set_gmac_speed(priv);
 211
 212         netif_tx_start_all_queues(ndev);
 213
 214         return 0;
 215 }
 216
 217 static int xlr_net_stop(struct net_device *ndev)
 218 {
 219         struct xlr_net_priv *priv = netdev_priv(ndev);
 220         struct phy_device *phydev = xlr_get_phydev(priv);
 221
 222         phy_stop(phydev);
 223         netif_tx_stop_all_queues(ndev);
 224         return 0;
 225 }
 226
 227 static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
 228                              struct sk_buff *skb)
 229 {
 230         unsigned long physkb = virt_to_phys(skb);
 231         int cpu_core = nlm_core_id();
 232         int fr_stn_id = cpu_core * 8 + XLR_FB_STN;      /* FB to 6th bucket */
 233
 234         msg->msg0 = (((u64)1 << 63)     |       /* End of packet descriptor */
 235                 ((u64)127 << 54)        |       /* No Free back */
 236                 (u64)skb->len << 40     |       /* Length of data */
 237                 ((u64)addr));
 238         msg->msg1 = (((u64)1 << 63)     |
 239                 ((u64)fr_stn_id << 54)  |       /* Free back id */
 240                 (u64)0 << 40            |       /* Set len to 0 */
 241                 ((u64)physkb  & 0xffffffff));   /* 32bit address */
 242         msg->msg2 = 0;
 243         msg->msg3 = 0;
 244 }
 245
 246 static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
 247                                       struct net_device *ndev)
 248 {
 249         struct nlm_fmn_msg msg;
 250         struct xlr_net_priv *priv = netdev_priv(ndev);
 251         int ret;
 252         u32 flags;
 253
 254         xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
 255         flags = nlm_cop2_enable_irqsave();
 256         ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
 257         nlm_cop2_disable_irqrestore(flags);
 258         if (ret)
 259                 dev_kfree_skb_any(skb);
 260         return NETDEV_TX_OK;
 261 }
 262
 263 static void xlr_hw_set_mac_addr(struct net_device *ndev)
 264 {
 265         struct xlr_net_priv *priv = netdev_priv(ndev);
 266
 267         /* set mac station address */
 268         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
 269                      ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
 270                      (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
 271         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
 272                      ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
 273
 274         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
 275         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
 276         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
 277         xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
 278
 279         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
 280                      (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
 281                      (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
 282                      (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
 283
 284         if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
 285             priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
 286                 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
 287 }
 288
 289 static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
 290 {
 291         int err;
 292
 293         err = eth_mac_addr(ndev, data);
 294         if (err)
 295                 return err;
 296         xlr_hw_set_mac_addr(ndev);
 297         return 0;
 298 }
 299
 300 static void xlr_set_rx_mode(struct net_device *ndev)
 301 {
 302         struct xlr_net_priv *priv = netdev_priv(ndev);
 303         u32 regval;
 304
 305         regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
 306
 307         if (ndev->flags & IFF_PROMISC) {
 308                 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
 309                 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
 310                 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
 311                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
 312         } else {
 313                 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
 314                 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
 315         }
 316
 317         xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
 318 }
 319
 320 static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
 321 {
 322         struct xlr_net_priv *priv = netdev_priv(ndev);
 323
 324         stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
 325         stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
 326         stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
 327         stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
 328         stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
 329         stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
 330                                           RX_DROP_PACKET_COUNTER);
 331         stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
 332                                           TX_DROP_FRAME_COUNTER);
 333
 334         stats->multicast = xlr_nae_rdreg(priv->base_addr,
 335                                          RX_MULTICAST_PACKET_COUNTER);
 336         stats->collisions = xlr_nae_rdreg(priv->base_addr,
 337                                           TX_TOTAL_COLLISION_COUNTER);
 338
 339         stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
 340                                                 RX_FRAME_LENGTH_ERROR_COUNTER);
 341         stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
 342                                               RX_DROP_PACKET_COUNTER);
 343         stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
 344                                              RX_FCS_ERROR_COUNTER);
 345         stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
 346                                                RX_ALIGNMENT_ERROR_COUNTER);
 347
 348         stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
 349                                               RX_DROP_PACKET_COUNTER);
 350         stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
 351                                                 RX_CARRIER_SENSE_ERROR_COUNTER);
 352
 353         stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
 354                             stats->rx_frame_errors + stats->rx_fifo_errors +
 355                             stats->rx_missed_errors);
 356
 357         stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
 358                                                  TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
 359         stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
 360                                                  TX_DROP_FRAME_COUNTER);
 361         stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
 362                                               TX_DROP_FRAME_COUNTER);
 363 }
 364
 365 static const struct net_device_ops xlr_netdev_ops = {
 366         .ndo_open = xlr_net_open,
 367         .ndo_stop = xlr_net_stop,
 368         .ndo_start_xmit = xlr_net_start_xmit,
 369         .ndo_select_queue = dev_pick_tx_cpu_id,
 370         .ndo_set_mac_address = xlr_net_set_mac_addr,
 371         .ndo_set_rx_mode = xlr_set_rx_mode,
 372         .ndo_get_stats64 = xlr_stats,
 373 };
 374
 375 /*
 376  * Gmac init
 377  */
 378 static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
 379                               int reg_start_1, int reg_size, int size)
 380 {
 381         void *spill;
 382         u32 *base;
 383         unsigned long phys_addr;
 384         u32 spill_size;
 385
 386         base = priv->base_addr;
 387         spill_size = size;
 388         spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_KERNEL);
 389         if (!spill)
 390                 return ZERO_SIZE_PTR;
 391
 392         spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
 393         phys_addr = virt_to_phys(spill);
 394         dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
 395                 size, phys_addr);
 396         xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
 397         xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
 398         xlr_nae_wreg(base, reg_size, spill_size);
 399
 400         return spill;
 401 }
 402
 403 /*
 404  * Configure the 6 FIFO's that are used by the network accelarator to
 405  * communicate with the rest of the XLx device. 4 of the FIFO's are for
 406  * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
 407  * the NA with free descriptors.
 408  */
 409 static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
 410 {
 411         priv->frin_spill = xlr_config_spill(priv,
 412                                             R_REG_FRIN_SPILL_MEM_START_0,
 413                                             R_REG_FRIN_SPILL_MEM_START_1,
 414                                             R_REG_FRIN_SPILL_MEM_SIZE,
 415                                             MAX_FRIN_SPILL * sizeof(u64));
 416         priv->frout_spill = xlr_config_spill(priv,
 417                                              R_FROUT_SPILL_MEM_START_0,
 418                                              R_FROUT_SPILL_MEM_START_1,
 419                                              R_FROUT_SPILL_MEM_SIZE,
 420                                              MAX_FROUT_SPILL * sizeof(u64));
 421         priv->class_0_spill = xlr_config_spill(priv,
 422                                                R_CLASS0_SPILL_MEM_START_0,
 423                                                R_CLASS0_SPILL_MEM_START_1,
 424                                                R_CLASS0_SPILL_MEM_SIZE,
 425                                                MAX_CLASS_0_SPILL * sizeof(u64));
 426         priv->class_1_spill = xlr_config_spill(priv,
 427                                                R_CLASS1_SPILL_MEM_START_0,
 428                                                R_CLASS1_SPILL_MEM_START_1,
 429                                                R_CLASS1_SPILL_MEM_SIZE,
 430                                                MAX_CLASS_1_SPILL * sizeof(u64));
 431         priv->class_2_spill = xlr_config_spill(priv,
 432                                                R_CLASS2_SPILL_MEM_START_0,
 433                                                R_CLASS2_SPILL_MEM_START_1,
 434                                                R_CLASS2_SPILL_MEM_SIZE,
 435                                                MAX_CLASS_2_SPILL * sizeof(u64));
 436         priv->class_3_spill = xlr_config_spill(priv,
 437                                                R_CLASS3_SPILL_MEM_START_0,
 438                                                R_CLASS3_SPILL_MEM_START_1,
 439                                                R_CLASS3_SPILL_MEM_SIZE,
 440                                                MAX_CLASS_3_SPILL * sizeof(u64));
 441 }
 442
 443 /*
 444  * Configure PDE to Round-Robin distribution of packets to the
 445  * available cpu
 446  */
 447 static void xlr_config_pde(struct xlr_net_priv *priv)
 448 {
 449         int i = 0;
 450         u64 bkt_map = 0;
 451
 452         /* Each core has 8 buckets(station) */
 453         for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
 454                 bkt_map |= (0xff << (i * 8));
 455
 456         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
 457         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
 458                      ((bkt_map >> 32) & 0xffffffff));
 459
 460         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
 461         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
 462                      ((bkt_map >> 32) & 0xffffffff));
 463
 464         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
 465         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
 466                      ((bkt_map >> 32) & 0xffffffff));
 467
 468         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
 469         xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
 470                      ((bkt_map >> 32) & 0xffffffff));
 471 }
 472
 473 /*
 474  * Setup the Message ring credits, bucket size and other
 475  * common configuration
 476  */
 477 static int xlr_config_common(struct xlr_net_priv *priv)
 478 {
 479         struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
 480         int start_stn_id = gmac->start_stn_id;
 481         int end_stn_id = gmac->end_stn_id;
 482         int *bucket_size = priv->nd->bucket_size;
 483         int i, j, err;
 484
 485         /* Setting non-core MsgBktSize(0x321 - 0x325) */
 486         for (i = start_stn_id; i <= end_stn_id; i++) {
 487                 xlr_nae_wreg(priv->base_addr,
 488                              R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
 489                              bucket_size[i]);
 490         }
 491
 492         /*
 493          * Setting non-core Credit counter register
 494          * Distributing Gmac's credit to CPU's
 495          */
 496         for (i = 0; i < 8; i++) {
 497                 for (j = 0; j < 8; j++)
 498                         xlr_nae_wreg(priv->base_addr,
 499                                      (R_CC_CPU0_0 + (i * 8)) + j,
 500                                      gmac->credit_config[(i * 8) + j]);
 501         }
 502
 503         xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
 504         xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
 505         xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
 506         xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
 507         xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
 508         xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
 509
 510         err = xlr_net_fill_rx_ring(priv->ndev);
 511         if (err)
 512                 return err;
 513         nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
 514                                  priv->adapter);
 515         return 0;
 516 }
 517
 518 static void xlr_config_translate_table(struct xlr_net_priv *priv)
 519 {
 520         u32 cpu_mask;
 521         u32 val;
 522         int bkts[32]; /* one bucket is assumed for each cpu */
 523         int b1, b2, c1, c2, i, j, k;
 524         int use_bkt;
 525
 526         use_bkt = 0;
 527         cpu_mask = priv->nd->cpu_mask;
 528
 529         pr_info("Using %s-based distribution\n",
 530                 (use_bkt) ? "bucket" : "class");
 531         j = 0;
 532         for (i = 0; i < 32; i++) {
 533                 if ((1 << i) & cpu_mask) {
 534                         /* for each cpu, mark the 4+threadid bucket */
 535                         bkts[j] = ((i / 4) * 8) + (i % 4);
 536                         j++;
 537                 }
 538         }
 539
 540         /*configure the 128 * 9 Translation table to send to available buckets*/
 541         k = 0;
 542         c1 = 3;
 543         c2 = 0;
 544         for (i = 0; i < 64; i++) {
 545                 /*
 546                  * On use_bkt set the b0, b1 are used, else
 547                  * the 4 classes are used, here implemented
 548                  * a logic to distribute the packets to the
 549                  * buckets equally or based on the class
 550                  */
 551                 c1 = (c1 + 1) & 3;
 552                 c2 = (c1 + 1) & 3;
 553                 b1 = bkts[k];
 554                 k = (k + 1) % j;
 555                 b2 = bkts[k];
 556                 k = (k + 1) % j;
 557
 558                 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
 559                                 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
 560                 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
 561                         i, b1, b2, c1, c2);
 562                 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
 563                 c1 = c2;
 564         }
 565 }
 566
 567 static void xlr_config_parser(struct xlr_net_priv *priv)
 568 {
 569         u32 val;
 570
 571         /* Mark it as ETHERNET type */
 572         xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
 573
 574         /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
 575         xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
 576                      ((0x7f << 8) | (1 << 1)));
 577
 578         /* configure the parser : L2 Type is configured in the bootloader */
 579         /* extract IP: src, dest protocol */
 580         xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
 581                      (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
 582                      (0x0800 << 0));
 583         xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
 584                      (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
 585                      (16 << 4) | 4);
 586
 587         /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
 588         xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
 589         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
 590         val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
 591         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
 592         xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
 593
 594         xlr_config_translate_table(priv);
 595 }
 596
 597 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
 598 {
 599         unsigned long timeout, stoptime, checktime;
 600         int timedout;
 601
 602         /* 100ms timeout*/
 603         timeout = msecs_to_jiffies(100);
 604         stoptime = jiffies + timeout;
 605         timedout = 0;
 606
 607         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
 608
 609         /* Write the data which starts the write cycle */
 610         xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
 611
 612         /* poll for the read cycle to complete */
 613         while (!timedout) {
 614                 checktime = jiffies;
 615                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
 616                         break;
 617                 timedout = time_after(checktime, stoptime);
 618         }
 619         if (timedout) {
 620                 pr_info("Phy device write err: device busy");
 621                 return -EBUSY;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
 628 {
 629         unsigned long timeout, stoptime, checktime;
 630         int timedout;
 631
 632         /* 100ms timeout*/
 633         timeout = msecs_to_jiffies(100);
 634         stoptime = jiffies + timeout;
 635         timedout = 0;
 636
 637         /* setup the phy reg to be used */
 638         xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
 639                      (phy_addr << 8) | (regnum << 0));
 640
 641         /* Issue the read command */
 642         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
 643                      (1 << O_MII_MGMT_COMMAND__rstat));
 644
 645         /* poll for the read cycle to complete */
 646         while (!timedout) {
 647                 checktime = jiffies;
 648                 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
 649                         break;
 650                 timedout = time_after(checktime, stoptime);
 651         }
 652         if (timedout) {
 653                 pr_info("Phy device read err: device busy");
 654                 return -EBUSY;
 655         }
 656
 657         /* clear the read cycle */
 658         xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
 659
 660         /* Read the data */
 661         return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
 662 }
 663
 664 static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
 665 {
 666         struct xlr_net_priv *priv = bus->priv;
 667         int ret;
 668
 669         ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
 670         dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
 671                 phy_addr, regnum, val, ret);
 672         return ret;
 673 }
 674
 675 static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
 676 {
 677         struct xlr_net_priv *priv = bus->priv;
 678         int ret;
 679
 680         ret =  xlr_phy_read(priv->mii_addr, phy_addr, regnum);
 681         dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
 682                 phy_addr, regnum, ret);
 683         return ret;
 684 }
 685
 686 /*
 687  * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
 688  * which can be configured either SGMII or RGMII, considered SGMII
 689  * by default, if board setup to RGMII the port_type need to set
 690  * accordingly.Serdes and PCS layer need to configured for SGMII
 691  */
 692 static void xlr_sgmii_init(struct xlr_net_priv *priv)
 693 {
 694         int phy;
 695
 696         xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
 697         xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
 698         xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
 699         xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
 700         xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
 701         xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
 702         xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
 703         xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
 704         xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
 705         xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
 706         xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
 707
 708         /* program  GPIO values for serdes init parameters */
 709         xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
 710         xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
 711
 712         xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
 713         xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
 714
 715         /* enable autoneg - more magic */
 716         phy = priv->phy_addr % 4 + 27;
 717         xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
 718         xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
 719 }
 720
 721 void xlr_set_gmac_speed(struct xlr_net_priv *priv)
 722 {
 723         struct phy_device *phydev = xlr_get_phydev(priv);
 724         int speed;
 725
 726         if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
 727                 xlr_sgmii_init(priv);
 728
 729         if (phydev->speed != priv->phy_speed) {
 730                 speed = phydev->speed;
 731                 if (speed == SPEED_1000) {
 732                         /* Set interface to Byte mode */
 733                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
 734                         priv->phy_speed = speed;
 735                 } else if (speed == SPEED_100 || speed == SPEED_10) {
 736                         /* Set interface to Nibble mode */
 737                         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
 738                         priv->phy_speed = speed;
 739                 }
 740                 /* Set SGMII speed in Interface control reg */
 741                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 742                         if (speed == SPEED_10)
 743                                 xlr_nae_wreg(priv->base_addr,
 744                                              R_INTERFACE_CONTROL,
 745                                              SGMII_SPEED_10);
 746                         if (speed == SPEED_100)
 747                                 xlr_nae_wreg(priv->base_addr,
 748                                              R_INTERFACE_CONTROL,
 749                                              SGMII_SPEED_100);
 750                         if (speed == SPEED_1000)
 751                                 xlr_nae_wreg(priv->base_addr,
 752                                              R_INTERFACE_CONTROL,
 753                                              SGMII_SPEED_1000);
 754                 }
 755                 if (speed == SPEED_10)
 756                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
 757                 if (speed == SPEED_100)
 758                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
 759                 if (speed == SPEED_1000)
 760                         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
 761         }
 762         pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
 763 }
 764
 765 static void xlr_gmac_link_adjust(struct net_device *ndev)
 766 {
 767         struct xlr_net_priv *priv = netdev_priv(ndev);
 768         struct phy_device *phydev = xlr_get_phydev(priv);
 769         u32 intreg;
 770
 771         intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
 772         if (phydev->link) {
 773                 if (phydev->speed != priv->phy_speed) {
 774                         xlr_set_gmac_speed(priv);
 775                         pr_info("gmac%d : Link up\n", priv->port_id);
 776                 }
 777         } else {
 778                 xlr_set_gmac_speed(priv);
 779                 pr_info("gmac%d : Link down\n", priv->port_id);
 780         }
 781 }
 782
 783 static int xlr_mii_probe(struct xlr_net_priv *priv)
 784 {
 785         struct phy_device *phydev = xlr_get_phydev(priv);
 786
 787         if (!phydev) {
 788                 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
 789                 return -ENODEV;
 790         }
 791
 792         /* Attach MAC to PHY */
 793         phydev = phy_connect(priv->ndev, phydev_name(phydev),
 794                              xlr_gmac_link_adjust, priv->nd->phy_interface);
 795
 796         if (IS_ERR(phydev)) {
 797                 pr_err("could not attach PHY\n");
 798                 return PTR_ERR(phydev);
 799         }
 800         phydev->supported &= (ADVERTISED_10baseT_Full
 801                                 | ADVERTISED_10baseT_Half
 802                                 | ADVERTISED_100baseT_Full
 803                                 | ADVERTISED_100baseT_Half
 804                                 | ADVERTISED_1000baseT_Full
 805                                 | ADVERTISED_Autoneg
 806                                 | ADVERTISED_MII);
 807
 808         phydev->advertising = phydev->supported;
 809         phy_attached_info(phydev);
 810         return 0;
 811 }
 812
 813 static int xlr_setup_mdio(struct xlr_net_priv *priv,
 814                           struct platform_device *pdev)
 815 {
 816         int err;
 817
 818         priv->mii_bus = mdiobus_alloc();
 819         if (!priv->mii_bus) {
 820                 pr_err("mdiobus alloc failed\n");
 821                 return -ENOMEM;
 822         }
 823
 824         priv->mii_bus->priv = priv;
 825         priv->mii_bus->name = "xlr-mdio";
 826         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
 827                  priv->mii_bus->name, priv->port_id);
 828         priv->mii_bus->read = xlr_mii_read;
 829         priv->mii_bus->write = xlr_mii_write;
 830         priv->mii_bus->parent = &pdev->dev;
 831
 832         /* Scan only the enabled address */
 833         priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
 834
 835         /* setting clock divisor to 54 */
 836         xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
 837
 838         err = mdiobus_register(priv->mii_bus);
 839         if (err) {
 840                 mdiobus_free(priv->mii_bus);
 841                 pr_err("mdio bus registration failed\n");
 842                 return err;
 843         }
 844
 845         pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
 846         err = xlr_mii_probe(priv);
 847         if (err) {
 848                 mdiobus_free(priv->mii_bus);
 849                 return err;
 850         }
 851         return 0;
 852 }
 853
 854 static void xlr_port_enable(struct xlr_net_priv *priv)
 855 {
 856         u32 prid = (read_c0_prid() & 0xf000);
 857
 858         /* Setup MAC_CONFIG reg if (xls & rgmii) */
 859         if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
 860             priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
 861                 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
 862                                (1 << O_RX_CONTROL__RGMII),
 863                                (1 << O_RX_CONTROL__RGMII));
 864
 865         /* Rx Tx enable */
 866         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
 867                        ((1 << O_MAC_CONFIG_1__rxen) |
 868                         (1 << O_MAC_CONFIG_1__txen) |
 869                         (1 << O_MAC_CONFIG_1__rxfc) |
 870                         (1 << O_MAC_CONFIG_1__txfc)),
 871                        ((1 << O_MAC_CONFIG_1__rxen) |
 872                         (1 << O_MAC_CONFIG_1__txen) |
 873                         (1 << O_MAC_CONFIG_1__rxfc) |
 874                         (1 << O_MAC_CONFIG_1__txfc)));
 875
 876         /* Setup tx control reg */
 877         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
 878                        ((1 << O_TX_CONTROL__TXENABLE) |
 879                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
 880
 881         /* Setup rx control reg */
 882         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
 883                        1 << O_RX_CONTROL__RXENABLE,
 884                        1 << O_RX_CONTROL__RXENABLE);
 885 }
 886
 887 static void xlr_port_disable(struct xlr_net_priv *priv)
 888 {
 889         /* Setup MAC_CONFIG reg */
 890         /* Rx Tx disable*/
 891         xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
 892                        ((1 << O_MAC_CONFIG_1__rxen) |
 893                         (1 << O_MAC_CONFIG_1__txen) |
 894                         (1 << O_MAC_CONFIG_1__rxfc) |
 895                         (1 << O_MAC_CONFIG_1__txfc)), 0x0);
 896
 897         /* Setup tx control reg */
 898         xlr_reg_update(priv->base_addr, R_TX_CONTROL,
 899                        ((1 << O_TX_CONTROL__TXENABLE) |
 900                        (512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
 901
 902         /* Setup rx control reg */
 903         xlr_reg_update(priv->base_addr, R_RX_CONTROL,
 904                        1 << O_RX_CONTROL__RXENABLE, 0);
 905 }
 906
 907 /*
 908  * Initialization of gmac
 909  */
 910 static int xlr_gmac_init(struct xlr_net_priv *priv,
 911                          struct platform_device *pdev)
 912 {
 913         int ret;
 914
 915         pr_info("Initializing the gmac%d\n", priv->port_id);
 916
 917         xlr_port_disable(priv);
 918
 919         xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
 920                      (1 << O_DESC_PACK_CTRL__MAXENTRY) |
 921                      (BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
 922                      (1600 << O_DESC_PACK_CTRL__REGULARSIZE));
 923
 924         ret = xlr_setup_mdio(priv, pdev);
 925         if (ret)
 926                 return ret;
 927         xlr_port_enable(priv);
 928
 929         /* Enable Full-duplex/1000Mbps/CRC */
 930         xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
 931         /* speed 2.5Mhz */
 932         xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
 933         /* Setup Interrupt mask reg */
 934         xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
 935                      (1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
 936                      (1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
 937                      (1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
 938
 939         /* Clear all stats */
 940         xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
 941         xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
 942         return 0;
 943 }
 944
 945 static int xlr_net_probe(struct platform_device *pdev)
 946 {
 947         struct xlr_net_priv *priv = NULL;
 948         struct net_device *ndev;
 949         struct resource *res;
 950         struct xlr_adapter *adapter;
 951         int err, port;
 952
 953         pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
 954         /*
 955          * Allocate our adapter data structure and attach it to the device.
 956          */
 957         adapter = devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
 958         if (!adapter)
 959                 return -ENOMEM;
 960
 961         /*
 962          * XLR and XLS have 1 and 2 NAE controller respectively
 963          * Each controller has 4 gmac ports, mapping each controller
 964          * under one parent device, 4 gmac ports under one device.
 965          */
 966         for (port = 0; port < pdev->num_resources / 2; port++) {
 967                 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
 968                 if (!ndev) {
 969                         dev_err(&pdev->dev,
 970                                 "Allocation of Ethernet device failed\n");
 971                         return -ENOMEM;
 972                 }
 973
 974                 priv = netdev_priv(ndev);
 975                 priv->pdev = pdev;
 976                 priv->ndev = ndev;
 977                 priv->port_id = (pdev->id * 4) + port;
 978                 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
 979                 priv->base_addr = devm_platform_ioremap_resource(pdev, port);
 980                 if (IS_ERR(priv->base_addr)) {
 981                         err = PTR_ERR(priv->base_addr);
 982                         goto err_gmac;
 983                 }
 984                 priv->adapter = adapter;
 985                 adapter->netdev[port] = ndev;
 986
 987                 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
 988                 if (!res) {
 989                         dev_err(&pdev->dev, "No irq resource for MAC %d\n",
 990                                 priv->port_id);
 991                         err = -ENODEV;
 992                         goto err_gmac;
 993                 }
 994
 995                 ndev->irq = res->start;
 996
 997                 priv->phy_addr = priv->nd->phy_addr[port];
 998                 priv->tx_stnid = priv->nd->tx_stnid[port];
 999                 priv->mii_addr = priv->nd->mii_addr;
1000                 priv->serdes_addr = priv->nd->serdes_addr;
1001                 priv->pcs_addr = priv->nd->pcs_addr;
1002                 priv->gpio_addr = priv->nd->gpio_addr;
1003
1004                 ndev->netdev_ops = &xlr_netdev_ops;
1005                 ndev->watchdog_timeo = HZ;
1006
1007                 /* Setup Mac address and Rx mode */
1008                 eth_hw_addr_random(ndev);
1009                 xlr_hw_set_mac_addr(ndev);
1010                 xlr_set_rx_mode(ndev);
1011
1012                 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1013                 ndev->ethtool_ops = &xlr_ethtool_ops;
1014                 SET_NETDEV_DEV(ndev, &pdev->dev);
1015
1016                 xlr_config_fifo_spill_area(priv);
1017                 /* Configure PDE to Round-Robin pkt distribution */
1018                 xlr_config_pde(priv);
1019                 xlr_config_parser(priv);
1020
1021                 /* Call init with respect to port */
1022                 if (strcmp(res->name, "gmac") == 0) {
1023                         err = xlr_gmac_init(priv, pdev);
1024                         if (err) {
1025                                 dev_err(&pdev->dev, "gmac%d init failed\n",
1026                                         priv->port_id);
1027                                 goto err_gmac;
1028                         }
1029                 }
1030
1031                 if (priv->port_id == 0 || priv->port_id == 4) {
1032                         err = xlr_config_common(priv);
1033                         if (err)
1034                                 goto err_netdev;
1035                 }
1036
1037                 err = register_netdev(ndev);
1038                 if (err) {
1039                         dev_err(&pdev->dev,
1040                                 "Registering netdev failed for gmac%d\n",
1041                                 priv->port_id);
1042                         goto err_netdev;
1043                 }
1044                 platform_set_drvdata(pdev, priv);
1045         }
1046
1047         return 0;
1048
1049 err_netdev:
1050         mdiobus_free(priv->mii_bus);
1051 err_gmac:
1052         free_netdev(ndev);
1053         return err;
1054 }
1055
1056 static int xlr_net_remove(struct platform_device *pdev)
1057 {
1058         struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1059
1060         unregister_netdev(priv->ndev);
1061         mdiobus_unregister(priv->mii_bus);
1062         mdiobus_free(priv->mii_bus);
1063         free_netdev(priv->ndev);
1064         return 0;
1065 }
1066
1067 static struct platform_driver xlr_net_driver = {
1068         .probe          = xlr_net_probe,
1069         .remove         = xlr_net_remove,
1070         .driver         = {
1071                 .name   = "xlr-net",
1072         },
1073 };
1074
1075 module_platform_driver(xlr_net_driver);
1076
1077 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1078 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1079 MODULE_LICENSE("Dual BSD/GPL");
1080 MODULE_ALIAS("platform:xlr-net");