1 // SPDX-License-Identifier: GPL-2.0+
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
11 * May 2009 Bruce Chang
12 * support RT2880/RT3883 PCIe
14 * May 2011 Bruce Chang
15 * support RT6855/MT7620 PCIe
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/sys_soc.h>
33 /* MediaTek specific configuration registers */
34 #define PCIE_FTS_NUM 0x70c
35 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
36 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
38 /* Host-PCI bridge registers */
39 #define RALINK_PCI_PCICFG_ADDR 0x0000
40 #define RALINK_PCI_PCIMSK_ADDR 0x000C
41 #define RALINK_PCI_CONFIG_ADDR 0x0020
42 #define RALINK_PCI_CONFIG_DATA 0x0024
43 #define RALINK_PCI_MEMBASE 0x0028
44 #define RALINK_PCI_IOBASE 0x002C
46 /* PCIe RC control registers */
47 #define RALINK_PCI_ID 0x0030
48 #define RALINK_PCI_CLASS 0x0034
49 #define RALINK_PCI_SUBID 0x0038
50 #define RALINK_PCI_STATUS 0x0050
52 /* Some definition values */
53 #define PCIE_REVISION_ID BIT(0)
54 #define PCIE_CLASS_CODE (0x60400 << 8)
55 #define PCIE_BAR_MAP_MAX GENMASK(30, 16)
56 #define PCIE_BAR_ENABLE BIT(0)
57 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
58 #define PCIE_PORT_LINKUP BIT(0)
60 #define PERST_DELAY_MS 100
63 * struct mt7621_pcie_port - PCIe port information
64 * @base: I/O mapped register base
66 * @pcie: pointer to PCIe host info
67 * @clk: pointer to the port clock gate
68 * @phy: pointer to PHY control block
69 * @pcie_rst: pointer to port reset control
70 * @gpio_rst: gpio reset
72 * @enabled: indicates if port is enabled
74 struct mt7621_pcie_port {
76 struct list_head list;
77 struct mt7621_pcie *pcie;
80 struct reset_control *pcie_rst;
81 struct gpio_desc *gpio_rst;
87 * struct mt7621_pcie - PCIe host information
88 * @base: IO Mapped Register Base
89 * @dev: Pointer to PCIe device
90 * @ports: pointer to PCIe port information
91 * @resets_inverted: depends on chip revision
92 * reset lines are inverted.
97 struct list_head ports;
101 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
103 return readl_relaxed(pcie->base + reg);
106 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
108 writel_relaxed(val, pcie->base + reg);
111 static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
113 u32 val = readl_relaxed(pcie->base + reg);
117 writel_relaxed(val, pcie->base + reg);
120 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
122 return readl_relaxed(port->base + reg);
125 static inline void pcie_port_write(struct mt7621_pcie_port *port,
128 writel_relaxed(val, port->base + reg);
131 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
132 unsigned int func, unsigned int where)
134 return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
135 (func << 8) | (where & 0xfc) | 0x80000000;
138 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
139 unsigned int devfn, int where)
141 struct mt7621_pcie *pcie = bus->sysdata;
142 u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
143 PCI_FUNC(devfn), where);
145 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
147 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
150 struct pci_ops mt7621_pci_ops = {
151 .map_bus = mt7621_pcie_map_bus,
152 .read = pci_generic_config_read,
153 .write = pci_generic_config_write,
156 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
158 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
160 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
161 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
164 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
167 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
169 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
170 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
173 static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
176 gpiod_set_value(port->gpio_rst, 1);
179 static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
182 gpiod_set_value(port->gpio_rst, 0);
185 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
187 return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
190 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
192 struct mt7621_pcie *pcie = port->pcie;
194 if (pcie->resets_inverted)
195 reset_control_assert(port->pcie_rst);
197 reset_control_deassert(port->pcie_rst);
200 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
202 struct mt7621_pcie *pcie = port->pcie;
204 if (pcie->resets_inverted)
205 reset_control_deassert(port->pcie_rst);
207 reset_control_assert(port->pcie_rst);
210 static int setup_cm_memory_region(struct pci_host_bridge *host)
212 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
213 struct device *dev = pcie->dev;
214 struct resource_entry *entry;
215 resource_size_t mask;
217 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
219 dev_err(dev, "Cannot get memory resource\n");
223 if (mips_cps_numiocu(0)) {
225 * FIXME: hardware doesn't accept mask values with 1s after
226 * 0s (e.g. 0xffef), so it would be great to warn if that's
229 mask = ~(entry->res->end - entry->res->start);
231 write_gcr_reg1_base(entry->res->start);
232 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
233 dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
234 (unsigned long long)read_gcr_reg1_base(),
235 (unsigned long long)read_gcr_reg1_mask());
241 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
242 struct device_node *node,
245 struct mt7621_pcie_port *port;
246 struct device *dev = pcie->dev;
247 struct platform_device *pdev = to_platform_device(dev);
251 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
255 port->base = devm_platform_ioremap_resource(pdev, slot + 1);
256 if (IS_ERR(port->base))
257 return PTR_ERR(port->base);
259 port->clk = devm_get_clk_from_child(dev, node, NULL);
260 if (IS_ERR(port->clk)) {
261 dev_err(dev, "failed to get pcie%d clock\n", slot);
262 return PTR_ERR(port->clk);
265 port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
266 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
267 dev_err(dev, "failed to get pcie%d reset control\n", slot);
268 return PTR_ERR(port->pcie_rst);
271 snprintf(name, sizeof(name), "pcie-phy%d", slot);
272 port->phy = devm_of_phy_get(dev, node, name);
273 if (IS_ERR(port->phy)) {
274 dev_err(dev, "failed to get pcie-phy%d\n", slot);
275 err = PTR_ERR(port->phy);
279 port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
281 if (IS_ERR(port->gpio_rst)) {
282 dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
283 err = PTR_ERR(port->gpio_rst);
290 INIT_LIST_HEAD(&port->list);
291 list_add_tail(&port->list, &pcie->ports);
296 reset_control_put(port->pcie_rst);
300 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
302 struct device *dev = pcie->dev;
303 struct platform_device *pdev = to_platform_device(dev);
304 struct device_node *node = dev->of_node, *child;
307 pcie->base = devm_platform_ioremap_resource(pdev, 0);
308 if (IS_ERR(pcie->base))
309 return PTR_ERR(pcie->base);
311 for_each_available_child_of_node(node, child) {
314 err = of_pci_get_devfn(child);
317 dev_err(dev, "failed to parse devfn: %d\n", err);
321 slot = PCI_SLOT(err);
323 err = mt7621_pcie_parse_port(pcie, child, slot);
333 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
335 struct mt7621_pcie *pcie = port->pcie;
336 struct device *dev = pcie->dev;
337 u32 slot = port->slot;
340 err = phy_init(port->phy);
342 dev_err(dev, "failed to initialize port%d phy\n", slot);
346 err = phy_power_on(port->phy);
348 dev_err(dev, "failed to power on port%d phy\n", slot);
353 port->enabled = true;
358 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
360 struct mt7621_pcie_port *port;
362 list_for_each_entry(port, &pcie->ports, list) {
363 /* PCIe RC reset assert */
364 mt7621_control_assert(port);
366 /* PCIe EP reset assert */
367 mt7621_rst_gpio_pcie_assert(port);
370 msleep(PERST_DELAY_MS);
373 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
375 struct mt7621_pcie_port *port;
377 list_for_each_entry(port, &pcie->ports, list)
378 mt7621_control_deassert(port);
381 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
383 struct mt7621_pcie_port *port;
385 list_for_each_entry(port, &pcie->ports, list)
386 mt7621_rst_gpio_pcie_deassert(port);
388 msleep(PERST_DELAY_MS);
391 static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
393 struct device *dev = pcie->dev;
394 struct mt7621_pcie_port *port, *tmp;
397 mt7621_pcie_reset_assert(pcie);
398 mt7621_pcie_reset_rc_deassert(pcie);
400 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
401 u32 slot = port->slot;
404 port->enabled = true;
408 err = mt7621_pcie_init_port(port);
410 dev_err(dev, "Initiating port %d failed\n", slot);
411 list_del(&port->list);
415 mt7621_pcie_reset_ep_deassert(pcie);
418 list_for_each_entry(port, &pcie->ports, list) {
419 u32 slot = port->slot;
421 if (!mt7621_pcie_port_is_linkup(port)) {
422 dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
424 mt7621_control_assert(port);
425 port->enabled = false;
432 if (slot == 1 && tmp && !tmp->enabled)
433 phy_power_off(tmp->phy);
438 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
440 struct mt7621_pcie *pcie = port->pcie;
441 u32 slot = port->slot;
444 /* enable pcie interrupt */
445 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
446 val |= PCIE_PORT_INT_EN(slot);
447 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
449 /* map 2G DDR region */
450 pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
453 /* configure class code and revision ID */
454 pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
457 /* configure RC FTS number to 250 when it leaves L0s */
458 val = read_config(pcie, slot, PCIE_FTS_NUM);
459 val &= ~PCIE_FTS_NUM_MASK;
460 val |= PCIE_FTS_NUM_L0(0x50);
461 write_config(pcie, slot, PCIE_FTS_NUM, val);
464 static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
466 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
467 struct device *dev = pcie->dev;
468 struct mt7621_pcie_port *port;
469 struct resource_entry *entry;
472 entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
474 dev_err(dev, "Cannot get io resource\n");
478 /* Setup MEMWIN and IOWIN */
479 pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
480 pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);
482 list_for_each_entry(port, &pcie->ports, list) {
484 err = clk_prepare_enable(port->clk);
486 dev_err(dev, "enabling clk pcie%d\n",
491 mt7621_pcie_enable_port(port);
492 dev_info(dev, "PCIE%d enabled\n", port->slot);
499 static int mt7621_pcie_register_host(struct pci_host_bridge *host)
501 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
503 host->ops = &mt7621_pci_ops;
504 host->sysdata = pcie;
505 return pci_host_probe(host);
508 static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
509 { .soc_id = "mt7621", .revision = "E2" }
512 static int mt7621_pci_probe(struct platform_device *pdev)
514 struct device *dev = &pdev->dev;
515 const struct soc_device_attribute *attr;
516 struct mt7621_pcie_port *port;
517 struct mt7621_pcie *pcie;
518 struct pci_host_bridge *bridge;
524 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
528 pcie = pci_host_bridge_priv(bridge);
530 platform_set_drvdata(pdev, pcie);
531 INIT_LIST_HEAD(&pcie->ports);
533 attr = soc_device_match(mt7621_pci_quirks_match);
535 pcie->resets_inverted = true;
537 err = mt7621_pcie_parse_dt(pcie);
539 dev_err(dev, "Parsing DT failed\n");
543 mt7621_pcie_init_ports(pcie);
545 err = mt7621_pcie_enable_ports(bridge);
547 dev_err(dev, "Error enabling pcie ports\n");
551 err = setup_cm_memory_region(bridge);
553 dev_err(dev, "Error setting up iocu mem regions\n");
557 return mt7621_pcie_register_host(bridge);
560 list_for_each_entry(port, &pcie->ports, list)
561 reset_control_put(port->pcie_rst);
566 static int mt7621_pci_remove(struct platform_device *pdev)
568 struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
569 struct mt7621_pcie_port *port;
571 list_for_each_entry(port, &pcie->ports, list)
572 reset_control_put(port->pcie_rst);
577 static const struct of_device_id mt7621_pci_ids[] = {
578 { .compatible = "mediatek,mt7621-pci" },
581 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
583 static struct platform_driver mt7621_pci_driver = {
584 .probe = mt7621_pci_probe,
585 .remove = mt7621_pci_remove,
587 .name = "mt7621-pci",
588 .of_match_table = of_match_ptr(mt7621_pci_ids),
591 builtin_platform_driver(mt7621_pci_driver);