1 // SPDX-License-Identifier: GPL-2.0+
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
11 * May 2009 Bruce Chang
12 * support RT2880/RT3883 PCIe
14 * May 2011 Bruce Chang
15 * support RT6855/MT7620 PCIe
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/iopoll.h>
22 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/of_platform.h>
28 #include <linux/pci.h>
29 #include <linux/phy/phy.h>
30 #include <linux/platform_device.h>
31 #include <linux/reset.h>
33 #include <ralink_regs.h>
35 #include "../../pci/pci.h"
38 #define MT7621_CHIP_REV_ID 0x0c
39 #define MT7621_GPIO_MODE 0x60
40 #define CHIP_REV_MT7621_E2 0x0101
42 /* MediaTek specific configuration registers */
43 #define PCIE_FTS_NUM 0x70c
44 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
45 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
47 /* rt_sysc_membase relative registers */
48 #define RALINK_CLKCFG1 0x30
49 #define RALINK_PCIE_CLK_GEN 0x7c
50 #define RALINK_PCIE_CLK_GEN1 0x80
52 /* Host-PCI bridge registers */
53 #define RALINK_PCI_PCICFG_ADDR 0x0000
54 #define RALINK_PCI_PCIMSK_ADDR 0x000C
55 #define RALINK_PCI_CONFIG_ADDR 0x0020
56 #define RALINK_PCI_CONFIG_DATA 0x0024
57 #define RALINK_PCI_MEMBASE 0x0028
58 #define RALINK_PCI_IOBASE 0x002C
60 /* PCICFG virtual bridges */
61 #define MT7621_BR0_MASK GENMASK(19, 16)
62 #define MT7621_BR1_MASK GENMASK(23, 20)
63 #define MT7621_BR2_MASK GENMASK(27, 24)
64 #define MT7621_BR_ALL_MASK GENMASK(27, 16)
65 #define MT7621_BR0_SHIFT 16
66 #define MT7621_BR1_SHIFT 20
67 #define MT7621_BR2_SHIFT 24
69 /* PCIe RC control registers */
70 #define MT7621_PCIE_OFFSET 0x2000
71 #define MT7621_NEXT_PORT 0x1000
73 #define RALINK_PCI_BAR0SETUP_ADDR 0x0010
74 #define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
75 #define RALINK_PCI_ID 0x0030
76 #define RALINK_PCI_CLASS 0x0034
77 #define RALINK_PCI_SUBID 0x0038
78 #define RALINK_PCI_STATUS 0x0050
80 /* Some definition values */
81 #define PCIE_REVISION_ID BIT(0)
82 #define PCIE_CLASS_CODE (0x60400 << 8)
83 #define PCIE_BAR_MAP_MAX GENMASK(30, 16)
84 #define PCIE_BAR_ENABLE BIT(0)
85 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
86 #define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
87 #define PCIE_PORT_LINKUP BIT(0)
89 #define PCIE_CLK_GEN_EN BIT(31)
90 #define PCIE_CLK_GEN_DIS 0
91 #define PCIE_CLK_GEN1_DIS GENMASK(30, 24)
92 #define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25))
93 #define MEMORY_BASE 0x0
94 #define PERST_MODE_MASK GENMASK(11, 10)
95 #define PERST_MODE_GPIO BIT(10)
96 #define PERST_DELAY_US 1000
99 * struct mt7621_pcie_port - PCIe port information
100 * @base: I/O mapped register base
102 * @pcie: pointer to PCIe host info
103 * @phy: pointer to PHY control block
104 * @pcie_rst: pointer to port reset control
106 * @enabled: indicates if port is enabled
108 struct mt7621_pcie_port {
110 struct list_head list;
111 struct mt7621_pcie *pcie;
113 struct reset_control *pcie_rst;
119 * struct mt7621_pcie - PCIe host information
120 * @base: IO Mapped Register Base
122 * @mem: non-prefetchable memory resource
124 * @offset: IO / Memory offset
125 * @dev: Pointer to PCIe device
126 * @ports: pointer to PCIe port information
128 * @rst: pointer to pcie reset
135 struct resource busn;
140 struct list_head ports;
141 struct gpio_desc *perst;
142 struct reset_control *rst;
145 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
147 return readl(pcie->base + reg);
150 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
152 writel(val, pcie->base + reg);
155 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
157 return readl(port->base + reg);
160 static inline void pcie_port_write(struct mt7621_pcie_port *port,
163 writel(val, port->base + reg);
166 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
167 unsigned int func, unsigned int where)
169 return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
170 (func << 8) | (where & 0xfc) | 0x80000000;
173 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
174 unsigned int devfn, int where)
176 struct mt7621_pcie *pcie = bus->sysdata;
177 u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
178 PCI_FUNC(devfn), where);
180 writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
182 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
185 struct pci_ops mt7621_pci_ops = {
186 .map_bus = mt7621_pcie_map_bus,
187 .read = pci_generic_config_read,
188 .write = pci_generic_config_write,
191 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
193 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
195 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
196 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
199 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
202 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
204 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
205 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
208 static inline void mt7621_perst_gpio_pcie_assert(struct mt7621_pcie *pcie)
210 gpiod_set_value(pcie->perst, 0);
211 mdelay(PERST_DELAY_US);
214 static inline void mt7621_perst_gpio_pcie_deassert(struct mt7621_pcie *pcie)
216 gpiod_set_value(pcie->perst, 1);
217 mdelay(PERST_DELAY_US);
220 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
222 return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
225 static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
227 rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
230 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
232 u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
234 if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
235 reset_control_assert(port->pcie_rst);
237 reset_control_deassert(port->pcie_rst);
240 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
242 u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
244 if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
245 reset_control_deassert(port->pcie_rst);
247 reset_control_assert(port->pcie_rst);
250 static void mt7621_reset_port(struct mt7621_pcie_port *port)
252 mt7621_control_assert(port);
254 mt7621_control_deassert(port);
257 static void setup_cm_memory_region(struct mt7621_pcie *pcie)
259 struct resource *mem_resource = &pcie->mem;
260 struct device *dev = pcie->dev;
261 resource_size_t mask;
263 if (mips_cps_numiocu(0)) {
265 * FIXME: hardware doesn't accept mask values with 1s after
266 * 0s (e.g. 0xffef), so it would be great to warn if that's
269 mask = ~(mem_resource->end - mem_resource->start);
271 write_gcr_reg1_base(mem_resource->start);
272 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
273 dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
274 (unsigned long long)read_gcr_reg1_base(),
275 (unsigned long long)read_gcr_reg1_mask());
279 static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
281 struct device *dev = pcie->dev;
282 struct device_node *node = dev->of_node;
283 struct of_pci_range_parser parser;
284 struct of_pci_range range;
287 if (of_pci_range_parser_init(&parser, node)) {
288 dev_err(dev, "missing \"ranges\" property\n");
292 for_each_of_pci_range(&parser, &range) {
293 struct resource *res = NULL;
295 switch (range.flags & IORESOURCE_TYPE_BITS) {
297 ioremap(range.cpu_addr, range.size);
299 pcie->offset.io = 0x00000000UL;
303 pcie->offset.mem = 0x00000000UL;
308 of_pci_range_to_resource(&range, node, res);
311 err = of_pci_parse_bus_range(node, &pcie->busn);
313 dev_err(dev, "failed to parse bus ranges property: %d\n", err);
314 pcie->busn.name = node->name;
315 pcie->busn.start = 0;
316 pcie->busn.end = 0xff;
317 pcie->busn.flags = IORESOURCE_BUS;
323 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
324 struct device_node *node,
327 struct mt7621_pcie_port *port;
328 struct device *dev = pcie->dev;
329 struct device_node *pnode = dev->of_node;
330 struct resource regs;
334 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
338 err = of_address_to_resource(pnode, slot + 1, ®s);
340 dev_err(dev, "missing \"reg\" property\n");
344 port->base = devm_ioremap_resource(dev, ®s);
345 if (IS_ERR(port->base))
346 return PTR_ERR(port->base);
348 snprintf(name, sizeof(name), "pcie%d", slot);
349 port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
350 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
351 dev_err(dev, "failed to get pcie%d reset control\n", slot);
352 return PTR_ERR(port->pcie_rst);
355 snprintf(name, sizeof(name), "pcie-phy%d", slot);
356 port->phy = devm_phy_get(dev, name);
357 if (IS_ERR(port->phy))
358 return PTR_ERR(port->phy);
363 INIT_LIST_HEAD(&port->list);
364 list_add_tail(&port->list, &pcie->ports);
369 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
371 struct device *dev = pcie->dev;
372 struct device_node *node = dev->of_node, *child;
373 struct resource regs;
376 pcie->perst = devm_gpiod_get(dev, "perst", GPIOD_OUT_HIGH);
377 if (IS_ERR(pcie->perst)) {
378 dev_err(dev, "failed to get gpio perst\n");
379 return PTR_ERR(pcie->perst);
382 err = of_address_to_resource(node, 0, ®s);
384 dev_err(dev, "missing \"reg\" property\n");
388 pcie->base = devm_ioremap_resource(dev, ®s);
389 if (IS_ERR(pcie->base))
390 return PTR_ERR(pcie->base);
392 pcie->rst = devm_reset_control_get_exclusive(dev, "pcie");
393 if (PTR_ERR(pcie->rst) == -EPROBE_DEFER) {
394 dev_err(dev, "failed to get pcie reset control\n");
395 return PTR_ERR(pcie->rst);
398 for_each_available_child_of_node(node, child) {
401 err = of_pci_get_devfn(child);
403 dev_err(dev, "failed to parse devfn: %d\n", err);
407 slot = PCI_SLOT(err);
409 err = mt7621_pcie_parse_port(pcie, child, slot);
417 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
419 struct mt7621_pcie *pcie = port->pcie;
420 struct device *dev = pcie->dev;
421 u32 slot = port->slot;
425 * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at
426 * the end of the chip_id has inverted PCI resets.
428 mt7621_reset_port(port);
430 err = phy_init(port->phy);
432 dev_err(dev, "failed to initialize port%d phy\n", slot);
436 err = phy_power_on(port->phy);
438 dev_err(dev, "failed to power on port%d phy\n", slot);
443 port->enabled = true;
448 static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
450 struct device *dev = pcie->dev;
451 struct mt7621_pcie_port *port, *tmp;
455 rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
457 mt7621_perst_gpio_pcie_assert(pcie);
459 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
460 u32 slot = port->slot;
462 err = mt7621_pcie_init_port(port);
464 dev_err(dev, "Initiating port %d failed\n", slot);
465 list_del(&port->list);
467 val = read_config(pcie, slot, PCIE_FTS_NUM);
468 dev_info(dev, "Port %d N_FTS = %x\n", slot,
473 reset_control_assert(pcie->rst);
475 mt7621_perst_gpio_pcie_deassert(pcie);
477 list_for_each_entry(port, &pcie->ports, list) {
478 u32 slot = port->slot;
480 if (!mt7621_pcie_port_is_linkup(port)) {
481 dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
483 phy_power_off(port->phy);
484 mt7621_control_assert(port);
485 mt7621_pcie_port_clk_disable(port);
486 port->enabled = false;
490 rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
491 rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
492 rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
493 rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
495 reset_control_deassert(pcie->rst);
498 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
500 struct mt7621_pcie *pcie = port->pcie;
501 u32 slot = port->slot;
502 u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
505 /* enable pcie interrupt */
506 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
507 val |= PCIE_PORT_INT_EN(slot);
508 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
510 /* map 2G DDR region */
511 pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
512 offset + RALINK_PCI_BAR0SETUP_ADDR);
513 pcie_write(pcie, MEMORY_BASE,
514 offset + RALINK_PCI_IMBASEBAR0_ADDR);
516 /* configure class code and revision ID */
517 pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
518 offset + RALINK_PCI_CLASS);
521 static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
523 struct device *dev = pcie->dev;
524 struct mt7621_pcie_port *port;
525 u8 num_slots_enabled = 0;
529 list_for_each_entry(port, &pcie->ports, list) {
531 mt7621_pcie_enable_port(port);
532 dev_info(dev, "PCIE%d enabled\n", num_slots_enabled);
537 for (slot = 0; slot < num_slots_enabled; slot++) {
538 val = read_config(pcie, slot, PCI_COMMAND);
539 val |= PCI_COMMAND_MASTER;
540 write_config(pcie, slot, PCI_COMMAND, val);
541 /* configure RC FTS number to 250 when it leaves L0s */
542 val = read_config(pcie, slot, PCIE_FTS_NUM);
543 val &= ~PCIE_FTS_NUM_MASK;
544 val |= PCIE_FTS_NUM_L0(0x50);
545 write_config(pcie, slot, PCIE_FTS_NUM, val);
549 static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
551 u32 pcie_link_status = 0;
553 struct mt7621_pcie_port *port;
555 list_for_each_entry(port, &pcie->ports, list) {
556 u32 slot = port->slot;
559 pcie_link_status |= BIT(slot);
562 if (pcie_link_status == 0)
566 * pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
576 switch (pcie_link_status) {
578 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
579 val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK);
580 val |= 0x1 << MT7621_BR0_SHIFT;
581 val |= 0x0 << MT7621_BR1_SHIFT;
582 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
585 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
586 val &= ~MT7621_BR_ALL_MASK;
587 val |= 0x1 << MT7621_BR0_SHIFT;
588 val |= 0x2 << MT7621_BR1_SHIFT;
589 val |= 0x0 << MT7621_BR2_SHIFT;
590 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
593 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
594 val &= ~MT7621_BR_ALL_MASK;
595 val |= 0x0 << MT7621_BR0_SHIFT;
596 val |= 0x2 << MT7621_BR1_SHIFT;
597 val |= 0x1 << MT7621_BR2_SHIFT;
598 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
601 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
602 val &= ~MT7621_BR_ALL_MASK;
603 val |= 0x2 << MT7621_BR0_SHIFT;
604 val |= 0x0 << MT7621_BR1_SHIFT;
605 val |= 0x1 << MT7621_BR2_SHIFT;
606 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
613 static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
614 struct list_head *res)
616 struct device *dev = pcie->dev;
619 pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
620 pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
621 pci_add_resource(res, &pcie->busn);
623 err = devm_request_pci_bus_resources(dev, res);
630 static int mt7621_pcie_register_host(struct pci_host_bridge *host,
631 struct list_head *res)
633 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
635 list_splice_init(res, &host->windows);
636 host->busnr = pcie->busn.start;
637 host->dev.parent = pcie->dev;
638 host->ops = &mt7621_pci_ops;
639 host->map_irq = of_irq_parse_and_map_pci;
640 host->swizzle_irq = pci_common_swizzle;
641 host->sysdata = pcie;
643 return pci_host_probe(host);
646 static int mt7621_pci_probe(struct platform_device *pdev)
648 struct device *dev = &pdev->dev;
649 struct mt7621_pcie *pcie;
650 struct pci_host_bridge *bridge;
657 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
661 pcie = pci_host_bridge_priv(bridge);
663 platform_set_drvdata(pdev, pcie);
664 INIT_LIST_HEAD(&pcie->ports);
666 err = mt7621_pcie_parse_dt(pcie);
668 dev_err(dev, "Parsing DT failed\n");
672 /* set resources limits */
673 iomem_resource.start = 0;
674 iomem_resource.end = ~0UL; /* no limit */
675 ioport_resource.start = 0;
676 ioport_resource.end = ~0UL; /* no limit */
678 mt7621_pcie_init_ports(pcie);
680 err = mt7621_pcie_init_virtual_bridges(pcie);
682 dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
686 mt7621_pcie_enable_ports(pcie);
688 err = mt7621_pci_parse_request_of_pci_ranges(pcie);
690 dev_err(dev, "Error requesting pci resources from ranges");
694 setup_cm_memory_region(pcie);
696 err = mt7621_pcie_request_resources(pcie, &res);
698 dev_err(dev, "Error requesting resources\n");
702 err = mt7621_pcie_register_host(bridge, &res);
704 dev_err(dev, "Error registering host\n");
711 static const struct of_device_id mt7621_pci_ids[] = {
712 { .compatible = "mediatek,mt7621-pci" },
715 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
717 static struct platform_driver mt7621_pci_driver = {
718 .probe = mt7621_pci_probe,
720 .name = "mt7621-pci",
721 .of_match_table = of_match_ptr(mt7621_pci_ids),
725 static int __init mt7621_pci_init(void)
727 return platform_driver_register(&mt7621_pci_driver);
730 module_init(mt7621_pci_init);