1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/clock/mt7621-clk.h>
8 compatible = "mediatek,mt7621-soc";
12 compatible = "mips,mips1004Kc";
16 compatible = "mips,mips1004Kc";
22 #interrupt-cells = <1>;
24 compatible = "mti,cpu-interrupt-controller";
32 mmc_fixed_3v3: fixedregulator@0 {
33 compatible = "regulator-fixed";
34 regulator-name = "mmc_power";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
41 mmc_fixed_1v8_io: fixedregulator@1 {
42 compatible = "regulator-fixed";
43 regulator-name = "mmc_io";
44 regulator-min-microvolt = <1800000>;
45 regulator-max-microvolt = <1800000>;
50 palmbus: palmbus@1E000000 {
51 compatible = "palmbus";
52 reg = <0x1E000000 0x100000>;
53 ranges = <0x0 0x1E000000 0x0FFFFF>;
59 compatible = "mediatek,mt7621-sysc", "syscon";
62 ralink,memctl = <&memc>;
63 clock-output-names = "xtal", "cpu", "bus",
64 "50m", "125m", "150m",
69 compatible = "mediatek,mt7621-wdt";
75 #interrupt-cells = <2>;
76 compatible = "mediatek,mt7621-gpio";
78 gpio-ranges = <&pinctrl 0 0 95>;
81 interrupt-parent = <&gic>;
82 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
86 compatible = "mediatek,mt7621-i2c";
89 clocks = <&sysc MT7621_CLK_I2C>;
91 resets = <&rstctrl 16>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&i2c_pins>;
104 compatible = "mediatek,mt7621-i2s";
107 clocks = <&sysc MT7621_CLK_I2S>;
109 resets = <&rstctrl 17>;
112 interrupt-parent = <&gic>;
113 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
120 dma-names = "tx", "rx";
126 compatible = "mediatek,mt7621-memc", "syscon";
127 reg = <0x5000 0x1000>;
131 compatible = "mediatek,mt7621-cpc";
132 reg = <0x1fbf0000 0x8000>;
136 compatible = "mediatek,mt7621-mc";
137 reg = <0x1fbf8000 0x8000>;
140 uartlite: uartlite@c00 {
141 compatible = "ns16550a";
144 clocks = <&sysc MT7621_CLK_UART1>;
145 clock-names = "uart1";
147 interrupt-parent = <&gic>;
148 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
158 compatible = "ralink,mt7621-spi";
161 clocks = <&sysc MT7621_CLK_SPI>;
164 resets = <&rstctrl 18>;
167 #address-cells = <1>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&spi_pins>;
175 compatible = "ralink,rt3883-gdma";
176 reg = <0x2800 0x800>;
178 clocks = <&sysc MT7621_CLK_GDMA>;
179 clock-names = "gdma";
180 resets = <&rstctrl 14>;
183 interrupt-parent = <&gic>;
184 interrupts = <0 13 4>;
187 #dma-channels = <16>;
188 #dma-requests = <16>;
194 compatible = "mediatek,mt7621-hsdma";
195 reg = <0x7000 0x1000>;
197 clocks = <&sysc MT7621_CLK_HSDMA>;
198 clock-names = "hsdma";
199 resets = <&rstctrl 5>;
200 reset-names = "hsdma";
202 interrupt-parent = <&gic>;
203 interrupts = <0 11 4>;
214 compatible = "ralink,rt2880-pinmux";
216 i2c_pins: i2c0-pins {
223 spi_pins: spi0-pins {
230 uart1_pins: uart1-pins {
237 uart2_pins: uart2-pins {
244 uart3_pins: uart3-pins {
251 rgmii1_pins: rgmii1-pins {
258 rgmii2_pins: rgmii2-pins {
265 mdio_pins: mdio0-pins {
272 pcie_pins: pcie0-pins {
279 nand_pins: nand0-pins {
291 sdhci_pins: sdhci0-pins {
300 compatible = "ralink,rt2880-reset";
304 sdhci: sdhci@1E130000 {
307 compatible = "mediatek,mt7620-mmc";
308 reg = <0x1E130000 0x4000>;
311 max-frequency = <48000000>;
314 vmmc-supply = <&mmc_fixed_3v3>;
315 vqmmc-supply = <&mmc_fixed_1v8_io>;
318 pinctrl-names = "default", "state_uhs";
319 pinctrl-0 = <&sdhci_pins>;
320 pinctrl-1 = <&sdhci_pins>;
322 clocks = <&sysc MT7621_CLK_SHXC>,
323 <&sysc MT7621_CLK_50M>;
324 clock-names = "source", "hclk";
326 interrupt-parent = <&gic>;
327 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
330 xhci: xhci@1E1C0000 {
333 compatible = "mediatek,mt8173-xhci";
334 reg = <0x1e1c0000 0x1000
336 reg-names = "mac", "ippc";
338 clocks = <&sysc MT7621_CLK_XTAL>;
339 clock-names = "sys_ck";
341 interrupt-parent = <&gic>;
342 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
345 gic: interrupt-controller@1fbc0000 {
346 compatible = "mti,gic";
347 reg = <0x1fbc0000 0x2000>;
349 interrupt-controller;
350 #interrupt-cells = <3>;
352 mti,reserved-cpu-vectors = <7>;
355 compatible = "mti,gic-timer";
356 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
357 clocks = <&sysc MT7621_CLK_CPU>;
361 nand: nand@1e003000 {
364 compatible = "mediatek,mt7621-nand";
366 reg = <0x1e003000 0x800
368 #address-cells = <1>;
371 clocks = <&sysc MT7621_CLK_NAND>;
372 clock-names = "nand";
375 ethernet: ethernet@1e100000 {
376 compatible = "mediatek,mt7621-eth";
377 reg = <0x1e100000 0x10000>;
379 clocks = <&sysc MT7621_CLK_FE>,
380 <&sysc MT7621_CLK_ETH>;
381 clock-names = "fe", "ethif";
383 #address-cells = <1>;
386 resets = <&rstctrl 6 &rstctrl 23>;
387 reset-names = "fe", "eth";
389 interrupt-parent = <&gic>;
390 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
392 mediatek,ethsys = <&sysc>;
396 compatible = "mediatek,eth-mac";
406 compatible = "mediatek,eth-mac";
409 phy-mode = "rgmii-rxid";
410 phy-handle = <&phy_external>;
413 #address-cells = <1>;
416 phy_external: ethernet-phy@5 {
419 phy-mode = "rgmii-rxid";
421 pinctrl-names = "default";
422 pinctrl-0 = <&rgmii2_pins>;
426 compatible = "mediatek,mt7621";
427 #address-cells = <1>;
431 resets = <&rstctrl 2>;
433 interrupt-controller;
434 #interrupt-cells = <1>;
435 interrupt-parent = <&gic>;
436 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
482 pcie: pcie@1e140000 {
483 compatible = "mediatek,mt7621-pci";
484 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
485 <0x1e142000 0x100>, /* pcie port 0 RC control registers */
486 <0x1e143000 0x100>, /* pcie port 1 RC control registers */
487 <0x1e144000 0x100>; /* pcie port 2 RC control registers */
488 #address-cells = <3>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pcie_pins>;
496 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
497 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
499 #interrupt-cells = <1>;
500 interrupt-map-mask = <0xF800 0 0 0>;
501 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
502 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
503 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
507 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
510 reg = <0x0000 0 0 0 0>;
511 #address-cells = <3>;
514 #interrupt-cells = <1>;
515 interrupt-map-mask = <0 0 0 0>;
516 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
517 resets = <&rstctrl 24>;
518 clocks = <&sysc MT7621_CLK_PCIE0>;
519 phys = <&pcie0_phy 1>;
520 phy-names = "pcie-phy0";
525 reg = <0x0800 0 0 0 0>;
526 #address-cells = <3>;
529 #interrupt-cells = <1>;
530 interrupt-map-mask = <0 0 0 0>;
531 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
532 resets = <&rstctrl 25>;
533 clocks = <&sysc MT7621_CLK_PCIE1>;
534 phys = <&pcie0_phy 1>;
535 phy-names = "pcie-phy1";
540 reg = <0x1000 0 0 0 0>;
541 #address-cells = <3>;
544 #interrupt-cells = <1>;
545 interrupt-map-mask = <0 0 0 0>;
546 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
547 resets = <&rstctrl 26>;
548 clocks = <&sysc MT7621_CLK_PCIE2>;
549 phys = <&pcie2_phy 0>;
550 phy-names = "pcie-phy2";
555 pcie0_phy: pcie-phy@1e149000 {
556 compatible = "mediatek,mt7621-pci-phy";
557 reg = <0x1e149000 0x0700>;
558 clocks = <&sysc MT7621_CLK_XTAL>;
562 pcie2_phy: pcie-phy@1e14a000 {
563 compatible = "mediatek,mt7621-pci-phy";
564 reg = <0x1e14a000 0x0700>;
565 clocks = <&sysc MT7621_CLK_XTAL>;