drivers/staging/mt7621-dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/gpio/gpio.h>
   3 #include <dt-bindings/clock/mt7621-clk.h>
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         compatible = "mediatek,mt7621-soc";
   9
  10         cpus {
  11                 cpu@0 {
  12                         compatible = "mips,mips1004Kc";
  13                 };
  14
  15                 cpu@1 {
  16                         compatible = "mips,mips1004Kc";
  17                 };
  18         };
  19
  20         cpuintc: cpuintc@0 {
  21                 #address-cells = <0>;
  22                 #interrupt-cells = <1>;
  23                 interrupt-controller;
  24                 compatible = "mti,cpu-interrupt-controller";
  25         };
  26
  27         aliases {
  28                 serial0 = &uartlite;
  29         };
  30
  31
  32         mmc_fixed_3v3: fixedregulator@0 {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "mmc_power";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37                 enable-active-high;
  38                 regulator-always-on;
  39           };
  40
  41           mmc_fixed_1v8_io: fixedregulator@1 {
  42                 compatible = "regulator-fixed";
  43                 regulator-name = "mmc_io";
  44                 regulator-min-microvolt = <1800000>;
  45                 regulator-max-microvolt = <1800000>;
  46                 enable-active-high;
  47                 regulator-always-on;
  48         };
  49
  50         palmbus: palmbus@1E000000 {
  51                 compatible = "palmbus";
  52                 reg = <0x1E000000 0x100000>;
  53                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  54
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57
  58                 sysc: syscon@0 {
  59                         compatible = "mediatek,mt7621-sysc", "syscon";
  60                         reg = <0x0 0x100>;
  61                         #clock-cells = <1>;
  62                         ralink,memctl = <&memc>;
  63                         clock-output-names = "xtal", "cpu", "bus",
  64                                              "50m", "125m", "150m",
  65                                              "250m", "270m";
  66                 };
  67
  68                 wdt: wdt@100 {
  69                         compatible = "mediatek,mt7621-wdt";
  70                         reg = <0x100 0x100>;
  71                 };
  72
  73                 gpio: gpio@600 {
  74                         #gpio-cells = <2>;
  75                         #interrupt-cells = <2>;
  76                         compatible = "mediatek,mt7621-gpio";
  77                         gpio-controller;
  78                         gpio-ranges = <&pinctrl 0 0 95>;
  79                         interrupt-controller;
  80                         reg = <0x600 0x100>;
  81                         interrupt-parent = <&gic>;
  82                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  83                 };
  84
  85                 i2c: i2c@900 {
  86                         compatible = "mediatek,mt7621-i2c";
  87                         reg = <0x900 0x100>;
  88
  89                         clocks = <&sysc MT7621_CLK_I2C>;
  90                         clock-names = "i2c";
  91                         resets = <&rstctrl 16>;
  92                         reset-names = "i2c";
  93
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96
  97                         status = "disabled";
  98
  99                         pinctrl-names = "default";
 100                         pinctrl-0 = <&i2c_pins>;
 101                 };
 102
 103                 i2s: i2s@a00 {
 104                         compatible = "mediatek,mt7621-i2s";
 105                         reg = <0xa00 0x100>;
 106
 107                         clocks = <&sysc MT7621_CLK_I2S>;
 108                         clock-names = "i2s";
 109                         resets = <&rstctrl 17>;
 110                         reset-names = "i2s";
 111
 112                         interrupt-parent = <&gic>;
 113                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 114
 115                         txdma-req = <2>;
 116                         rxdma-req = <3>;
 117
 118                         dmas = <&gdma 4>,
 119                                 <&gdma 6>;
 120                         dma-names = "tx", "rx";
 121
 122                         status = "disabled";
 123                 };
 124
 125                 memc: syscon@5000 {
 126                         compatible = "mediatek,mt7621-memc", "syscon";
 127                         reg = <0x5000 0x1000>;
 128                 };
 129
 130                 cpc: cpc@1fbf0000 {
 131                              compatible = "mediatek,mt7621-cpc";
 132                              reg = <0x1fbf0000 0x8000>;
 133                 };
 134
 135                 mc: mc@1fbf8000 {
 136                             compatible = "mediatek,mt7621-mc";
 137                             reg = <0x1fbf8000 0x8000>;
 138                 };
 139
 140                 uartlite: uartlite@c00 {
 141                         compatible = "ns16550a";
 142                         reg = <0xc00 0x100>;
 143
 144                         clocks = <&sysc MT7621_CLK_UART1>;
 145                         clock-names = "uart1";
 146
 147                         interrupt-parent = <&gic>;
 148                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 149
 150                         reg-shift = <2>;
 151                         reg-io-width = <4>;
 152                         no-loopback-test;
 153                 };
 154
 155                 spi0: spi@b00 {
 156                         status = "disabled";
 157
 158                         compatible = "ralink,mt7621-spi";
 159                         reg = <0xb00 0x100>;
 160
 161                         clocks = <&sysc MT7621_CLK_SPI>;
 162                         clock-names = "spi";
 163
 164                         resets = <&rstctrl 18>;
 165                         reset-names = "spi";
 166
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169
 170                         pinctrl-names = "default";
 171                         pinctrl-0 = <&spi_pins>;
 172                 };
 173
 174                 gdma: gdma@2800 {
 175                         compatible = "ralink,rt3883-gdma";
 176                         reg = <0x2800 0x800>;
 177
 178                         clocks = <&sysc MT7621_CLK_GDMA>;
 179                         clock-names = "gdma";
 180                         resets = <&rstctrl 14>;
 181                         reset-names = "dma";
 182
 183                         interrupt-parent = <&gic>;
 184                         interrupts = <0 13 4>;
 185
 186                         #dma-cells = <1>;
 187                         #dma-channels = <16>;
 188                         #dma-requests = <16>;
 189
 190                         status = "disabled";
 191                 };
 192
 193                 hsdma: hsdma@7000 {
 194                         compatible = "mediatek,mt7621-hsdma";
 195                         reg = <0x7000 0x1000>;
 196
 197                         clocks = <&sysc MT7621_CLK_HSDMA>;
 198                         clock-names = "hsdma";
 199                         resets = <&rstctrl 5>;
 200                         reset-names = "hsdma";
 201
 202                         interrupt-parent = <&gic>;
 203                         interrupts = <0 11 4>;
 204
 205                         #dma-cells = <1>;
 206                         #dma-channels = <1>;
 207                         #dma-requests = <1>;
 208
 209                         status = "disabled";
 210                 };
 211         };
 212
 213         pinctrl: pinctrl {
 214                 compatible = "ralink,rt2880-pinmux";
 215
 216                 i2c_pins: i2c0-pins {
 217                         pinmux {
 218                                 groups = "i2c";
 219                                 function = "i2c";
 220                         };
 221                 };
 222
 223                 spi_pins: spi0-pins {
 224                         pinmux {
 225                                 groups = "spi";
 226                                 function = "spi";
 227                         };
 228                 };
 229
 230                 uart1_pins: uart1-pins {
 231                         pinmux {
 232                                 groups = "uart1";
 233                                 function = "uart1";
 234                         };
 235                 };
 236
 237                 uart2_pins: uart2-pins {
 238                         pinmux {
 239                                 groups = "uart2";
 240                                 function = "uart2";
 241                         };
 242                 };
 243
 244                 uart3_pins: uart3-pins {
 245                         pinmux {
 246                                 groups = "uart3";
 247                                 function = "uart3";
 248                         };
 249                 };
 250
 251                 rgmii1_pins: rgmii1-pins {
 252                         pinmux {
 253                                 groups = "rgmii1";
 254                                 function = "rgmii1";
 255                         };
 256                 };
 257
 258                 rgmii2_pins: rgmii2-pins {
 259                         pinmux {
 260                                 groups = "rgmii2";
 261                                 function = "rgmii2";
 262                         };
 263                 };
 264
 265                 mdio_pins: mdio0-pins {
 266                         pinmux {
 267                                 groups = "mdio";
 268                                 function = "mdio";
 269                         };
 270                 };
 271
 272                 pcie_pins: pcie0-pins {
 273                         pinmux {
 274                                 groups = "pcie";
 275                                 function = "gpio";
 276                         };
 277                 };
 278
 279                 nand_pins: nand0-pins {
 280                         spi-pinmux {
 281                                 groups = "spi";
 282                                 function = "nand1";
 283                         };
 284
 285                         sdhci-pinmux {
 286                                 groups = "sdhci";
 287                                 function = "nand2";
 288                         };
 289                 };
 290
 291                 sdhci_pins: sdhci0-pins {
 292                         pinmux {
 293                                 groups = "sdhci";
 294                                 function = "sdhci";
 295                         };
 296                 };
 297         };
 298
 299         rstctrl: rstctrl {
 300                 compatible = "ralink,rt2880-reset";
 301                 #reset-cells = <1>;
 302         };
 303
 304         sdhci: sdhci@1E130000 {
 305                 status = "disabled";
 306
 307                 compatible = "mediatek,mt7620-mmc";
 308                 reg = <0x1E130000 0x4000>;
 309
 310                 bus-width = <4>;
 311                 max-frequency = <48000000>;
 312                 cap-sd-highspeed;
 313                 cap-mmc-highspeed;
 314                 vmmc-supply = <&mmc_fixed_3v3>;
 315                 vqmmc-supply = <&mmc_fixed_1v8_io>;
 316                 disable-wp;
 317
 318                 pinctrl-names = "default", "state_uhs";
 319                 pinctrl-0 = <&sdhci_pins>;
 320                 pinctrl-1 = <&sdhci_pins>;
 321
 322                 clocks = <&sysc MT7621_CLK_SHXC>,
 323                          <&sysc MT7621_CLK_50M>;
 324                 clock-names = "source", "hclk";
 325
 326                 interrupt-parent = <&gic>;
 327                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 328         };
 329
 330         xhci: xhci@1E1C0000 {
 331                 status = "okay";
 332
 333                 compatible = "mediatek,mt8173-xhci";
 334                 reg = <0x1e1c0000 0x1000
 335                        0x1e1d0700 0x0100>;
 336                 reg-names = "mac", "ippc";
 337
 338                 clocks = <&sysc MT7621_CLK_XTAL>;
 339                 clock-names = "sys_ck";
 340
 341                 interrupt-parent = <&gic>;
 342                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 343         };
 344
 345         gic: interrupt-controller@1fbc0000 {
 346                 compatible = "mti,gic";
 347                 reg = <0x1fbc0000 0x2000>;
 348
 349                 interrupt-controller;
 350                 #interrupt-cells = <3>;
 351
 352                 mti,reserved-cpu-vectors = <7>;
 353
 354                 timer {
 355                         compatible = "mti,gic-timer";
 356                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 357                         clocks = <&sysc MT7621_CLK_CPU>;
 358                 };
 359         };
 360
 361         nand: nand@1e003000 {
 362                 status = "disabled";
 363
 364                 compatible = "mediatek,mt7621-nand";
 365                 bank-width = <2>;
 366                 reg = <0x1e003000 0x800
 367                         0x1e003800 0x800>;
 368                 #address-cells = <1>;
 369                 #size-cells = <1>;
 370
 371                 clocks = <&sysc MT7621_CLK_NAND>;
 372                 clock-names = "nand";
 373         };
 374
 375         ethernet: ethernet@1e100000 {
 376                 compatible = "mediatek,mt7621-eth";
 377                 reg = <0x1e100000 0x10000>;
 378
 379                 clocks = <&sysc MT7621_CLK_FE>,
 380                          <&sysc MT7621_CLK_ETH>;
 381                 clock-names = "fe", "ethif";
 382
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385
 386                 resets = <&rstctrl 6 &rstctrl 23>;
 387                 reset-names = "fe", "eth";
 388
 389                 interrupt-parent = <&gic>;
 390                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 391
 392                 mediatek,ethsys = <&sysc>;
 393
 394
 395                 gmac0: mac@0 {
 396                         compatible = "mediatek,eth-mac";
 397                         reg = <0>;
 398                         phy-mode = "rgmii";
 399                         fixed-link {
 400                                 speed = <1000>;
 401                                 full-duplex;
 402                                 pause;
 403                         };
 404                 };
 405                 gmac1: mac@1 {
 406                         compatible = "mediatek,eth-mac";
 407                         reg = <1>;
 408                         status = "off";
 409                         phy-mode = "rgmii-rxid";
 410                         phy-handle = <&phy_external>;
 411                 };
 412                 mdio-bus {
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415
 416                         phy_external: ethernet-phy@5 {
 417                                 status = "off";
 418                                 reg = <5>;
 419                                 phy-mode = "rgmii-rxid";
 420
 421                                 pinctrl-names = "default";
 422                                 pinctrl-0 = <&rgmii2_pins>;
 423                         };
 424
 425                         switch0: switch0@0 {
 426                                 compatible = "mediatek,mt7621";
 427                                 #address-cells = <1>;
 428                                 #size-cells = <0>;
 429                                 reg = <0>;
 430                                 mediatek,mcm;
 431                                 resets = <&rstctrl 2>;
 432                                 reset-names = "mcm";
 433                                 interrupt-controller;
 434                                 #interrupt-cells = <1>;
 435                                 interrupt-parent = <&gic>;
 436                                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 437
 438                                 ports {
 439                                         #address-cells = <1>;
 440                                         #size-cells = <0>;
 441                                         reg = <0>;
 442                                         port@0 {
 443                                                 status = "off";
 444                                                 reg = <0>;
 445                                                 label = "lan0";
 446                                         };
 447                                         port@1 {
 448                                                 status = "off";
 449                                                 reg = <1>;
 450                                                 label = "lan1";
 451                                         };
 452                                         port@2 {
 453                                                 status = "off";
 454                                                 reg = <2>;
 455                                                 label = "lan2";
 456                                         };
 457                                         port@3 {
 458                                                 status = "off";
 459                                                 reg = <3>;
 460                                                 label = "lan3";
 461                                         };
 462                                         port@4 {
 463                                                 status = "off";
 464                                                 reg = <4>;
 465                                                 label = "lan4";
 466                                         };
 467                                         port@6 {
 468                                                 reg = <6>;
 469                                                 label = "cpu";
 470                                                 ethernet = <&gmac0>;
 471                                                 phy-mode = "trgmii";
 472                                                 fixed-link {
 473                                                         speed = <1000>;
 474                                                         full-duplex;
 475                                                 };
 476                                         };
 477                                 };
 478                         };
 479                 };
 480         };
 481
 482         pcie: pcie@1e140000 {
 483                 compatible = "mediatek,mt7621-pci";
 484                 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
 485                       <0x1e142000 0x100>, /* pcie port 0 RC control registers */
 486                       <0x1e143000 0x100>, /* pcie port 1 RC control registers */
 487                       <0x1e144000 0x100>; /* pcie port 2 RC control registers */
 488                 #address-cells = <3>;
 489                 #size-cells = <2>;
 490
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&pcie_pins>;
 493
 494                 device_type = "pci";
 495
 496                 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
 497                          <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
 498
 499                 #interrupt-cells = <1>;
 500                 interrupt-map-mask = <0xF800 0 0 0>;
 501                 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
 502                                 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
 503                                 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 504
 505                 status = "disabled";
 506
 507                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 508
 509                 pcie@0,0 {
 510                         reg = <0x0000 0 0 0 0>;
 511                         #address-cells = <3>;
 512                         #size-cells = <2>;
 513                         device_type = "pci";
 514                         #interrupt-cells = <1>;
 515                         interrupt-map-mask = <0 0 0 0>;
 516                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 517                         resets = <&rstctrl 24>;
 518                         clocks = <&sysc MT7621_CLK_PCIE0>;
 519                         phys = <&pcie0_phy 1>;
 520                         phy-names = "pcie-phy0";
 521                         ranges;
 522                 };
 523
 524                 pcie@1,0 {
 525                         reg = <0x0800 0 0 0 0>;
 526                         #address-cells = <3>;
 527                         #size-cells = <2>;
 528                         device_type = "pci";
 529                         #interrupt-cells = <1>;
 530                         interrupt-map-mask = <0 0 0 0>;
 531                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 532                         resets = <&rstctrl 25>;
 533                         clocks = <&sysc MT7621_CLK_PCIE1>;
 534                         phys = <&pcie0_phy 1>;
 535                         phy-names = "pcie-phy1";
 536                         ranges;
 537                 };
 538
 539                 pcie@2,0 {
 540                         reg = <0x1000 0 0 0 0>;
 541                         #address-cells = <3>;
 542                         #size-cells = <2>;
 543                         device_type = "pci";
 544                         #interrupt-cells = <1>;
 545                         interrupt-map-mask = <0 0 0 0>;
 546                         interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 547                         resets = <&rstctrl 26>;
 548                         clocks = <&sysc MT7621_CLK_PCIE2>;
 549                         phys = <&pcie2_phy 0>;
 550                         phy-names = "pcie-phy2";
 551                         ranges;
 552                 };
 553         };
 554
 555         pcie0_phy: pcie-phy@1e149000 {
 556                 compatible = "mediatek,mt7621-pci-phy";
 557                 reg = <0x1e149000 0x0700>;
 558                 clocks = <&sysc MT7621_CLK_XTAL>;
 559                 #phy-cells = <1>;
 560         };
 561
 562         pcie2_phy: pcie-phy@1e14a000 {
 563                 compatible = "mediatek,mt7621-pci-phy";
 564                 reg = <0x1e14a000 0x0700>;
 565                 clocks = <&sysc MT7621_CLK_XTAL>;
 566                 #phy-cells = <1>;
 567         };
 568 };