drivers/staging/media/rockchip/vpu/rk3399_vpu_hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Rockchip VPU codec driver
   4  *
   5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6  *      Jeffy Chen <jeffy.chen@rock-chips.com>
   7  */
   8
   9 #include <linux/clk.h>
  10
  11 #include "rockchip_vpu.h"
  12 #include "rockchip_vpu_jpeg.h"
  13 #include "rk3399_vpu_regs.h"
  14
  15 #define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
  16
  17 /*
  18  * Supported formats.
  19  */
  20
  21 static const struct rockchip_vpu_fmt rk3399_vpu_enc_fmts[] = {
  22         {
  23                 .fourcc = V4L2_PIX_FMT_YUV420M,
  24                 .codec_mode = RK_VPU_MODE_NONE,
  25                 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
  26         },
  27         {
  28                 .fourcc = V4L2_PIX_FMT_NV12M,
  29                 .codec_mode = RK_VPU_MODE_NONE,
  30                 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
  31         },
  32         {
  33                 .fourcc = V4L2_PIX_FMT_YUYV,
  34                 .codec_mode = RK_VPU_MODE_NONE,
  35                 .enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
  36         },
  37         {
  38                 .fourcc = V4L2_PIX_FMT_UYVY,
  39                 .codec_mode = RK_VPU_MODE_NONE,
  40                 .enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
  41         },
  42         {
  43                 .fourcc = V4L2_PIX_FMT_JPEG,
  44                 .codec_mode = RK_VPU_MODE_JPEG_ENC,
  45                 .max_depth = 2,
  46                 .header_size = JPEG_HEADER_SIZE,
  47                 .frmsize = {
  48                         .min_width = 96,
  49                         .max_width = 8192,
  50                         .step_width = JPEG_MB_DIM,
  51                         .min_height = 32,
  52                         .max_height = 8192,
  53                         .step_height = JPEG_MB_DIM,
  54                 },
  55         },
  56 };
  57
  58 static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id)
  59 {
  60         struct rockchip_vpu_dev *vpu = dev_id;
  61         enum vb2_buffer_state state;
  62         u32 status, bytesused;
  63
  64         status = vepu_read(vpu, VEPU_REG_INTERRUPT);
  65         bytesused = vepu_read(vpu, VEPU_REG_STR_BUF_LIMIT) / 8;
  66         state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
  67                 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
  68
  69         vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
  70         vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
  71
  72         rockchip_vpu_irq_done(vpu, bytesused, state);
  73
  74         return IRQ_HANDLED;
  75 }
  76
  77 static int rk3399_vpu_hw_init(struct rockchip_vpu_dev *vpu)
  78 {
  79         /* Bump ACLK to max. possible freq. to improve performance. */
  80         clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
  81         return 0;
  82 }
  83
  84 static void rk3399_vpu_enc_reset(struct rockchip_vpu_ctx *ctx)
  85 {
  86         struct rockchip_vpu_dev *vpu = ctx->dev;
  87
  88         vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
  89         vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
  90         vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
  91 }
  92
  93 /*
  94  * Supported codec ops.
  95  */
  96
  97 static const struct rockchip_vpu_codec_ops rk3399_vpu_codec_ops[] = {
  98         [RK_VPU_MODE_JPEG_ENC] = {
  99                 .run = rk3399_vpu_jpeg_enc_run,
 100                 .reset = rk3399_vpu_enc_reset,
 101         },
 102 };
 103
 104 /*
 105  * VPU variant.
 106  */
 107
 108 const struct rockchip_vpu_variant rk3399_vpu_variant = {
 109         .enc_offset = 0x0,
 110         .enc_fmts = rk3399_vpu_enc_fmts,
 111         .num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),
 112         .codec = RK_VPU_CODEC_JPEG,
 113         .codec_ops = rk3399_vpu_codec_ops,
 114         .vepu_irq = rk3399_vepu_irq,
 115         .init = rk3399_vpu_hw_init,
 116         .clk_names = {"aclk", "hclk"},
 117         .num_clocks = 2
 118 };