1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver
5 * Copyright (C) 2019 Linaro Ltd
6 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_graph.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/reset.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-subdev.h>
32 #include "imx-media.h"
34 #define CSIS_DRIVER_NAME "imx7-mipi-csis"
35 #define CSIS_SUBDEV_NAME CSIS_DRIVER_NAME
37 #define CSIS_PAD_SINK 0
38 #define CSIS_PAD_SOURCE 1
39 #define CSIS_PADS_NUM 2
41 #define MIPI_CSIS_DEF_PIX_WIDTH 640
42 #define MIPI_CSIS_DEF_PIX_HEIGHT 480
44 /* Register map definition */
46 /* CSIS common control */
47 #define MIPI_CSIS_CMN_CTRL 0x04
48 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
49 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
50 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
51 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
52 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
54 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
55 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
57 /* CSIS clock control */
58 #define MIPI_CSIS_CLK_CTRL 0x08
59 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
60 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
61 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
62 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
63 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4)
64 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
66 /* CSIS Interrupt mask */
67 #define MIPI_CSIS_INTMSK 0x10
68 #define MIPI_CSIS_INTMSK_EVEN_BEFORE BIT(31)
69 #define MIPI_CSIS_INTMSK_EVEN_AFTER BIT(30)
70 #define MIPI_CSIS_INTMSK_ODD_BEFORE BIT(29)
71 #define MIPI_CSIS_INTMSK_ODD_AFTER BIT(28)
72 #define MIPI_CSIS_INTMSK_FRAME_START BIT(24)
73 #define MIPI_CSIS_INTMSK_FRAME_END BIT(20)
74 #define MIPI_CSIS_INTMSK_ERR_SOT_HS BIT(16)
75 #define MIPI_CSIS_INTMSK_ERR_LOST_FS BIT(12)
76 #define MIPI_CSIS_INTMSK_ERR_LOST_FE BIT(8)
77 #define MIPI_CSIS_INTMSK_ERR_OVER BIT(4)
78 #define MIPI_CSIS_INTMSK_ERR_WRONG_CFG BIT(3)
79 #define MIPI_CSIS_INTMSK_ERR_ECC BIT(2)
80 #define MIPI_CSIS_INTMSK_ERR_CRC BIT(1)
81 #define MIPI_CSIS_INTMSK_ERR_UNKNOWN BIT(0)
83 /* CSIS Interrupt source */
84 #define MIPI_CSIS_INTSRC 0x14
85 #define MIPI_CSIS_INTSRC_EVEN_BEFORE BIT(31)
86 #define MIPI_CSIS_INTSRC_EVEN_AFTER BIT(30)
87 #define MIPI_CSIS_INTSRC_EVEN BIT(30)
88 #define MIPI_CSIS_INTSRC_ODD_BEFORE BIT(29)
89 #define MIPI_CSIS_INTSRC_ODD_AFTER BIT(28)
90 #define MIPI_CSIS_INTSRC_ODD (0x3 << 28)
91 #define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
92 #define MIPI_CSIS_INTSRC_FRAME_START BIT(24)
93 #define MIPI_CSIS_INTSRC_FRAME_END BIT(20)
94 #define MIPI_CSIS_INTSRC_ERR_SOT_HS BIT(16)
95 #define MIPI_CSIS_INTSRC_ERR_LOST_FS BIT(12)
96 #define MIPI_CSIS_INTSRC_ERR_LOST_FE BIT(8)
97 #define MIPI_CSIS_INTSRC_ERR_OVER BIT(4)
98 #define MIPI_CSIS_INTSRC_ERR_WRONG_CFG BIT(3)
99 #define MIPI_CSIS_INTSRC_ERR_ECC BIT(2)
100 #define MIPI_CSIS_INTSRC_ERR_CRC BIT(1)
101 #define MIPI_CSIS_INTSRC_ERR_UNKNOWN BIT(0)
102 #define MIPI_CSIS_INTSRC_ERRORS 0xfffff
104 /* D-PHY status control */
105 #define MIPI_CSIS_DPHYSTATUS 0x20
106 #define MIPI_CSIS_DPHYSTATUS_ULPS_DAT BIT(8)
107 #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT BIT(4)
108 #define MIPI_CSIS_DPHYSTATUS_ULPS_CLK BIT(1)
109 #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK BIT(0)
111 /* D-PHY common control */
112 #define MIPI_CSIS_DPHYCTRL 0x24
113 #define MIPI_CSIS_DPHYCTRL_HSS_MASK (0xff << 24)
114 #define MIPI_CSIS_DPHYCTRL_HSS_OFFSET 24
115 #define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22)
116 #define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22
117 #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK BIT(6)
118 #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT BIT(5)
119 #define MIPI_CSIS_DPHYCTRL_ENABLE_DAT BIT(1)
120 #define MIPI_CSIS_DPHYCTRL_ENABLE_CLK BIT(0)
121 #define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0)
123 /* D-PHY Master and Slave Control register Low */
124 #define MIPI_CSIS_DPHYBCTRL_L 0x30
125 /* D-PHY Master and Slave Control register High */
126 #define MIPI_CSIS_DPHYBCTRL_H 0x34
127 /* D-PHY Slave Control register Low */
128 #define MIPI_CSIS_DPHYSCTRL_L 0x38
129 /* D-PHY Slave Control register High */
130 #define MIPI_CSIS_DPHYSCTRL_H 0x3c
132 /* ISP Configuration register */
133 #define MIPI_CSIS_ISPCONFIG_CH0 0x40
134 #define MIPI_CSIS_ISPCONFIG_CH1 0x50
135 #define MIPI_CSIS_ISPCONFIG_CH2 0x60
136 #define MIPI_CSIS_ISPCONFIG_CH3 0x70
138 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
139 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
140 #define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT BIT(12)
141 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
142 #define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT (0x1e << 2)
143 #define MIPI_CSIS_ISPCFG_FMT_RAW8 (0x2a << 2)
144 #define MIPI_CSIS_ISPCFG_FMT_RAW10 (0x2b << 2)
145 #define MIPI_CSIS_ISPCFG_FMT_RAW12 (0x2c << 2)
147 /* User defined formats, x = 1...4 */
148 #define MIPI_CSIS_ISPCFG_FMT_USER(x) ((0x30 + (x) - 1) << 2)
149 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
151 /* ISP Image Resolution register */
152 #define MIPI_CSIS_ISPRESOL_CH0 0x44
153 #define MIPI_CSIS_ISPRESOL_CH1 0x54
154 #define MIPI_CSIS_ISPRESOL_CH2 0x64
155 #define MIPI_CSIS_ISPRESOL_CH3 0x74
156 #define CSIS_MAX_PIX_WIDTH 0xffff
157 #define CSIS_MAX_PIX_HEIGHT 0xffff
159 /* ISP SYNC register */
160 #define MIPI_CSIS_ISPSYNC_CH0 0x48
161 #define MIPI_CSIS_ISPSYNC_CH1 0x58
162 #define MIPI_CSIS_ISPSYNC_CH2 0x68
163 #define MIPI_CSIS_ISPSYNC_CH3 0x78
165 #define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18
166 #define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12
167 #define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0
169 /* Non-image packet data buffers */
170 #define MIPI_CSIS_PKTDATA_ODD 0x2000
171 #define MIPI_CSIS_PKTDATA_EVEN 0x3000
172 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K
174 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
182 struct mipi_csis_event {
184 const char * const name;
185 unsigned int counter;
188 static const struct mipi_csis_event mipi_csis_events[] = {
190 { MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
191 { MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
192 { MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
193 { MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
194 { MIPI_CSIS_INTSRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
195 { MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error" },
196 { MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error" },
197 { MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
198 /* Non-image data receive events */
199 { MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
200 { MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
201 { MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
202 { MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
203 /* Frame start/end */
204 { MIPI_CSIS_INTSRC_FRAME_START, "Frame Start" },
205 { MIPI_CSIS_INTSRC_FRAME_END, "Frame End" },
208 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
210 static const char * const mipi_csis_clk_id[] = {"pclk", "wrap", "phy"};
212 struct csis_hw_reset {
219 /* lock elements below */
221 /* lock for event handler */
224 struct media_pad pads[CSIS_PADS_NUM];
225 struct v4l2_subdev mipi_sd;
226 struct v4l2_subdev *src_sd;
229 struct platform_device *pdev;
232 struct clk *wrap_clk;
236 struct dentry *debugfs_root;
240 struct clk_bulk_data *clks;
245 struct reset_control *mrst;
247 const struct csis_pix_format *csis_fmt;
248 struct v4l2_mbus_framefmt format_mbus;
250 struct v4l2_fwnode_bus_mipi_csi2 bus;
252 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
254 struct v4l2_async_notifier subdev_notifier;
256 struct csis_hw_reset hw_reset;
257 struct regulator *mipi_phy_regulator;
261 struct csis_pix_format {
262 unsigned int pix_width_alignment;
268 static const struct csis_pix_format mipi_csis_formats[] = {
270 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
271 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
272 .data_alignment = 16,
274 .code = MEDIA_BUS_FMT_VYUY8_2X8,
275 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
276 .data_alignment = 16,
278 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
279 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
282 .code = MEDIA_BUS_FMT_YUYV8_2X8,
283 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
284 .data_alignment = 16,
288 #define mipi_csis_write(__csis, __r, __v) writel(__v, (__csis)->regs + (__r))
289 #define mipi_csis_read(__csis, __r) readl((__csis)->regs + (__r))
291 static int mipi_csis_dump_regs(struct csi_state *state)
293 struct device *dev = &state->pdev->dev;
296 static const struct {
298 const char * const name;
301 { 0x24, "DPHYCTRL" },
305 { 0x40, "CONFIG_CH0" },
306 { 0xC0, "DBG_CONFIG" },
307 { 0x38, "DPHYSLAVE_L" },
308 { 0x3C, "DPHYSLAVE_H" },
311 dev_info(dev, "--- REGISTERS ---\n");
313 for (i = 0; i < ARRAY_SIZE(registers); i++) {
314 cfg = mipi_csis_read(state, registers[i].offset);
315 dev_info(dev, "%12s: 0x%08x\n", registers[i].name, cfg);
321 static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
323 return container_of(sdev, struct csi_state, mipi_sd);
326 static const struct csis_pix_format *find_csis_format(u32 code)
330 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
331 if (code == mipi_csis_formats[i].code)
332 return &mipi_csis_formats[i];
336 static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
338 mipi_csis_write(state, MIPI_CSIS_INTMSK, on ? 0xffffffff : 0);
341 static void mipi_csis_sw_reset(struct csi_state *state)
343 u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
345 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
346 val | MIPI_CSIS_CMN_CTRL_RESET);
347 usleep_range(10, 20);
350 static int mipi_csis_phy_init(struct csi_state *state)
352 state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
353 if (IS_ERR(state->mipi_phy_regulator))
354 return PTR_ERR(state->mipi_phy_regulator);
356 return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
360 static void mipi_csis_phy_reset(struct csi_state *state)
362 reset_control_assert(state->mrst);
366 reset_control_deassert(state->mrst);
369 static void mipi_csis_system_enable(struct csi_state *state, int on)
373 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
375 val |= MIPI_CSIS_CMN_CTRL_ENABLE;
377 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
378 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
380 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
381 val &= ~MIPI_CSIS_DPHYCTRL_ENABLE;
383 mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
384 val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE);
386 mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
389 /* Called with the state.lock mutex held */
390 static void __mipi_csis_set_format(struct csi_state *state)
392 struct v4l2_mbus_framefmt *mf = &state->format_mbus;
396 val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
397 val = (val & ~MIPI_CSIS_ISPCFG_FMT_MASK) | state->csis_fmt->fmt_reg;
398 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
400 /* Pixel resolution */
401 val = mf->width | (mf->height << 16);
402 mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);
405 static void mipi_csis_set_hsync_settle(struct csi_state *state, int hs_settle)
407 u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
409 val = ((val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (hs_settle << 24));
411 mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
414 static void mipi_csis_set_params(struct csi_state *state)
416 int lanes = state->bus.num_data_lanes;
419 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
420 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
421 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
422 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
424 __mipi_csis_set_format(state);
426 mipi_csis_set_hsync_settle(state, state->hs_settle);
428 val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
429 if (state->csis_fmt->data_alignment == 32)
430 val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT;
432 val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT;
433 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
435 val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
436 (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
437 (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);
438 mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val);
440 val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
441 val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
443 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
445 val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
447 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
448 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
449 mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
451 mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_L, 0x1f4);
452 mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_H, 0);
454 /* Update the shadow register. */
455 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
456 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
457 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
458 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
461 static int mipi_csis_clk_enable(struct csi_state *state)
463 return clk_bulk_prepare_enable(state->num_clks, state->clks);
466 static void mipi_csis_clk_disable(struct csi_state *state)
468 clk_bulk_disable_unprepare(state->num_clks, state->clks);
471 static int mipi_csis_clk_get(struct csi_state *state)
473 struct device *dev = &state->pdev->dev;
477 state->num_clks = ARRAY_SIZE(mipi_csis_clk_id);
478 state->clks = devm_kcalloc(dev, state->num_clks, sizeof(*state->clks),
484 for (i = 0; i < state->num_clks; i++)
485 state->clks[i].id = mipi_csis_clk_id[i];
487 ret = devm_clk_bulk_get(dev, state->num_clks, state->clks);
491 state->wrap_clk = devm_clk_get(dev, "wrap");
492 if (IS_ERR(state->wrap_clk))
493 return PTR_ERR(state->wrap_clk);
496 ret = clk_set_rate(state->wrap_clk, state->clk_frequency);
498 dev_err(dev, "set rate=%d failed: %d\n", state->clk_frequency,
504 static void mipi_csis_start_stream(struct csi_state *state)
506 mipi_csis_sw_reset(state);
507 mipi_csis_set_params(state);
508 mipi_csis_system_enable(state, true);
509 mipi_csis_enable_interrupts(state, true);
512 static void mipi_csis_stop_stream(struct csi_state *state)
514 mipi_csis_enable_interrupts(state, false);
515 mipi_csis_system_enable(state, false);
518 static void mipi_csis_clear_counters(struct csi_state *state)
523 spin_lock_irqsave(&state->slock, flags);
524 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
525 state->events[i].counter = 0;
526 spin_unlock_irqrestore(&state->slock, flags);
529 static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
531 int i = non_errors ? MIPI_CSIS_NUM_EVENTS : MIPI_CSIS_NUM_EVENTS - 4;
532 struct device *dev = &state->pdev->dev;
535 spin_lock_irqsave(&state->slock, flags);
537 for (i--; i >= 0; i--) {
538 if (state->events[i].counter > 0 || state->debug)
539 dev_info(dev, "%s events: %d\n", state->events[i].name,
540 state->events[i].counter);
542 spin_unlock_irqrestore(&state->slock, flags);
546 * V4L2 subdev operations
548 static int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable)
550 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
554 mipi_csis_clear_counters(state);
555 ret = pm_runtime_get_sync(&state->pdev->dev);
557 pm_runtime_put_noidle(&state->pdev->dev);
560 ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
565 mutex_lock(&state->lock);
567 if (state->flags & ST_SUSPENDED) {
572 mipi_csis_start_stream(state);
573 ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
577 mipi_csis_log_counters(state, true);
579 state->flags |= ST_STREAMING;
581 v4l2_subdev_call(state->src_sd, video, s_stream, 0);
582 ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
583 mipi_csis_stop_stream(state);
584 state->flags &= ~ST_STREAMING;
586 mipi_csis_log_counters(state, true);
590 mutex_unlock(&state->lock);
592 pm_runtime_put(&state->pdev->dev);
597 static int mipi_csis_link_setup(struct media_entity *entity,
598 const struct media_pad *local_pad,
599 const struct media_pad *remote_pad, u32 flags)
601 struct v4l2_subdev *mipi_sd = media_entity_to_v4l2_subdev(entity);
602 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
603 struct v4l2_subdev *remote_sd;
606 dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
607 local_pad->entity->name);
609 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
611 mutex_lock(&state->lock);
613 if (local_pad->flags & MEDIA_PAD_FL_SOURCE) {
614 if (flags & MEDIA_LNK_FL_ENABLED) {
615 if (state->sink_linked) {
619 state->sink_linked = true;
621 state->sink_linked = false;
624 if (flags & MEDIA_LNK_FL_ENABLED) {
629 state->src_sd = remote_sd;
631 state->src_sd = NULL;
636 mutex_unlock(&state->lock);
640 static int mipi_csis_init_cfg(struct v4l2_subdev *mipi_sd,
641 struct v4l2_subdev_pad_config *cfg)
643 struct v4l2_mbus_framefmt *mf;
647 for (i = 0; i < CSIS_PADS_NUM; i++) {
648 mf = v4l2_subdev_get_try_format(mipi_sd, cfg, i);
650 ret = imx_media_init_mbus_fmt(mf, MIPI_CSIS_DEF_PIX_HEIGHT,
651 MIPI_CSIS_DEF_PIX_WIDTH, 0,
652 V4L2_FIELD_NONE, NULL);
660 static struct csis_pix_format const *
661 mipi_csis_try_format(struct v4l2_subdev *mipi_sd, struct v4l2_mbus_framefmt *mf)
663 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
664 struct csis_pix_format const *csis_fmt;
666 csis_fmt = find_csis_format(mf->code);
668 csis_fmt = &mipi_csis_formats[0];
670 v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
671 csis_fmt->pix_width_alignment,
672 &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
675 state->format_mbus.code = csis_fmt->code;
676 state->format_mbus.width = mf->width;
677 state->format_mbus.height = mf->height;
682 static struct v4l2_mbus_framefmt *
683 mipi_csis_get_format(struct csi_state *state,
684 struct v4l2_subdev_pad_config *cfg,
685 enum v4l2_subdev_format_whence which,
688 if (which == V4L2_SUBDEV_FORMAT_TRY)
689 return v4l2_subdev_get_try_format(&state->mipi_sd, cfg, pad);
691 return &state->format_mbus;
694 static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd,
695 struct v4l2_subdev_pad_config *cfg,
696 struct v4l2_subdev_format *sdformat)
698 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
699 struct csis_pix_format const *csis_fmt;
700 struct v4l2_mbus_framefmt *fmt;
702 if (sdformat->pad >= CSIS_PADS_NUM)
705 fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
707 mutex_lock(&state->lock);
708 if (sdformat->pad == CSIS_PAD_SOURCE) {
709 sdformat->format = *fmt;
713 csis_fmt = mipi_csis_try_format(mipi_sd, &sdformat->format);
715 sdformat->format = *fmt;
717 if (csis_fmt && sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
718 state->csis_fmt = csis_fmt;
720 cfg->try_fmt = sdformat->format;
723 mutex_unlock(&state->lock);
728 static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd,
729 struct v4l2_subdev_pad_config *cfg,
730 struct v4l2_subdev_format *sdformat)
732 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
733 struct v4l2_mbus_framefmt *fmt;
735 mutex_lock(&state->lock);
737 fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
739 sdformat->format = *fmt;
741 mutex_unlock(&state->lock);
746 static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd)
748 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
750 mutex_lock(&state->lock);
751 mipi_csis_log_counters(state, true);
752 if (state->debug && (state->flags & ST_POWERED))
753 mipi_csis_dump_regs(state);
754 mutex_unlock(&state->lock);
759 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
761 struct csi_state *state = dev_id;
766 status = mipi_csis_read(state, MIPI_CSIS_INTSRC);
768 spin_lock_irqsave(&state->slock, flags);
770 /* Update the event/error counters */
771 if ((status & MIPI_CSIS_INTSRC_ERRORS) || state->debug) {
772 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
773 if (!(status & state->events[i].mask))
775 state->events[i].counter++;
778 spin_unlock_irqrestore(&state->slock, flags);
780 mipi_csis_write(state, MIPI_CSIS_INTSRC, status);
785 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
786 .log_status = mipi_csis_log_status,
789 static const struct media_entity_operations mipi_csis_entity_ops = {
790 .link_setup = mipi_csis_link_setup,
791 .link_validate = v4l2_subdev_link_validate,
794 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
795 .s_stream = mipi_csis_s_stream,
798 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
799 .init_cfg = mipi_csis_init_cfg,
800 .get_fmt = mipi_csis_get_fmt,
801 .set_fmt = mipi_csis_set_fmt,
804 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
805 .core = &mipi_csis_core_ops,
806 .video = &mipi_csis_video_ops,
807 .pad = &mipi_csis_pad_ops,
810 static int mipi_csis_parse_dt(struct platform_device *pdev,
811 struct csi_state *state)
813 struct device_node *node = pdev->dev.of_node;
815 if (of_property_read_u32(node, "clock-frequency",
816 &state->clk_frequency))
817 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
819 /* Get MIPI PHY resets */
820 state->mrst = devm_reset_control_get_exclusive(&pdev->dev, "mrst");
821 if (IS_ERR(state->mrst))
822 return PTR_ERR(state->mrst);
824 /* Get MIPI CSI-2 bus configuration from the endpoint node. */
825 of_property_read_u32(node, "fsl,csis-hs-settle", &state->hs_settle);
830 static int mipi_csis_pm_resume(struct device *dev, bool runtime);
832 static int mipi_csis_parse_endpoint(struct device *dev,
833 struct v4l2_fwnode_endpoint *ep,
834 struct v4l2_async_subdev *asd)
836 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
837 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
839 if (ep->bus_type != V4L2_MBUS_CSI2_DPHY) {
840 dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
844 state->bus = ep->bus.mipi_csi2;
846 dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
847 dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
852 static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd,
853 struct platform_device *pdev,
854 const struct v4l2_subdev_ops *ops)
856 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
857 unsigned int sink_port = 0;
860 v4l2_subdev_init(mipi_sd, ops);
861 mipi_sd->owner = THIS_MODULE;
862 snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d",
863 CSIS_SUBDEV_NAME, state->index);
865 mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
866 mipi_sd->ctrl_handler = NULL;
868 mipi_sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
869 mipi_sd->entity.ops = &mipi_csis_entity_ops;
871 mipi_sd->dev = &pdev->dev;
873 state->csis_fmt = &mipi_csis_formats[0];
874 state->format_mbus.code = mipi_csis_formats[0].code;
875 state->format_mbus.width = MIPI_CSIS_DEF_PIX_WIDTH;
876 state->format_mbus.height = MIPI_CSIS_DEF_PIX_HEIGHT;
877 state->format_mbus.field = V4L2_FIELD_NONE;
879 v4l2_set_subdevdata(mipi_sd, &pdev->dev);
881 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
882 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
883 ret = media_entity_pads_init(&mipi_sd->entity, CSIS_PADS_NUM,
888 ret = v4l2_async_register_fwnode_subdev(mipi_sd,
889 sizeof(struct v4l2_async_subdev),
891 mipi_csis_parse_endpoint);
893 dev_err(&pdev->dev, "async fwnode register failed: %d\n", ret);
898 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
900 struct csi_state *state = m->private;
902 return mipi_csis_dump_regs(state);
904 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
906 static int mipi_csis_debugfs_init(struct csi_state *state)
910 if (!debugfs_initialized())
913 state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
914 if (!state->debugfs_root)
917 d = debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
922 d = debugfs_create_file("dump_regs", 0600, state->debugfs_root,
923 state, &mipi_csis_dump_regs_fops);
930 debugfs_remove_recursive(state->debugfs_root);
935 static void mipi_csis_debugfs_exit(struct csi_state *state)
937 debugfs_remove_recursive(state->debugfs_root);
940 static int mipi_csis_probe(struct platform_device *pdev)
942 struct device *dev = &pdev->dev;
943 struct csi_state *state;
946 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
950 spin_lock_init(&state->slock);
955 ret = mipi_csis_parse_dt(pdev, state);
957 dev_err(dev, "Failed to parse device tree: %d\n", ret);
961 ret = mipi_csis_phy_init(state);
965 mipi_csis_phy_reset(state);
967 state->regs = devm_platform_ioremap_resource(pdev, 0);
968 if (IS_ERR(state->regs))
969 return PTR_ERR(state->regs);
971 state->irq = platform_get_irq(pdev, 0);
975 ret = mipi_csis_clk_get(state);
979 ret = mipi_csis_clk_enable(state);
981 dev_err(state->dev, "failed to enable clocks: %d\n", ret);
985 ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler,
986 0, dev_name(dev), state);
988 dev_err(dev, "Interrupt request failed\n");
992 platform_set_drvdata(pdev, &state->mipi_sd);
994 mutex_init(&state->lock);
995 ret = mipi_csis_subdev_init(&state->mipi_sd, pdev,
996 &mipi_csis_subdev_ops);
1000 memcpy(state->events, mipi_csis_events, sizeof(state->events));
1002 mipi_csis_debugfs_init(state);
1003 pm_runtime_enable(dev);
1004 if (!pm_runtime_enabled(dev)) {
1005 ret = mipi_csis_pm_resume(dev, true);
1007 goto unregister_all;
1010 dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
1011 state->bus.num_data_lanes, state->hs_settle,
1012 state->wrap_clk ? 1 : 0, state->clk_frequency);
1017 mipi_csis_debugfs_exit(state);
1018 media_entity_cleanup(&state->mipi_sd.entity);
1019 v4l2_async_unregister_subdev(&state->mipi_sd);
1021 mipi_csis_clk_disable(state);
1022 mutex_destroy(&state->lock);
1027 static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
1029 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1030 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1033 mutex_lock(&state->lock);
1034 if (state->flags & ST_POWERED) {
1035 mipi_csis_stop_stream(state);
1036 ret = regulator_disable(state->mipi_phy_regulator);
1039 mipi_csis_clk_disable(state);
1040 state->flags &= ~ST_POWERED;
1042 state->flags |= ST_SUSPENDED;
1046 mutex_unlock(&state->lock);
1048 return ret ? -EAGAIN : 0;
1051 static int mipi_csis_pm_resume(struct device *dev, bool runtime)
1053 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1054 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1057 mutex_lock(&state->lock);
1058 if (!runtime && !(state->flags & ST_SUSPENDED))
1061 if (!(state->flags & ST_POWERED)) {
1062 ret = regulator_enable(state->mipi_phy_regulator);
1066 state->flags |= ST_POWERED;
1067 mipi_csis_clk_enable(state);
1069 if (state->flags & ST_STREAMING)
1070 mipi_csis_start_stream(state);
1072 state->flags &= ~ST_SUSPENDED;
1075 mutex_unlock(&state->lock);
1077 return ret ? -EAGAIN : 0;
1080 static int __maybe_unused mipi_csis_suspend(struct device *dev)
1082 return mipi_csis_pm_suspend(dev, false);
1085 static int __maybe_unused mipi_csis_resume(struct device *dev)
1087 return mipi_csis_pm_resume(dev, false);
1090 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1092 return mipi_csis_pm_suspend(dev, true);
1095 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1097 return mipi_csis_pm_resume(dev, true);
1100 static int mipi_csis_remove(struct platform_device *pdev)
1102 struct v4l2_subdev *mipi_sd = platform_get_drvdata(pdev);
1103 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1105 mipi_csis_debugfs_exit(state);
1106 v4l2_async_unregister_subdev(&state->mipi_sd);
1107 v4l2_async_notifier_unregister(&state->subdev_notifier);
1109 pm_runtime_disable(&pdev->dev);
1110 mipi_csis_pm_suspend(&pdev->dev, true);
1111 mipi_csis_clk_disable(state);
1112 media_entity_cleanup(&state->mipi_sd.entity);
1113 mutex_destroy(&state->lock);
1114 pm_runtime_set_suspended(&pdev->dev);
1119 static const struct dev_pm_ops mipi_csis_pm_ops = {
1120 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1122 SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
1125 static const struct of_device_id mipi_csis_of_match[] = {
1126 { .compatible = "fsl,imx7-mipi-csi2", },
1129 MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1131 static struct platform_driver mipi_csis_driver = {
1132 .probe = mipi_csis_probe,
1133 .remove = mipi_csis_remove,
1135 .of_match_table = mipi_csis_of_match,
1136 .name = CSIS_DRIVER_NAME,
1137 .pm = &mipi_csis_pm_ops,
1141 module_platform_driver(mipi_csis_driver);
1143 MODULE_DESCRIPTION("i.MX7 MIPI CSI-2 Receiver driver");
1144 MODULE_LICENSE("GPL v2");
1145 MODULE_ALIAS("platform:imx7-mipi-csi2");