1 // SPDX-License-Identifier: GPL-2.0+
3 * MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC.
5 * Copyright (c) 2012-2017 Mentor Graphics Inc.
8 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
13 #include <linux/of_graph.h>
14 #include <linux/platform_device.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-mc.h>
18 #include <media/v4l2-subdev.h>
19 #include "imx-media.h"
22 * there must be 5 pads: 1 input pad from sensor, and
23 * the 4 virtual channel output pads
25 #define CSI2_SINK_PAD 0
26 #define CSI2_NUM_SINK_PADS 1
27 #define CSI2_NUM_SRC_PADS 4
28 #define CSI2_NUM_PADS 5
31 * The default maximum bit-rate per lane in Mbps, if the
32 * source subdev does not provide V4L2_CID_LINK_FREQ.
34 #define CSI2_DEFAULT_MAX_MBPS 849
38 struct v4l2_subdev sd;
39 struct v4l2_async_notifier notifier;
40 struct media_pad pad[CSI2_NUM_PADS];
42 struct clk *pllref_clk;
43 struct clk *pix_clk; /* what is this? */
46 struct v4l2_subdev *remote;
47 unsigned int remote_pad;
48 unsigned short data_lanes;
50 /* lock to protect all members below */
53 struct v4l2_mbus_framefmt format_mbus;
56 struct v4l2_subdev *src_sd;
57 bool sink_linked[CSI2_NUM_SRC_PADS];
60 #define DEVICE_NAME "imx6-mipi-csi2"
62 /* Register offsets */
63 #define CSI2_VERSION 0x000
64 #define CSI2_N_LANES 0x004
65 #define CSI2_PHY_SHUTDOWNZ 0x008
66 #define CSI2_DPHY_RSTZ 0x00c
67 #define CSI2_RESETN 0x010
68 #define CSI2_PHY_STATE 0x014
69 #define PHY_STOPSTATEDATA_BIT 4
70 #define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n))
71 #define PHY_RXCLKACTIVEHS BIT(8)
72 #define PHY_RXULPSCLKNOT BIT(9)
73 #define PHY_STOPSTATECLK BIT(10)
74 #define CSI2_DATA_IDS_1 0x018
75 #define CSI2_DATA_IDS_2 0x01c
76 #define CSI2_ERR1 0x020
77 #define CSI2_ERR2 0x024
78 #define CSI2_MSK1 0x028
79 #define CSI2_MSK2 0x02c
80 #define CSI2_PHY_TST_CTRL0 0x030
81 #define PHY_TESTCLR BIT(0)
82 #define PHY_TESTCLK BIT(1)
83 #define CSI2_PHY_TST_CTRL1 0x034
84 #define PHY_TESTEN BIT(16)
86 * i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is
87 * not part of the MIPI CSI-2 core, but its registers fall in the
88 * same register map range.
90 #define CSI2IPU_GASKET 0xf00
91 #define CSI2IPU_YUV422_YUYV BIT(2)
93 static inline struct csi2_dev *sd_to_dev(struct v4l2_subdev *sdev)
95 return container_of(sdev, struct csi2_dev, sd);
98 static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n)
100 return container_of(n, struct csi2_dev, notifier);
104 * The required sequence of MIPI CSI-2 startup as specified in the i.MX6
105 * reference manual is as follows:
107 * 1. Deassert presetn signal (global reset).
108 * It's not clear what this "global reset" signal is (maybe APB
109 * global reset), but in any case this step would be probably
110 * be carried out during driver load in csi2_probe().
112 * 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state.
113 * This must be carried out by the MIPI sensor's s_power(ON) subdev
116 * 3. D-PHY initialization.
117 * 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ,
118 * deassert PHY_RSTZ, deassert CSI2_RESETN).
119 * 5. Read the PHY status register (PHY_STATE) to confirm that all data and
120 * clock lanes of the D-PHY are in LP-11 state.
121 * 6. Configure the MIPI Camera Sensor to start transmitting a clock on the
123 * 7. CSI2 Controller programming - Read the PHY status register (PHY_STATE)
124 * to confirm that the D-PHY is receiving a clock on the D-PHY clock lane.
126 * All steps 3 through 7 are carried out by csi2_s_stream(ON) here. Step
127 * 6 is accomplished by calling the source subdev's s_stream(ON) between
131 static void csi2_enable(struct csi2_dev *csi2, bool enable)
134 writel(0x1, csi2->base + CSI2_PHY_SHUTDOWNZ);
135 writel(0x1, csi2->base + CSI2_DPHY_RSTZ);
136 writel(0x1, csi2->base + CSI2_RESETN);
138 writel(0x0, csi2->base + CSI2_PHY_SHUTDOWNZ);
139 writel(0x0, csi2->base + CSI2_DPHY_RSTZ);
140 writel(0x0, csi2->base + CSI2_RESETN);
144 static void csi2_set_lanes(struct csi2_dev *csi2, unsigned int lanes)
146 writel(lanes - 1, csi2->base + CSI2_N_LANES);
149 static void dw_mipi_csi2_phy_write(struct csi2_dev *csi2,
150 u32 test_code, u32 test_data)
152 /* Clear PHY test interface */
153 writel(PHY_TESTCLR, csi2->base + CSI2_PHY_TST_CTRL0);
154 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL1);
155 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
157 /* Raise test interface strobe signal */
158 writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
160 /* Configure address write on falling edge and lower strobe signal */
161 writel(PHY_TESTEN | test_code, csi2->base + CSI2_PHY_TST_CTRL1);
162 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
164 /* Configure data write on rising edge and raise strobe signal */
165 writel(test_data, csi2->base + CSI2_PHY_TST_CTRL1);
166 writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
168 /* Clear strobe signal */
169 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
173 * This table is based on the table documented at
174 * https://community.nxp.com/docs/DOC-94312. It assumes
175 * a 27MHz D-PHY pll reference clock.
177 static const struct {
181 { 90, 0x00}, {100, 0x20}, {110, 0x40}, {125, 0x02},
182 {140, 0x22}, {150, 0x42}, {160, 0x04}, {180, 0x24},
183 {200, 0x44}, {210, 0x06}, {240, 0x26}, {250, 0x46},
184 {270, 0x08}, {300, 0x28}, {330, 0x48}, {360, 0x2a},
185 {400, 0x4a}, {450, 0x0c}, {500, 0x2c}, {550, 0x0e},
186 {600, 0x2e}, {650, 0x10}, {700, 0x30}, {750, 0x12},
187 {800, 0x32}, {850, 0x14}, {900, 0x34}, {950, 0x54},
191 static int max_mbps_to_hsfreqrange_sel(u32 max_mbps)
195 for (i = 0; i < ARRAY_SIZE(hsfreq_map); i++)
196 if (hsfreq_map[i].max_mbps > max_mbps)
197 return hsfreq_map[i].hsfreqrange_sel;
202 static int csi2_dphy_init(struct csi2_dev *csi2)
204 struct v4l2_ctrl *ctrl;
208 ctrl = v4l2_ctrl_find(csi2->src_sd->ctrl_handler,
211 mbps_per_lane = CSI2_DEFAULT_MAX_MBPS;
213 mbps_per_lane = DIV_ROUND_UP_ULL(2 * ctrl->qmenu_int[ctrl->val],
216 sel = max_mbps_to_hsfreqrange_sel(mbps_per_lane);
220 dw_mipi_csi2_phy_write(csi2, 0x44, sel);
226 * Waits for ultra-low-power state on D-PHY clock lane. This is currently
227 * unused and may not be needed at all, but keep around just in case.
229 static int __maybe_unused csi2_dphy_wait_ulp(struct csi2_dev *csi2)
234 /* wait for ULP on clock lane */
235 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
236 !(reg & PHY_RXULPSCLKNOT), 0, 500000);
238 v4l2_err(&csi2->sd, "ULP timeout, phy_state = 0x%08x\n", reg);
242 /* wait until no errors on bus */
243 ret = readl_poll_timeout(csi2->base + CSI2_ERR1, reg,
244 reg == 0x0, 0, 500000);
246 v4l2_err(&csi2->sd, "stable bus timeout, err1 = 0x%08x\n", reg);
253 /* Waits for low-power LP-11 state on data and clock lanes. */
254 static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2, unsigned int lanes)
259 mask = PHY_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STOPSTATEDATA_BIT);
261 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
262 (reg & mask) == mask, 0, 500000);
264 v4l2_warn(&csi2->sd, "LP-11 wait timeout, likely a sensor driver bug, expect capture failures.\n");
265 v4l2_warn(&csi2->sd, "phy_state = 0x%08x\n", reg);
269 /* Wait for active clock on the clock lane. */
270 static int csi2_dphy_wait_clock_lane(struct csi2_dev *csi2)
275 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
276 (reg & PHY_RXCLKACTIVEHS), 0, 500000);
278 v4l2_err(&csi2->sd, "clock lane timeout, phy_state = 0x%08x\n",
286 /* Setup the i.MX CSI2IPU Gasket */
287 static void csi2ipu_gasket_init(struct csi2_dev *csi2)
291 switch (csi2->format_mbus.code) {
292 case MEDIA_BUS_FMT_YUYV8_2X8:
293 case MEDIA_BUS_FMT_YUYV8_1X16:
294 reg = CSI2IPU_YUV422_YUYV;
300 writel(reg, csi2->base + CSI2IPU_GASKET);
303 static int csi2_get_active_lanes(struct csi2_dev *csi2, unsigned int *lanes)
305 struct v4l2_mbus_config mbus_config = { 0 };
306 unsigned int num_lanes = UINT_MAX;
309 *lanes = csi2->data_lanes;
311 ret = v4l2_subdev_call(csi2->remote, pad, get_mbus_config,
312 csi2->remote_pad, &mbus_config);
313 if (ret == -ENOIOCTLCMD) {
314 dev_dbg(csi2->dev, "No remote mbus configuration available\n");
319 dev_err(csi2->dev, "Failed to get remote mbus configuration\n");
323 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
324 dev_err(csi2->dev, "Unsupported media bus type %u\n",
329 switch (mbus_config.flags & V4L2_MBUS_CSI2_LANES) {
330 case V4L2_MBUS_CSI2_1_LANE:
333 case V4L2_MBUS_CSI2_2_LANE:
336 case V4L2_MBUS_CSI2_3_LANE:
339 case V4L2_MBUS_CSI2_4_LANE:
343 num_lanes = csi2->data_lanes;
347 if (num_lanes > csi2->data_lanes) {
349 "Unsupported mbus config: too many data lanes %u\n",
359 static int csi2_start(struct csi2_dev *csi2)
364 ret = clk_prepare_enable(csi2->pix_clk);
368 /* setup the gasket */
369 csi2ipu_gasket_init(csi2);
372 ret = csi2_dphy_init(csi2);
374 goto err_disable_clk;
376 ret = csi2_get_active_lanes(csi2, &lanes);
378 goto err_disable_clk;
381 csi2_set_lanes(csi2, lanes);
382 csi2_enable(csi2, true);
385 csi2_dphy_wait_stopstate(csi2, lanes);
388 ret = v4l2_subdev_call(csi2->src_sd, video, s_stream, 1);
389 ret = (ret && ret != -ENOIOCTLCMD) ? ret : 0;
391 goto err_assert_reset;
394 ret = csi2_dphy_wait_clock_lane(csi2);
396 goto err_stop_upstream;
401 v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
403 csi2_enable(csi2, false);
405 clk_disable_unprepare(csi2->pix_clk);
409 static void csi2_stop(struct csi2_dev *csi2)
412 v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
414 csi2_enable(csi2, false);
415 clk_disable_unprepare(csi2->pix_clk);
419 * V4L2 subdev operations.
422 static int csi2_s_stream(struct v4l2_subdev *sd, int enable)
424 struct csi2_dev *csi2 = sd_to_dev(sd);
427 mutex_lock(&csi2->lock);
434 for (i = 0; i < CSI2_NUM_SRC_PADS; i++) {
435 if (csi2->sink_linked[i])
438 if (i >= CSI2_NUM_SRC_PADS) {
444 * enable/disable streaming only if stream_count is
445 * going from 0 to 1 / 1 to 0.
447 if (csi2->stream_count != !enable)
450 dev_dbg(csi2->dev, "stream %s\n", enable ? "ON" : "OFF");
452 ret = csi2_start(csi2);
459 csi2->stream_count += enable ? 1 : -1;
460 if (csi2->stream_count < 0)
461 csi2->stream_count = 0;
463 mutex_unlock(&csi2->lock);
467 static int csi2_link_setup(struct media_entity *entity,
468 const struct media_pad *local,
469 const struct media_pad *remote, u32 flags)
471 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
472 struct csi2_dev *csi2 = sd_to_dev(sd);
473 struct v4l2_subdev *remote_sd;
476 dev_dbg(csi2->dev, "link setup %s -> %s", remote->entity->name,
477 local->entity->name);
479 remote_sd = media_entity_to_v4l2_subdev(remote->entity);
481 mutex_lock(&csi2->lock);
483 if (local->flags & MEDIA_PAD_FL_SOURCE) {
484 if (flags & MEDIA_LNK_FL_ENABLED) {
485 if (csi2->sink_linked[local->index - 1]) {
489 csi2->sink_linked[local->index - 1] = true;
491 csi2->sink_linked[local->index - 1] = false;
494 if (flags & MEDIA_LNK_FL_ENABLED) {
499 csi2->src_sd = remote_sd;
506 mutex_unlock(&csi2->lock);
510 static struct v4l2_mbus_framefmt *
511 __csi2_get_fmt(struct csi2_dev *csi2, struct v4l2_subdev_state *sd_state,
512 unsigned int pad, enum v4l2_subdev_format_whence which)
514 if (which == V4L2_SUBDEV_FORMAT_TRY)
515 return v4l2_subdev_get_try_format(&csi2->sd, sd_state, pad);
517 return &csi2->format_mbus;
520 static int csi2_get_fmt(struct v4l2_subdev *sd,
521 struct v4l2_subdev_state *sd_state,
522 struct v4l2_subdev_format *sdformat)
524 struct csi2_dev *csi2 = sd_to_dev(sd);
525 struct v4l2_mbus_framefmt *fmt;
527 mutex_lock(&csi2->lock);
529 fmt = __csi2_get_fmt(csi2, sd_state, sdformat->pad, sdformat->which);
531 sdformat->format = *fmt;
533 mutex_unlock(&csi2->lock);
538 static int csi2_set_fmt(struct v4l2_subdev *sd,
539 struct v4l2_subdev_state *sd_state,
540 struct v4l2_subdev_format *sdformat)
542 struct csi2_dev *csi2 = sd_to_dev(sd);
543 struct v4l2_mbus_framefmt *fmt;
546 if (sdformat->pad >= CSI2_NUM_PADS)
549 mutex_lock(&csi2->lock);
551 if (csi2->stream_count > 0) {
556 /* Output pads mirror active input pad, no limits on input pads */
557 if (sdformat->pad != CSI2_SINK_PAD)
558 sdformat->format = csi2->format_mbus;
560 fmt = __csi2_get_fmt(csi2, sd_state, sdformat->pad, sdformat->which);
562 *fmt = sdformat->format;
564 mutex_unlock(&csi2->lock);
568 static int csi2_registered(struct v4l2_subdev *sd)
570 struct csi2_dev *csi2 = sd_to_dev(sd);
572 /* set a default mbus format */
573 return imx_media_init_mbus_fmt(&csi2->format_mbus,
574 IMX_MEDIA_DEF_PIX_WIDTH,
575 IMX_MEDIA_DEF_PIX_HEIGHT, 0,
576 V4L2_FIELD_NONE, NULL);
579 static const struct media_entity_operations csi2_entity_ops = {
580 .link_setup = csi2_link_setup,
581 .link_validate = v4l2_subdev_link_validate,
582 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
585 static const struct v4l2_subdev_video_ops csi2_video_ops = {
586 .s_stream = csi2_s_stream,
589 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
590 .init_cfg = imx_media_init_cfg,
591 .get_fmt = csi2_get_fmt,
592 .set_fmt = csi2_set_fmt,
595 static const struct v4l2_subdev_ops csi2_subdev_ops = {
596 .video = &csi2_video_ops,
597 .pad = &csi2_pad_ops,
600 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
601 .registered = csi2_registered,
604 static int csi2_notify_bound(struct v4l2_async_notifier *notifier,
605 struct v4l2_subdev *sd,
606 struct v4l2_async_subdev *asd)
608 struct csi2_dev *csi2 = notifier_to_dev(notifier);
609 struct media_pad *sink = &csi2->sd.entity.pads[CSI2_SINK_PAD];
612 pad = media_entity_get_fwnode_pad(&sd->entity, asd->match.fwnode,
613 MEDIA_PAD_FL_SOURCE);
615 dev_err(csi2->dev, "Failed to find pad for %s\n", sd->name);
620 csi2->remote_pad = pad;
622 dev_dbg(csi2->dev, "Bound %s pad: %d\n", sd->name, pad);
624 return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
627 static void csi2_notify_unbind(struct v4l2_async_notifier *notifier,
628 struct v4l2_subdev *sd,
629 struct v4l2_async_subdev *asd)
631 struct csi2_dev *csi2 = notifier_to_dev(notifier);
636 static const struct v4l2_async_notifier_operations csi2_notify_ops = {
637 .bound = csi2_notify_bound,
638 .unbind = csi2_notify_unbind,
641 static int csi2_async_register(struct csi2_dev *csi2)
643 struct v4l2_fwnode_endpoint vep = {
644 .bus_type = V4L2_MBUS_CSI2_DPHY,
646 struct v4l2_async_subdev *asd;
647 struct fwnode_handle *ep;
650 v4l2_async_notifier_init(&csi2->notifier);
652 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0,
653 FWNODE_GRAPH_ENDPOINT_NEXT);
657 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
661 csi2->data_lanes = vep.bus.mipi_csi2.num_data_lanes;
663 dev_dbg(csi2->dev, "data lanes: %d\n", vep.bus.mipi_csi2.num_data_lanes);
664 dev_dbg(csi2->dev, "flags: 0x%08x\n", vep.bus.mipi_csi2.flags);
666 asd = v4l2_async_notifier_add_fwnode_remote_subdev(
667 &csi2->notifier, ep, struct v4l2_async_subdev);
668 fwnode_handle_put(ep);
673 csi2->notifier.ops = &csi2_notify_ops;
675 ret = v4l2_async_subdev_notifier_register(&csi2->sd,
680 return v4l2_async_register_subdev(&csi2->sd);
683 fwnode_handle_put(ep);
687 static int csi2_probe(struct platform_device *pdev)
689 struct csi2_dev *csi2;
690 struct resource *res;
693 csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL);
697 csi2->dev = &pdev->dev;
699 v4l2_subdev_init(&csi2->sd, &csi2_subdev_ops);
700 v4l2_set_subdevdata(&csi2->sd, &pdev->dev);
701 csi2->sd.internal_ops = &csi2_internal_ops;
702 csi2->sd.entity.ops = &csi2_entity_ops;
703 csi2->sd.dev = &pdev->dev;
704 csi2->sd.owner = THIS_MODULE;
705 csi2->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
706 strscpy(csi2->sd.name, DEVICE_NAME, sizeof(csi2->sd.name));
707 csi2->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
708 csi2->sd.grp_id = IMX_MEDIA_GRP_ID_CSI2;
710 for (i = 0; i < CSI2_NUM_PADS; i++) {
711 csi2->pad[i].flags = (i == CSI2_SINK_PAD) ?
712 MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
715 ret = media_entity_pads_init(&csi2->sd.entity, CSI2_NUM_PADS,
720 csi2->pllref_clk = devm_clk_get(&pdev->dev, "ref");
721 if (IS_ERR(csi2->pllref_clk)) {
722 v4l2_err(&csi2->sd, "failed to get pll reference clock\n");
723 return PTR_ERR(csi2->pllref_clk);
726 csi2->dphy_clk = devm_clk_get(&pdev->dev, "dphy");
727 if (IS_ERR(csi2->dphy_clk)) {
728 v4l2_err(&csi2->sd, "failed to get dphy clock\n");
729 return PTR_ERR(csi2->dphy_clk);
732 csi2->pix_clk = devm_clk_get(&pdev->dev, "pix");
733 if (IS_ERR(csi2->pix_clk)) {
734 v4l2_err(&csi2->sd, "failed to get pixel clock\n");
735 return PTR_ERR(csi2->pix_clk);
738 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
740 v4l2_err(&csi2->sd, "failed to get platform resources\n");
744 csi2->base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
748 mutex_init(&csi2->lock);
750 ret = clk_prepare_enable(csi2->pllref_clk);
752 v4l2_err(&csi2->sd, "failed to enable pllref_clk\n");
756 ret = clk_prepare_enable(csi2->dphy_clk);
758 v4l2_err(&csi2->sd, "failed to enable dphy_clk\n");
762 platform_set_drvdata(pdev, &csi2->sd);
764 ret = csi2_async_register(csi2);
771 v4l2_async_notifier_unregister(&csi2->notifier);
772 v4l2_async_notifier_cleanup(&csi2->notifier);
773 clk_disable_unprepare(csi2->dphy_clk);
775 clk_disable_unprepare(csi2->pllref_clk);
777 mutex_destroy(&csi2->lock);
781 static int csi2_remove(struct platform_device *pdev)
783 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
784 struct csi2_dev *csi2 = sd_to_dev(sd);
786 v4l2_async_notifier_unregister(&csi2->notifier);
787 v4l2_async_notifier_cleanup(&csi2->notifier);
788 v4l2_async_unregister_subdev(sd);
789 clk_disable_unprepare(csi2->dphy_clk);
790 clk_disable_unprepare(csi2->pllref_clk);
791 mutex_destroy(&csi2->lock);
792 media_entity_cleanup(&sd->entity);
797 static const struct of_device_id csi2_dt_ids[] = {
798 { .compatible = "fsl,imx6-mipi-csi2", },
801 MODULE_DEVICE_TABLE(of, csi2_dt_ids);
803 static struct platform_driver csi2_driver = {
806 .of_match_table = csi2_dt_ids,
809 .remove = csi2_remove,
812 module_platform_driver(csi2_driver);
814 MODULE_DESCRIPTION("i.MX5/6 MIPI CSI-2 Receiver driver");
815 MODULE_AUTHOR("Steve Longerbeam <steve_longerbeam@mentor.com>");
816 MODULE_LICENSE("GPL");