drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2010 - 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #define __INLINE_INPUT_SYSTEM__
  16 #include "input_system.h"
  17 #include "assert_support.h"
  18 #include "ia_css_isys.h"
  19 #include "ia_css_irq.h"
  20 #include "sh_css_internal.h"
  21
  22 #if !defined(USE_INPUT_SYSTEM_VERSION_2401)
  23 void ia_css_isys_rx_enable_all_interrupts(enum mipi_port_id port)
  24 {
  25         hrt_data bits = receiver_port_reg_load(RX0_ID,
  26                                                port,
  27                                                _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
  28
  29         bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) |
  30 #if defined(HAS_RX_VERSION_2)
  31                 (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT) |
  32 #endif
  33                 (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT) |
  34                 (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT) |
  35                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT) |
  36                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT) |
  37                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT) |
  38                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT) |
  39                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT) |
  40                 /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT) | */
  41                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT) |
  42                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT) |
  43                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT) |
  44                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT) |
  45                 (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT) |
  46                 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT);
  47         /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT); */
  48
  49         receiver_port_reg_store(RX0_ID,
  50                                 port,
  51                                 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
  52
  53         /*
  54          * The CSI is nested into the Iunit IRQ's
  55          */
  56         ia_css_irq_enable(IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR, true);
  57
  58         return;
  59 }
  60
  61 /* This function converts between the enum used on the CSS API and the
  62  * internal DLI enum type.
  63  * We do not use an array for this since we cannot use named array
  64  * initializers in Windows. Without that there is no easy way to guarantee
  65  * that the array values would be in the correct order.
  66  * */
  67 enum mipi_port_id ia_css_isys_port_to_mipi_port(enum mipi_port_id api_port)
  68 {
  69         /* In this module the validity of the inptu variable should
  70          * have been checked already, so we do not check for erroneous
  71          * values. */
  72         enum mipi_port_id port = MIPI_PORT0_ID;
  73
  74         if (api_port == MIPI_PORT1_ID)
  75                 port = MIPI_PORT1_ID;
  76         else if (api_port == MIPI_PORT2_ID)
  77                 port = MIPI_PORT2_ID;
  78
  79         return port;
  80 }
  81
  82 unsigned int ia_css_isys_rx_get_interrupt_reg(enum mipi_port_id port)
  83 {
  84         return receiver_port_reg_load(RX0_ID,
  85                                       port,
  86                                       _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
  87 }
  88
  89 void ia_css_rx_get_irq_info(unsigned int *irq_infos)
  90 {
  91         ia_css_rx_port_get_irq_info(MIPI_PORT1_ID, irq_infos);
  92 }
  93
  94 void ia_css_rx_port_get_irq_info(enum mipi_port_id api_port,
  95                                  unsigned int *irq_infos)
  96 {
  97         enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port);
  98
  99         ia_css_isys_rx_get_irq_info(port, irq_infos);
 100 }
 101
 102 void ia_css_isys_rx_get_irq_info(enum mipi_port_id port,
 103                                  unsigned int *irq_infos)
 104 {
 105         unsigned int bits;
 106
 107         assert(irq_infos);
 108         bits = ia_css_isys_rx_get_interrupt_reg(port);
 109         *irq_infos = ia_css_isys_rx_translate_irq_infos(bits);
 110 }
 111
 112 /* Translate register bits to CSS API enum mask */
 113 unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits)
 114 {
 115         unsigned int infos = 0;
 116
 117         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT))
 118                 infos |= IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN;
 119 #if defined(HAS_RX_VERSION_2)
 120         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT))
 121                 infos |= IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT;
 122 #endif
 123         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT))
 124                 infos |= IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE;
 125         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT))
 126                 infos |= IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE;
 127         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT))
 128                 infos |= IA_CSS_RX_IRQ_INFO_ECC_CORRECTED;
 129         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT))
 130                 infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT;
 131         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT))
 132                 infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC;
 133         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT))
 134                 infos |= IA_CSS_RX_IRQ_INFO_ERR_CONTROL;
 135         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT))
 136                 infos |= IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE;
 137         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT))
 138                 infos |= IA_CSS_RX_IRQ_INFO_ERR_CRC;
 139         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT))
 140                 infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID;
 141         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT))
 142                 infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC;
 143         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT))
 144                 infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA;
 145         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT))
 146                 infos |= IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT;
 147         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT))
 148                 infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC;
 149         if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT))
 150                 infos |= IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC;
 151
 152         return infos;
 153 }
 154
 155 void ia_css_rx_clear_irq_info(unsigned int irq_infos)
 156 {
 157         ia_css_rx_port_clear_irq_info(MIPI_PORT1_ID, irq_infos);
 158 }
 159
 160 void ia_css_rx_port_clear_irq_info(enum mipi_port_id api_port,
 161                                    unsigned int irq_infos)
 162 {
 163         enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port);
 164
 165         ia_css_isys_rx_clear_irq_info(port, irq_infos);
 166 }
 167
 168 void ia_css_isys_rx_clear_irq_info(enum mipi_port_id port,
 169                                    unsigned int irq_infos)
 170 {
 171         hrt_data bits = receiver_port_reg_load(RX0_ID,
 172                                                port,
 173                                                _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
 174
 175         /* MW: Why do we remap the receiver bitmap */
 176         if (irq_infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
 177                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT;
 178 #if defined(HAS_RX_VERSION_2)
 179         if (irq_infos & IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT)
 180                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT;
 181 #endif
 182         if (irq_infos & IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE)
 183                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT;
 184         if (irq_infos & IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE)
 185                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT;
 186         if (irq_infos & IA_CSS_RX_IRQ_INFO_ECC_CORRECTED)
 187                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT;
 188         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
 189                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT;
 190         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
 191                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT;
 192         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
 193                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT;
 194         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
 195                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT;
 196         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
 197                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT;
 198         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
 199                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT;
 200         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
 201                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT;
 202         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
 203                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT;
 204         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
 205                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT;
 206         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
 207                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT;
 208         if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
 209                 bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT;
 210
 211         receiver_port_reg_store(RX0_ID,
 212                                 port,
 213                                 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
 214
 215         return;
 216 }
 217 #endif /* #if !defined(USE_INPUT_SYSTEM_VERSION_2401) */
 218
 219 enum ia_css_err ia_css_isys_convert_stream_format_to_mipi_format(
 220     enum atomisp_input_format input_format,
 221     mipi_predictor_t compression,
 222     unsigned int *fmt_type)
 223 {
 224         assert(fmt_type);
 225         /*
 226          * Custom (user defined) modes. Used for compressed
 227          * MIPI transfers
 228          *
 229          * Checkpatch thinks the indent before "if" is suspect
 230          * I think the only suspect part is the missing "else"
 231          * because of the return.
 232          */
 233         if (compression != MIPI_PREDICTOR_NONE) {
 234                 switch (input_format) {
 235                 case ATOMISP_INPUT_FORMAT_RAW_6:
 236                         *fmt_type = 6;
 237                         break;
 238                 case ATOMISP_INPUT_FORMAT_RAW_7:
 239                         *fmt_type = 7;
 240                         break;
 241                 case ATOMISP_INPUT_FORMAT_RAW_8:
 242                         *fmt_type = 8;
 243                         break;
 244                 case ATOMISP_INPUT_FORMAT_RAW_10:
 245                         *fmt_type = 10;
 246                         break;
 247                 case ATOMISP_INPUT_FORMAT_RAW_12:
 248                         *fmt_type = 12;
 249                         break;
 250                 case ATOMISP_INPUT_FORMAT_RAW_14:
 251                         *fmt_type = 14;
 252                         break;
 253                 case ATOMISP_INPUT_FORMAT_RAW_16:
 254                         *fmt_type = 16;
 255                         break;
 256                 default:
 257                         return IA_CSS_ERR_INTERNAL_ERROR;
 258                 }
 259                 return IA_CSS_SUCCESS;
 260         }
 261         /*
 262          * This mapping comes from the Arasan CSS function spec
 263          * (CSS_func_spec1.08_ahb_sep29_08.pdf).
 264          *
 265          * MW: For some reason the mapping is not 1-to-1
 266          */
 267         switch (input_format) {
 268         case ATOMISP_INPUT_FORMAT_RGB_888:
 269                 *fmt_type = MIPI_FORMAT_RGB888;
 270                 break;
 271         case ATOMISP_INPUT_FORMAT_RGB_555:
 272                 *fmt_type = MIPI_FORMAT_RGB555;
 273                 break;
 274         case ATOMISP_INPUT_FORMAT_RGB_444:
 275                 *fmt_type = MIPI_FORMAT_RGB444;
 276                 break;
 277         case ATOMISP_INPUT_FORMAT_RGB_565:
 278                 *fmt_type = MIPI_FORMAT_RGB565;
 279                 break;
 280         case ATOMISP_INPUT_FORMAT_RGB_666:
 281                 *fmt_type = MIPI_FORMAT_RGB666;
 282                 break;
 283         case ATOMISP_INPUT_FORMAT_RAW_8:
 284                 *fmt_type = MIPI_FORMAT_RAW8;
 285                 break;
 286         case ATOMISP_INPUT_FORMAT_RAW_10:
 287                 *fmt_type = MIPI_FORMAT_RAW10;
 288                 break;
 289         case ATOMISP_INPUT_FORMAT_RAW_6:
 290                 *fmt_type = MIPI_FORMAT_RAW6;
 291                 break;
 292         case ATOMISP_INPUT_FORMAT_RAW_7:
 293                 *fmt_type = MIPI_FORMAT_RAW7;
 294                 break;
 295         case ATOMISP_INPUT_FORMAT_RAW_12:
 296                 *fmt_type = MIPI_FORMAT_RAW12;
 297                 break;
 298         case ATOMISP_INPUT_FORMAT_RAW_14:
 299                 *fmt_type = MIPI_FORMAT_RAW14;
 300                 break;
 301         case ATOMISP_INPUT_FORMAT_YUV420_8:
 302                 *fmt_type = MIPI_FORMAT_YUV420_8;
 303                 break;
 304         case ATOMISP_INPUT_FORMAT_YUV420_10:
 305                 *fmt_type = MIPI_FORMAT_YUV420_10;
 306                 break;
 307         case ATOMISP_INPUT_FORMAT_YUV422_8:
 308                 *fmt_type = MIPI_FORMAT_YUV422_8;
 309                 break;
 310         case ATOMISP_INPUT_FORMAT_YUV422_10:
 311                 *fmt_type = MIPI_FORMAT_YUV422_10;
 312                 break;
 313         case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY:
 314                 *fmt_type = MIPI_FORMAT_YUV420_8_LEGACY;
 315                 break;
 316         case ATOMISP_INPUT_FORMAT_EMBEDDED:
 317                 *fmt_type = MIPI_FORMAT_EMBEDDED;
 318                 break;
 319 #ifndef USE_INPUT_SYSTEM_VERSION_2401
 320         case ATOMISP_INPUT_FORMAT_RAW_16:
 321                 /* This is not specified by Arasan, so we use
 322                  * 17 for now.
 323                  */
 324                 *fmt_type = MIPI_FORMAT_RAW16;
 325                 break;
 326         case ATOMISP_INPUT_FORMAT_BINARY_8:
 327                 *fmt_type = MIPI_FORMAT_BINARY_8;
 328                 break;
 329 #else
 330         case ATOMISP_INPUT_FORMAT_USER_DEF1:
 331                 *fmt_type = MIPI_FORMAT_CUSTOM0;
 332                 break;
 333         case ATOMISP_INPUT_FORMAT_USER_DEF2:
 334                 *fmt_type = MIPI_FORMAT_CUSTOM1;
 335                 break;
 336         case ATOMISP_INPUT_FORMAT_USER_DEF3:
 337                 *fmt_type = MIPI_FORMAT_CUSTOM2;
 338                 break;
 339         case ATOMISP_INPUT_FORMAT_USER_DEF4:
 340                 *fmt_type = MIPI_FORMAT_CUSTOM3;
 341                 break;
 342         case ATOMISP_INPUT_FORMAT_USER_DEF5:
 343                 *fmt_type = MIPI_FORMAT_CUSTOM4;
 344                 break;
 345         case ATOMISP_INPUT_FORMAT_USER_DEF6:
 346                 *fmt_type = MIPI_FORMAT_CUSTOM5;
 347                 break;
 348         case ATOMISP_INPUT_FORMAT_USER_DEF7:
 349                 *fmt_type = MIPI_FORMAT_CUSTOM6;
 350                 break;
 351         case ATOMISP_INPUT_FORMAT_USER_DEF8:
 352                 *fmt_type = MIPI_FORMAT_CUSTOM7;
 353                 break;
 354 #endif
 355
 356         case ATOMISP_INPUT_FORMAT_YUV420_16:
 357         case ATOMISP_INPUT_FORMAT_YUV422_16:
 358         default:
 359                 return IA_CSS_ERR_INTERNAL_ERROR;
 360         }
 361         return IA_CSS_SUCCESS;
 362 }
 363
 364 #if defined(USE_INPUT_SYSTEM_VERSION_2401)
 365 static mipi_predictor_t sh_css_csi2_compression_type_2_mipi_predictor(
 366     enum ia_css_csi2_compression_type type)
 367 {
 368         mipi_predictor_t predictor = MIPI_PREDICTOR_NONE;
 369
 370         switch (type) {
 371         case IA_CSS_CSI2_COMPRESSION_TYPE_1:
 372                 predictor = MIPI_PREDICTOR_TYPE1 - 1;
 373                 break;
 374         case IA_CSS_CSI2_COMPRESSION_TYPE_2:
 375                 predictor = MIPI_PREDICTOR_TYPE2 - 1;
 376         default:
 377                 break;
 378         }
 379         return predictor;
 380 }
 381
 382 enum ia_css_err ia_css_isys_convert_compressed_format(
 383     struct ia_css_csi2_compression *comp,
 384     struct input_system_cfg_s *cfg)
 385 {
 386         enum ia_css_err err = IA_CSS_SUCCESS;
 387
 388         assert(comp);
 389         assert(cfg);
 390
 391         if (comp->type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) {
 392                 /* compression register bit slicing
 393                 4 bit for each user defined data type
 394                         3 bit indicate compression scheme
 395                                 000 No compression
 396                                 001 10-6-10
 397                                 010 10-7-10
 398                                 011 10-8-10
 399                                 100 12-6-12
 400                                 101 12-6-12
 401                                 100 12-7-12
 402                                 110 12-8-12
 403                         1 bit indicate predictor
 404                 */
 405                 if (comp->uncompressed_bits_per_pixel == UNCOMPRESSED_BITS_PER_PIXEL_10) {
 406                         switch (comp->compressed_bits_per_pixel) {
 407                         case COMPRESSED_BITS_PER_PIXEL_6:
 408                                 cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_6_10;
 409                                 break;
 410                         case COMPRESSED_BITS_PER_PIXEL_7:
 411                                 cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_7_10;
 412                                 break;
 413                         case COMPRESSED_BITS_PER_PIXEL_8:
 414                                 cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_8_10;
 415                                 break;
 416                         default:
 417                                 err = IA_CSS_ERR_INVALID_ARGUMENTS;
 418                         }
 419                 } else if (comp->uncompressed_bits_per_pixel ==
 420                            UNCOMPRESSED_BITS_PER_PIXEL_12) {
 421                         switch (comp->compressed_bits_per_pixel) {
 422                         case COMPRESSED_BITS_PER_PIXEL_6:
 423                                 cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_6_12;
 424                                 break;
 425                         case COMPRESSED_BITS_PER_PIXEL_7:
 426                                 cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_7_12;
 427                                 break;
 428                         case COMPRESSED_BITS_PER_PIXEL_8:
 429                                 cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_8_12;
 430                                 break;
 431                         default:
 432                                 err = IA_CSS_ERR_INVALID_ARGUMENTS;
 433                         }
 434                 } else
 435                         err = IA_CSS_ERR_INVALID_ARGUMENTS;
 436                 cfg->csi_port_attr.comp_predictor =
 437                     sh_css_csi2_compression_type_2_mipi_predictor(comp->type);
 438                 cfg->csi_port_attr.comp_enable = true;
 439         } else /* No compression */
 440                 cfg->csi_port_attr.comp_enable = false;
 441         return err;
 442 }
 443
 444 unsigned int ia_css_csi2_calculate_input_system_alignment(
 445     enum atomisp_input_format fmt_type)
 446 {
 447         unsigned int memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES;
 448
 449         switch (fmt_type) {
 450         case ATOMISP_INPUT_FORMAT_RAW_6:
 451         case ATOMISP_INPUT_FORMAT_RAW_7:
 452         case ATOMISP_INPUT_FORMAT_RAW_8:
 453         case ATOMISP_INPUT_FORMAT_RAW_10:
 454         case ATOMISP_INPUT_FORMAT_RAW_12:
 455         case ATOMISP_INPUT_FORMAT_RAW_14:
 456                 memory_alignment_in_bytes = 2 * ISP_VEC_NELEMS;
 457                 break;
 458         case ATOMISP_INPUT_FORMAT_YUV420_8:
 459         case ATOMISP_INPUT_FORMAT_YUV422_8:
 460         case ATOMISP_INPUT_FORMAT_USER_DEF1:
 461         case ATOMISP_INPUT_FORMAT_USER_DEF2:
 462         case ATOMISP_INPUT_FORMAT_USER_DEF3:
 463         case ATOMISP_INPUT_FORMAT_USER_DEF4:
 464         case ATOMISP_INPUT_FORMAT_USER_DEF5:
 465         case ATOMISP_INPUT_FORMAT_USER_DEF6:
 466         case ATOMISP_INPUT_FORMAT_USER_DEF7:
 467         case ATOMISP_INPUT_FORMAT_USER_DEF8:
 468                 /* Planar YUV formats need to have all planes aligned, this means
 469                  * double the alignment for the Y plane if the horizontal decimation is 2. */
 470                 memory_alignment_in_bytes = 2 * HIVE_ISP_DDR_WORD_BYTES;
 471                 break;
 472         case ATOMISP_INPUT_FORMAT_EMBEDDED:
 473         default:
 474                 memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES;
 475                 break;
 476         }
 477         return memory_alignment_in_bytes;
 478 }
 479
 480 #endif
 481
 482 #if !defined(USE_INPUT_SYSTEM_VERSION_2401)
 483 void ia_css_isys_rx_configure(const rx_cfg_t *config,
 484                               const enum ia_css_input_mode input_mode)
 485 {
 486 #if defined(HAS_RX_VERSION_2)
 487         bool port_enabled[N_MIPI_PORT_ID];
 488         bool any_port_enabled = false;
 489         enum mipi_port_id port;
 490
 491         if ((!config)
 492             || (config->mode >= N_RX_MODE)
 493             || (config->port >= N_MIPI_PORT_ID)) {
 494                 assert(0);
 495                 return;
 496         }
 497         for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) {
 498                 if (is_receiver_port_enabled(RX0_ID, port))
 499                         any_port_enabled = true;
 500         }
 501         /* AM: Check whether this is a problem with multiple
 502          * streams. MS: This is the case. */
 503
 504         port = config->port;
 505         receiver_port_enable(RX0_ID, port, false);
 506
 507         port = config->port;
 508
 509         /* AM: Check whether this is a problem with multiple streams. */
 510         if (MIPI_PORT_LANES[config->mode][port] != MIPI_0LANE_CFG) {
 511                 receiver_port_reg_store(RX0_ID, port,
 512                                         _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX,
 513                                         config->timeout);
 514                 receiver_port_reg_store(RX0_ID, port,
 515                                         _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX,
 516                                         config->initcount);
 517                 receiver_port_reg_store(RX0_ID, port,
 518                                         _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX,
 519                                         config->synccount);
 520                 receiver_port_reg_store(RX0_ID, port,
 521                                         _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX,
 522                                         config->rxcount);
 523
 524                 port_enabled[port] = true;
 525
 526                 if (input_mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) {
 527                         /* MW: A bit of a hack, straight wiring of the capture
 528                          * units,assuming they are linearly enumerated. */
 529                         input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
 530                                                           GPREGS_UNIT0_ID,
 531                                                           HIVE_ISYS_GPREG_MULTICAST_A_IDX
 532                                                           + (unsigned int)port,
 533                                                           INPUT_SYSTEM_CSI_BACKEND);
 534                         /* MW: Like the integration test example we overwite,
 535                          * the GPREG_MUX register */
 536                         input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
 537                                                           GPREGS_UNIT0_ID,
 538                                                           HIVE_ISYS_GPREG_MUX_IDX,
 539                                                           (input_system_multiplex_t)port);
 540                 } else {
 541                         /*
 542                          * AM: A bit of a hack, wiring the input system.
 543                          */
 544                         input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
 545                                                           GPREGS_UNIT0_ID,
 546                                                           HIVE_ISYS_GPREG_MULTICAST_A_IDX
 547                                                           + (unsigned int)port,
 548                                                           INPUT_SYSTEM_INPUT_BUFFER);
 549                         input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
 550                                                           GPREGS_UNIT0_ID,
 551                                                           HIVE_ISYS_GPREG_MUX_IDX,
 552                                                           INPUT_SYSTEM_ACQUISITION_UNIT);
 553                 }
 554         }
 555         /*
 556          * The 2ppc is shared for all ports, so we cannot
 557          * disable->configure->enable individual ports
 558          */
 559         /* AM: Check whether this is a problem with multiple streams. */
 560         /* MS: 2ppc should be a property per binary and should be
 561          * enabled/disabled per binary.
 562          * Currently it is implemented as a system wide setting due
 563          * to effort and risks. */
 564         if (!any_port_enabled) {
 565                 receiver_reg_store(RX0_ID,
 566                                    _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX,
 567                                    config->is_two_ppc);
 568                 receiver_reg_store(RX0_ID, _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX,
 569                                    config->is_two_ppc);
 570         }
 571         receiver_port_enable(RX0_ID, port, true);
 572         /* TODO: JB: need to add the beneath used define to mizuchi */
 573         /* sh_css_sw_hive_isp_css_2400_system_20121224_0125\css
 574          *                      \hrt\input_system_defs.h
 575          * #define INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG 0X207
 576          */
 577         /* TODO: need better name for define
 578          * input_system_reg_store(INPUT_SYSTEM0_ID,
 579          *                INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG, 1);
 580          */
 581         input_system_reg_store(INPUT_SYSTEM0_ID, 0x207, 1);
 582 #else
 583 #error "rx.c: RX version must be one of {RX_VERSION_2}"
 584 #endif
 585
 586         return;
 587 }
 588
 589 void ia_css_isys_rx_disable(void)
 590 {
 591         enum mipi_port_id port;
 592
 593         for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) {
 594                 receiver_port_reg_store(RX0_ID, port,
 595                                         _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX,
 596                                         false);
 597         }
 598         return;
 599 }
 600 #endif /* if !defined(USE_INPUT_SYSTEM_VERSION_2401) */