2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __SYSTEM_LOCAL_H_INCLUDED__
16 #define __SYSTEM_LOCAL_H_INCLUDED__
18 #ifdef HRT_ISP_CSS_CUSTOM_HOST
19 #ifndef HRT_USE_VIR_ADDRS
20 #define HRT_USE_VIR_ADDRS
22 /* This interface is deprecated */
23 /*#include "hive_isp_css_custom_host_hrt.h"*/
26 #include "system_global.h"
28 #define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
30 /* This interface is deprecated */
31 #include "hive_types.h"
34 * Cell specific address maps
36 #if HRT_ADDRESS_WIDTH == 64
38 #define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
41 static const hrt_address DDR_BASE[N_DDR_ID] = {
46 static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
50 static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
54 static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
58 static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
59 0x00000000001C0000ULL,
60 0x00000000001D0000ULL,
64 static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
69 static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
73 static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
78 #if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM)
80 * MMU0_ID: The data MMU
81 * MMU1_ID: The icache MMU
83 static const hrt_address MMU_BASE[N_MMU_ID] = {
84 0x0000000000070000ULL,
88 #error "system_local.h: SYSTEM must be one of {2400, 2401 }"
92 static const hrt_address DMA_BASE[N_DMA_ID] = {
96 static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
101 static const hrt_address IRQ_BASE[N_IRQ_ID] = {
102 0x0000000000000500ULL,
103 0x0000000000030A00ULL,
104 0x000000000008C000ULL,
105 0x0000000000090200ULL
108 0x0000000000000500ULL};
112 static const hrt_address GDC_BASE[N_GDC_ID] = {
113 0x0000000000050000ULL,
114 0x0000000000060000ULL
117 /* FIFO_MONITOR (not a subset of GP_DEVICE) */
118 static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
119 0x0000000000000000ULL
123 static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
124 0x0000000000000000ULL};
126 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
127 0x0000000000090000ULL};
130 /* GP_DEVICE (single base for all separate GP_REG instances) */
131 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
132 0x0000000000000000ULL
135 /*GP TIMER , all timer registers are inter-twined,
136 * so, having multiple base addresses for
137 * different timers does not help*/
138 static const hrt_address GP_TIMER_BASE =
139 (hrt_address)0x0000000000000600ULL;
142 static const hrt_address GPIO_BASE[N_GPIO_ID] = {
143 0x0000000000000400ULL
147 static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
148 0x0000000000000100ULL
151 /* INPUT_FORMATTER */
152 static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
153 0x0000000000030000ULL,
154 0x0000000000030200ULL,
155 0x0000000000030400ULL,
156 0x0000000000030600ULL
160 static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
161 0x0000000000080000ULL
163 /* 0x0000000000081000ULL, */ /* capture A */
164 /* 0x0000000000082000ULL, */ /* capture B */
165 /* 0x0000000000083000ULL, */ /* capture C */
166 /* 0x0000000000084000ULL, */ /* Acquisition */
167 /* 0x0000000000085000ULL, */ /* DMA */
168 /* 0x0000000000089000ULL, */ /* ctrl */
169 /* 0x000000000008A000ULL, */ /* GP regs */
170 /* 0x000000000008B000ULL, */ /* FIFO */
171 /* 0x000000000008C000ULL, */ /* IRQ */
173 /* RX, the MIPI lane control regs start at offset 0 */
174 static const hrt_address RX_BASE[N_RX_ID] = {
175 0x0000000000080100ULL
178 /* IBUF_CTRL, part of the Input System 2401 */
179 static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
180 0x00000000000C1800ULL, /* ibuf controller A */
181 0x00000000000C3800ULL, /* ibuf controller B */
182 0x00000000000C5800ULL /* ibuf controller C */
185 /* ISYS IRQ Controllers, part of the Input System 2401 */
186 static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
187 0x00000000000C1400ULL, /* port a */
188 0x00000000000C3400ULL, /* port b */
189 0x00000000000C5400ULL /* port c */
192 /* CSI FE, part of the Input System 2401 */
193 static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
194 0x00000000000C0400ULL, /* csi fe controller A */
195 0x00000000000C2400ULL, /* csi fe controller B */
196 0x00000000000C4400ULL /* csi fe controller C */
199 /* CSI BE, part of the Input System 2401 */
200 static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
201 0x00000000000C0800ULL, /* csi be controller A */
202 0x00000000000C2800ULL, /* csi be controller B */
203 0x00000000000C4800ULL /* csi be controller C */
206 /* PIXEL Generator, part of the Input System 2401 */
207 static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
208 0x00000000000C1000ULL, /* pixel gen controller A */
209 0x00000000000C3000ULL, /* pixel gen controller B */
210 0x00000000000C5000ULL /* pixel gen controller C */
213 /* Stream2MMIO, part of the Input System 2401 */
214 static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
215 0x00000000000C0C00ULL, /* stream2mmio controller A */
216 0x00000000000C2C00ULL, /* stream2mmio controller B */
217 0x00000000000C4C00ULL /* stream2mmio controller C */
219 #elif HRT_ADDRESS_WIDTH == 32
221 #define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
223 /* DDR : Attention, this value not defined in 32-bit */
224 static const hrt_address DDR_BASE[N_DDR_ID] = {
229 static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
233 static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
237 static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
241 static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
247 static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
252 static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
256 static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
261 #if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM)
263 * MMU0_ID: The data MMU
264 * MMU1_ID: The icache MMU
266 static const hrt_address MMU_BASE[N_MMU_ID] = {
271 #error "system_local.h: SYSTEM must be one of {2400, 2401 }"
275 static const hrt_address DMA_BASE[N_DMA_ID] = {
279 static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
284 static const hrt_address IRQ_BASE[N_IRQ_ID] = {
295 static const hrt_address GDC_BASE[N_GDC_ID] = {
300 /* FIFO_MONITOR (not a subset of GP_DEVICE) */
301 static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
306 static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
309 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
313 /* GP_DEVICE (single base for all separate GP_REG instances) */
314 static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
318 /*GP TIMER , all timer registers are inter-twined,
319 * so, having multiple base addresses for
320 * different timers does not help*/
321 static const hrt_address GP_TIMER_BASE =
322 (hrt_address)0x00000600UL;
324 static const hrt_address GPIO_BASE[N_GPIO_ID] = {
329 static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
333 /* INPUT_FORMATTER */
334 static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
339 /* 0x00030600UL, */ /* memcpy() */
342 static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
345 /* 0x00081000UL, */ /* capture A */
346 /* 0x00082000UL, */ /* capture B */
347 /* 0x00083000UL, */ /* capture C */
348 /* 0x00084000UL, */ /* Acquisition */
349 /* 0x00085000UL, */ /* DMA */
350 /* 0x00089000UL, */ /* ctrl */
351 /* 0x0008A000UL, */ /* GP regs */
352 /* 0x0008B000UL, */ /* FIFO */
353 /* 0x0008C000UL, */ /* IRQ */
355 /* RX, the MIPI lane control regs start at offset 0 */
356 static const hrt_address RX_BASE[N_RX_ID] = {
360 /* IBUF_CTRL, part of the Input System 2401 */
361 static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
362 0x000C1800UL, /* ibuf controller A */
363 0x000C3800UL, /* ibuf controller B */
364 0x000C5800UL /* ibuf controller C */
367 /* ISYS IRQ Controllers, part of the Input System 2401 */
368 static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
369 0x000C1400ULL, /* port a */
370 0x000C3400ULL, /* port b */
371 0x000C5400ULL /* port c */
374 /* CSI FE, part of the Input System 2401 */
375 static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
376 0x000C0400UL, /* csi fe controller A */
377 0x000C2400UL, /* csi fe controller B */
378 0x000C4400UL /* csi fe controller C */
381 /* CSI BE, part of the Input System 2401 */
382 static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
383 0x000C0800UL, /* csi be controller A */
384 0x000C2800UL, /* csi be controller B */
385 0x000C4800UL /* csi be controller C */
388 /* PIXEL Generator, part of the Input System 2401 */
389 static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
390 0x000C1000UL, /* pixel gen controller A */
391 0x000C3000UL, /* pixel gen controller B */
392 0x000C5000UL /* pixel gen controller C */
395 /* Stream2MMIO, part of the Input System 2401 */
396 static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
397 0x000C0C00UL, /* stream2mmio controller A */
398 0x000C2C00UL, /* stream2mmio controller B */
399 0x000C4C00UL /* stream2mmio controller C */
403 #error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
406 #endif /* __SYSTEM_LOCAL_H_INCLUDED__ */