1 // SPDX-License-Identifier: GPL-2.0+
3 * KP2000 SPI controller driver
5 * Copyright (C) 2014-2018 Daktronics
6 * Author: Matt Sickler <matt.sickler@daktronics.com>
7 * Very loosely based on spi-omap2-mcspi.c
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/module.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <linux/slab.h>
22 #include <linux/pm_runtime.h>
24 #include <linux/of_device.h>
25 #include <linux/gcd.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/flash.h>
28 #include <linux/mtd/partitions.h>
31 #include "spi_parts.h"
37 #define KP_SPI_REG_CONFIG 0x0 /* 0x00 */
38 #define KP_SPI_REG_STATUS 0x1 /* 0x08 */
39 #define KP_SPI_REG_FFCTRL 0x2 /* 0x10 */
40 #define KP_SPI_REG_TXDATA 0x3 /* 0x18 */
41 #define KP_SPI_REG_RXDATA 0x4 /* 0x20 */
43 #define KP_SPI_CLK 48000000
44 #define KP_SPI_MAX_FIFODEPTH 64
45 #define KP_SPI_MAX_FIFOWCNT 0xFFFF
47 #define KP_SPI_REG_CONFIG_TRM_TXRX 0
48 #define KP_SPI_REG_CONFIG_TRM_RX 1
49 #define KP_SPI_REG_CONFIG_TRM_TX 2
51 #define KP_SPI_REG_STATUS_RXS 0x01
52 #define KP_SPI_REG_STATUS_TXS 0x02
53 #define KP_SPI_REG_STATUS_EOT 0x04
54 #define KP_SPI_REG_STATUS_TXFFE 0x10
55 #define KP_SPI_REG_STATUS_TXFFF 0x20
56 #define KP_SPI_REG_STATUS_RXFFE 0x40
57 #define KP_SPI_REG_STATUS_RXFFF 0x80
65 struct spi_master *master;
70 unsigned int pin_dir:1;
74 struct kp_spi_controller_state {
77 unsigned char chip_select;
84 /* use this to access individual elements */
85 struct __attribute__((packed)) spi_config_bitfield {
86 unsigned int pha : 1; /* spim_clk Phase */
87 unsigned int pol : 1; /* spim_clk Polarity */
88 unsigned int epol : 1; /* spim_csx Polarity */
89 unsigned int dpe : 1; /* Transmission Enable */
90 unsigned int wl : 5; /* Word Length */
92 unsigned int trm : 2; /* TxRx Mode */
93 unsigned int cs : 4; /* Chip Select */
94 unsigned int wcnt : 7; /* Word Count */
95 unsigned int ffen : 1; /* FIFO Enable */
96 unsigned int spi_en : 1; /* SPI Enable */
99 /* use this to grab the whole register */
105 union kp_spi_status {
106 struct __attribute__((packed)) spi_status_bitfield {
107 unsigned int rx : 1; /* Rx Status */
108 unsigned int tx : 1; /* Tx Status */
109 unsigned int eo : 1; /* End of Transfer */
111 unsigned int txffe : 1; /* Tx FIFO Empty */
112 unsigned int txfff : 1; /* Tx FIFO Full */
113 unsigned int rxffe : 1; /* Rx FIFO Empty */
114 unsigned int rxfff : 1; /* Rx FIFO Full */
122 union kp_spi_ffctrl {
123 struct __attribute__((packed)) spi_ffctrl_bitfield {
124 unsigned int ffstart : 1; /* FIFO Start */
136 kp_spi_bytes_per_word(int word_len)
141 else if (word_len <= 16) {
144 else { /* word_len <= 32 */
150 kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx)
152 u64 __iomem *addr = cs->base;
156 if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0)){
157 return cs->conf_cache;
159 val = readq((void*)addr);
164 kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val)
166 u64 __iomem *addr = cs->base;
168 writeq(val, (void*)addr);
169 if (idx == KP_SPI_REG_CONFIG)
170 cs->conf_cache = val;
174 kp_spi_wait_for_reg_bit(struct kp_spi_controller_state *cs, int idx, unsigned long bit)
176 unsigned long timeout;
177 timeout = jiffies + msecs_to_jiffies(1000);
178 while (!(kp_spi_read_reg(cs, idx) & bit)) {
179 if (time_after(jiffies, timeout)) {
180 if (!(kp_spi_read_reg(cs, idx) & bit)) {
192 kp_spi_txrx_pio(struct spi_device *spidev, struct spi_transfer *transfer)
194 struct kp_spi_controller_state *cs = spidev->controller_state;
195 unsigned int count = transfer->len;
196 unsigned int c = count;
199 u8 *rx = transfer->rx_buf;
200 const u8 *tx = transfer->tx_buf;
204 for (i = 0 ; i < c ; i++) {
207 if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS, KP_SPI_REG_STATUS_TXS) < 0) {
211 kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, val);
216 for (i = 0 ; i < c ; i++) {
219 kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, 0x00);
221 if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS, KP_SPI_REG_STATUS_RXS) < 0) {
225 test = kp_spi_read_reg(cs, KP_SPI_REG_RXDATA);
231 if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS, KP_SPI_REG_STATUS_EOT) < 0) {
232 //TODO: Figure out how to abort transaction?? This has never happened in practice though...
243 kp_spi_setup(struct spi_device *spidev)
245 union kp_spi_config sc;
246 struct kp_spi *kpspi = spi_master_get_devdata(spidev->master);
247 struct kp_spi_controller_state *cs;
249 /* setup controller state */
250 cs = spidev->controller_state;
252 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
256 cs->base = kpspi->base;
257 cs->phys = kpspi->phys;
258 cs->chip_select = spidev->chip_select;
259 cs->word_len = spidev->bits_per_word;
261 spidev->controller_state = cs;
264 /* set config register */
265 sc.bitfield.wl = spidev->bits_per_word - 1;
266 sc.bitfield.cs = spidev->chip_select;
267 sc.bitfield.spi_en = 0;
269 sc.bitfield.ffen = 0;
270 kp_spi_write_reg(spidev->controller_state, KP_SPI_REG_CONFIG, sc.reg);
275 kp_spi_transfer_one_message(struct spi_master *master, struct spi_message *m)
277 struct kp_spi_controller_state *cs;
278 struct spi_device *spidev;
279 struct kp_spi *kpspi;
280 struct spi_transfer *transfer;
281 union kp_spi_config sc;
285 kpspi = spi_master_get_devdata(master);
286 m->actual_length = 0;
289 cs = spidev->controller_state;
291 /* reject invalid messages and transfers */
292 if (list_empty(&m->transfers)) {
297 list_for_each_entry(transfer, &m->transfers, transfer_list) {
298 const void *tx_buf = transfer->tx_buf;
299 void *rx_buf = transfer->rx_buf;
300 unsigned len = transfer->len;
302 if (transfer->speed_hz > KP_SPI_CLK || (len && !(rx_buf || tx_buf))) {
303 dev_dbg(kpspi->dev, " transfer: %d Hz, %d %s%s, %d bpw\n",
308 transfer->bits_per_word);
309 dev_dbg(kpspi->dev, " transfer -EINVAL\n");
312 if (transfer->speed_hz && (transfer->speed_hz < (KP_SPI_CLK >> 15))) {
313 dev_dbg(kpspi->dev, "speed_hz %d below minimum %d Hz\n",
316 dev_dbg(kpspi->dev, " speed_hz -EINVAL\n");
321 /* assert chip select to start the sequence*/
322 sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
323 sc.bitfield.spi_en = 1;
324 kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
327 if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS, KP_SPI_REG_STATUS_EOT) < 0) {
328 dev_info(kpspi->dev, "EOT timed out\n");
332 /* do the transfers for this message */
333 list_for_each_entry(transfer, &m->transfers, transfer_list) {
334 if (transfer->tx_buf == NULL && transfer->rx_buf == NULL && transfer->len) {
341 unsigned int word_len = spidev->bits_per_word;
344 /* set up the transfer... */
345 sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
348 if (transfer->tx_buf) {
349 sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_TX;
351 else if (transfer->rx_buf) {
352 sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_RX;
356 if (transfer->bits_per_word) {
357 word_len = transfer->bits_per_word;
359 cs->word_len = word_len;
360 sc.bitfield.wl = word_len-1;
363 sc.bitfield.cs = spidev->chip_select;
365 /* ...and write the new settings */
366 kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
368 /* do the transfer */
369 count = kp_spi_txrx_pio(spidev, transfer);
370 m->actual_length += count;
372 if (count != transfer->len) {
378 if (transfer->delay_usecs) {
379 udelay(transfer->delay_usecs);
383 /* de-assert chip select to end the sequence */
384 sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
385 sc.bitfield.spi_en = 0;
386 kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
390 spi_finalize_current_message(master);
395 kp_spi_cleanup(struct spi_device *spidev)
397 struct kp_spi_controller_state *cs = spidev->controller_state;
409 kp_spi_probe(struct platform_device *pldev)
411 struct kpc_core_device_platdata *drvdata;
412 struct spi_master *master;
413 struct kp_spi *kpspi;
418 drvdata = pldev->dev.platform_data;
420 dev_err(&pldev->dev, "kp_spi_probe: platform_data is NULL!\n");
424 master = spi_alloc_master(&pldev->dev, sizeof(struct kp_spi));
425 if (master == NULL) {
426 dev_err(&pldev->dev, "kp_spi_probe: master allocation failed\n");
430 /* set up the spi functions */
431 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
432 master->bits_per_word_mask = (unsigned int)SPI_BPW_RANGE_MASK(4, 32);
433 master->setup = kp_spi_setup;
434 master->transfer_one_message = kp_spi_transfer_one_message;
435 master->cleanup = kp_spi_cleanup;
437 platform_set_drvdata(pldev, master);
439 kpspi = spi_master_get_devdata(master);
440 kpspi->master = master;
441 kpspi->dev = &pldev->dev;
443 master->num_chipselect = 4;
444 if (pldev->id != -1) {
445 master->bus_num = pldev->id;
449 r = platform_get_resource(pldev, IORESOURCE_MEM, 0);
451 dev_err(&pldev->dev, "kp_spi_probe: Unable to get platform resources\n");
456 kpspi->phys = (unsigned long)ioremap_nocache(r->start, resource_size(r));
457 kpspi->base = (u64 __iomem *)kpspi->phys;
459 status = spi_register_master(master);
461 dev_err(&pldev->dev, "Unable to register SPI device\n");
465 /* register the slave boards */
466 #define NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(table) \
467 for (i = 0 ; i < ARRAY_SIZE(table) ; i++) { \
468 spi_new_device(master, &(table[i])); \
471 switch ((drvdata->card_id & 0xFFFF0000) >> 16){
472 case PCI_DEVICE_ID_DAKTRONICS_KADOKA_P2KR0:
473 NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(p2kr0_board_info);
476 dev_err(&pldev->dev, "Unknown hardware, cant know what partition table to use!\n");
484 spi_master_put(master);
489 kp_spi_remove(struct platform_device *pldev)
491 struct spi_master * master = platform_get_drvdata(pldev);
492 spi_unregister_master(master);
497 static struct platform_driver kp_spi_driver = {
499 .name = KP_DRIVER_NAME_SPI,
501 .probe = kp_spi_probe,
502 .remove = kp_spi_remove,
505 module_platform_driver(kp_spi_driver);
506 MODULE_LICENSE("GPL");
507 MODULE_ALIAS("platform:kp_spi");