drivers/staging/imx-drm/ipu-v3/ipu-dc.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/export.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/errno.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22
  23 #include "../imx-drm.h"
  24 #include "imx-ipu-v3.h"
  25 #include "ipu-prv.h"
  26
  27 #define DC_MAP_CONF_PTR(n)      (0x108 + ((n) & ~0x1) * 2)
  28 #define DC_MAP_CONF_VAL(n)      (0x144 + ((n) & ~0x1) * 2)
  29
  30 #define DC_EVT_NF               0
  31 #define DC_EVT_NL               1
  32 #define DC_EVT_EOF              2
  33 #define DC_EVT_NFIELD           3
  34 #define DC_EVT_EOL              4
  35 #define DC_EVT_EOFIELD          5
  36 #define DC_EVT_NEW_ADDR         6
  37 #define DC_EVT_NEW_CHAN         7
  38 #define DC_EVT_NEW_DATA         8
  39
  40 #define DC_EVT_NEW_ADDR_W_0     0
  41 #define DC_EVT_NEW_ADDR_W_1     1
  42 #define DC_EVT_NEW_CHAN_W_0     2
  43 #define DC_EVT_NEW_CHAN_W_1     3
  44 #define DC_EVT_NEW_DATA_W_0     4
  45 #define DC_EVT_NEW_DATA_W_1     5
  46 #define DC_EVT_NEW_ADDR_R_0     6
  47 #define DC_EVT_NEW_ADDR_R_1     7
  48 #define DC_EVT_NEW_CHAN_R_0     8
  49 #define DC_EVT_NEW_CHAN_R_1     9
  50 #define DC_EVT_NEW_DATA_R_0     10
  51 #define DC_EVT_NEW_DATA_R_1     11
  52
  53 #define DC_WR_CH_CONF           0x0
  54 #define DC_WR_CH_ADDR           0x4
  55 #define DC_RL_CH(evt)           (8 + ((evt) & ~0x1) * 2)
  56
  57 #define DC_GEN                  0xd4
  58 #define DC_DISP_CONF1(disp)     (0xd8 + (disp) * 4)
  59 #define DC_DISP_CONF2(disp)     (0xe8 + (disp) * 4)
  60 #define DC_STAT                 0x1c8
  61
  62 #define WROD(lf)                (0x18 | ((lf) << 1))
  63 #define WRG                     0x01
  64 #define WCLK                    0xc9
  65
  66 #define SYNC_WAVE 0
  67 #define NULL_WAVE (-1)
  68
  69 #define DC_GEN_SYNC_1_6_SYNC    (2 << 1)
  70 #define DC_GEN_SYNC_PRIORITY_1  (1 << 7)
  71
  72 #define DC_WR_CH_CONF_WORD_SIZE_8               (0 << 0)
  73 #define DC_WR_CH_CONF_WORD_SIZE_16              (1 << 0)
  74 #define DC_WR_CH_CONF_WORD_SIZE_24              (2 << 0)
  75 #define DC_WR_CH_CONF_WORD_SIZE_32              (3 << 0)
  76 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)       (((i) & 0x1) << 3)
  77 #define DC_WR_CH_CONF_DISP_ID_SERIAL            (2 << 3)
  78 #define DC_WR_CH_CONF_DISP_ID_ASYNC             (3 << 4)
  79 #define DC_WR_CH_CONF_FIELD_MODE                (1 << 9)
  80 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL          (4 << 5)
  81 #define DC_WR_CH_CONF_PROG_TYPE_MASK            (7 << 5)
  82 #define DC_WR_CH_CONF_PROG_DI_ID                (1 << 2)
  83 #define DC_WR_CH_CONF_PROG_DISP_ID(i)           (((i) & 0x1) << 3)
  84
  85 #define IPU_DC_NUM_CHANNELS     10
  86
  87 struct ipu_dc_priv;
  88
  89 enum ipu_dc_map {
  90         IPU_DC_MAP_RGB24,
  91         IPU_DC_MAP_RGB565,
  92         IPU_DC_MAP_GBR24, /* TVEv2 */
  93         IPU_DC_MAP_BGR666,
  94         IPU_DC_MAP_LVDS666,
  95         IPU_DC_MAP_BGR24,
  96 };
  97
  98 struct ipu_dc {
  99         /* The display interface number assigned to this dc channel */
 100         unsigned int            di;
 101         void __iomem            *base;
 102         struct ipu_dc_priv      *priv;
 103         int                     chno;
 104         bool                    in_use;
 105 };
 106
 107 struct ipu_dc_priv {
 108         void __iomem            *dc_reg;
 109         void __iomem            *dc_tmpl_reg;
 110         struct ipu_soc          *ipu;
 111         struct device           *dev;
 112         struct ipu_dc           channels[IPU_DC_NUM_CHANNELS];
 113         struct mutex            mutex;
 114 };
 115
 116 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
 117 {
 118         u32 reg;
 119
 120         reg = readl(dc->base + DC_RL_CH(event));
 121         reg &= ~(0xffff << (16 * (event & 0x1)));
 122         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 123         writel(reg, dc->base + DC_RL_CH(event));
 124 }
 125
 126 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
 127                 int map, int wave, int glue, int sync, int stop)
 128 {
 129         struct ipu_dc_priv *priv = dc->priv;
 130         u32 reg1, reg2;
 131
 132         if (opcode == WCLK) {
 133                 reg1 = (operand << 20) & 0xfff00000;
 134                 reg2 = operand >> 12 | opcode << 1 | stop << 9;
 135         } else if (opcode == WRG) {
 136                 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
 137                 reg2 = operand >> 17 | opcode << 7 | stop << 9;
 138         } else {
 139                 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
 140                 reg2 = operand >> 12 | opcode << 4 | stop << 9;
 141         }
 142         writel(reg1, priv->dc_tmpl_reg + word * 8);
 143         writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
 144 }
 145
 146 static int ipu_pixfmt_to_map(u32 fmt)
 147 {
 148         switch (fmt) {
 149         case V4L2_PIX_FMT_RGB24:
 150                 return IPU_DC_MAP_RGB24;
 151         case V4L2_PIX_FMT_RGB565:
 152                 return IPU_DC_MAP_RGB565;
 153         case IPU_PIX_FMT_GBR24:
 154                 return IPU_DC_MAP_GBR24;
 155         case V4L2_PIX_FMT_BGR666:
 156                 return IPU_DC_MAP_BGR666;
 157         case v4l2_fourcc('L', 'V', 'D', '6'):
 158                 return IPU_DC_MAP_LVDS666;
 159         case V4L2_PIX_FMT_BGR24:
 160                 return IPU_DC_MAP_BGR24;
 161         default:
 162                 return -EINVAL;
 163         }
 164 }
 165
 166 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 167                 u32 pixel_fmt, u32 width)
 168 {
 169         struct ipu_dc_priv *priv = dc->priv;
 170         u32 reg = 0;
 171         int map;
 172
 173         dc->di = ipu_di_get_num(di);
 174
 175         map = ipu_pixfmt_to_map(pixel_fmt);
 176         if (map < 0) {
 177                 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
 178                 return map;
 179         }
 180
 181         if (interlaced) {
 182                 dc_link_event(dc, DC_EVT_NL, 0, 3);
 183                 dc_link_event(dc, DC_EVT_EOL, 0, 2);
 184                 dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
 185
 186                 /* Init template microcode */
 187                 dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
 188         } else {
 189                 if (dc->di) {
 190                         dc_link_event(dc, DC_EVT_NL, 2, 3);
 191                         dc_link_event(dc, DC_EVT_EOL, 3, 2);
 192                         dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
 193                         /* Init template microcode */
 194                         dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 195                         dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 196                         dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 197                         dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 198                 } else {
 199                         dc_link_event(dc, DC_EVT_NL, 5, 3);
 200                         dc_link_event(dc, DC_EVT_EOL, 6, 2);
 201                         dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
 202                         /* Init template microcode */
 203                         dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 204                         dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 205                         dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 206                         dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 207                 }
 208         }
 209         dc_link_event(dc, DC_EVT_NF, 0, 0);
 210         dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
 211         dc_link_event(dc, DC_EVT_EOF, 0, 0);
 212         dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
 213         dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
 214         dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
 215
 216         reg = readl(dc->base + DC_WR_CH_CONF);
 217         if (interlaced)
 218                 reg |= DC_WR_CH_CONF_FIELD_MODE;
 219         else
 220                 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
 221         writel(reg, dc->base + DC_WR_CH_CONF);
 222
 223         writel(0x0, dc->base + DC_WR_CH_ADDR);
 224         writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
 225
 226         ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
 227
 228         return 0;
 229 }
 230 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
 231
 232 void ipu_dc_enable_channel(struct ipu_dc *dc)
 233 {
 234         int di;
 235         u32 reg;
 236
 237         di = dc->di;
 238
 239         reg = readl(dc->base + DC_WR_CH_CONF);
 240         reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
 241         writel(reg, dc->base + DC_WR_CH_CONF);
 242 }
 243 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
 244
 245 void ipu_dc_disable_channel(struct ipu_dc *dc)
 246 {
 247         struct ipu_dc_priv *priv = dc->priv;
 248         u32 val;
 249         int irq = 0, timeout = 50;
 250
 251         if (dc->chno == 1)
 252                 irq = IPU_IRQ_DC_FC_1;
 253         else if (dc->chno == 5)
 254                 irq = IPU_IRQ_DP_SF_END;
 255         else
 256                 return;
 257
 258         /* should wait for the interrupt here */
 259         mdelay(50);
 260
 261         if (dc->di == 0)
 262                 val = 0x00000002;
 263         else
 264                 val = 0x00000020;
 265
 266         /* Wait for DC triple buffer to empty */
 267         while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
 268                 usleep_range(2000, 20000);
 269                 timeout -= 2;
 270                 if (timeout <= 0)
 271                         break;
 272         }
 273
 274         val = readl(dc->base + DC_WR_CH_CONF);
 275         val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 276         writel(val, dc->base + DC_WR_CH_CONF);
 277 }
 278 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
 279
 280 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
 281                 int byte_num, int offset, int mask)
 282 {
 283         int ptr = map * 3 + byte_num;
 284         u32 reg;
 285
 286         reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 287         reg &= ~(0xffff << (16 * (ptr & 0x1)));
 288         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 289         writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 290
 291         reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 292         reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
 293         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 294         writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
 295 }
 296
 297 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
 298 {
 299         u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 300
 301         writel(reg & ~(0xffff << (16 * (map & 0x1))),
 302                      priv->dc_reg + DC_MAP_CONF_PTR(map));
 303 }
 304
 305 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
 306 {
 307         struct ipu_dc_priv *priv = ipu->dc_priv;
 308         struct ipu_dc *dc;
 309
 310         if (channel >= IPU_DC_NUM_CHANNELS)
 311                 return ERR_PTR(-ENODEV);
 312
 313         dc = &priv->channels[channel];
 314
 315         mutex_lock(&priv->mutex);
 316
 317         if (dc->in_use) {
 318                 mutex_unlock(&priv->mutex);
 319                 return ERR_PTR(-EBUSY);
 320         }
 321
 322         dc->in_use = true;
 323
 324         mutex_unlock(&priv->mutex);
 325
 326         return dc;
 327 }
 328 EXPORT_SYMBOL_GPL(ipu_dc_get);
 329
 330 void ipu_dc_put(struct ipu_dc *dc)
 331 {
 332         struct ipu_dc_priv *priv = dc->priv;
 333
 334         mutex_lock(&priv->mutex);
 335         dc->in_use = false;
 336         mutex_unlock(&priv->mutex);
 337 }
 338 EXPORT_SYMBOL_GPL(ipu_dc_put);
 339
 340 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
 341                 unsigned long base, unsigned long template_base)
 342 {
 343         struct ipu_dc_priv *priv;
 344         static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
 345                 0x78, 0, 0x94, 0xb4};
 346         int i;
 347
 348         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 349         if (!priv)
 350                 return -ENOMEM;
 351
 352         mutex_init(&priv->mutex);
 353
 354         priv->dev = dev;
 355         priv->ipu = ipu;
 356         priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
 357         priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
 358         if (!priv->dc_reg || !priv->dc_tmpl_reg)
 359                 return -ENOMEM;
 360
 361         for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
 362                 priv->channels[i].chno = i;
 363                 priv->channels[i].priv = priv;
 364                 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
 365         }
 366
 367         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
 368                         DC_WR_CH_CONF_PROG_DI_ID,
 369                         priv->channels[1].base + DC_WR_CH_CONF);
 370         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
 371                         priv->channels[5].base + DC_WR_CH_CONF);
 372
 373         writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
 374                 priv->dc_reg + DC_GEN);
 375
 376         ipu->dc_priv = priv;
 377
 378         dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
 379                         base, template_base);
 380
 381         /* rgb24 */
 382         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
 383         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
 384         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
 385         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
 386
 387         /* rgb565 */
 388         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
 389         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
 390         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
 391         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
 392
 393         /* gbr24 */
 394         ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
 395         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
 396         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
 397         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
 398
 399         /* bgr666 */
 400         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
 401         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
 402         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
 403         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
 404
 405         /* lvds666 */
 406         ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
 407         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
 408         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
 409         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
 410
 411         /* bgr24 */
 412         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
 413         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
 414         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
 415         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
 416
 417         return 0;
 418 }
 419
 420 void ipu_dc_exit(struct ipu_soc *ipu)
 421 {
 422 }