drivers/staging/iio/cdc/ad7150.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AD7150 capacitive sensor driver supporting AD7150/1/6
   4  *
   5  * Copyright 2010-2011 Analog Devices Inc.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/device.h>
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/i2c.h>
  14 #include <linux/irq.h>
  15 #include <linux/module.h>
  16
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/sysfs.h>
  19 #include <linux/iio/events.h>
  20 /*
  21  * AD7150 registers definition
  22  */
  23
  24 #define AD7150_STATUS              0
  25 #define AD7150_STATUS_OUT1         BIT(3)
  26 #define AD7150_STATUS_OUT2         BIT(5)
  27 #define AD7150_CH1_DATA_HIGH       1
  28 #define AD7150_CH2_DATA_HIGH       3
  29 #define AD7150_CH1_AVG_HIGH        5
  30 #define AD7150_CH2_AVG_HIGH        7
  31 #define AD7150_CH1_SENSITIVITY     9
  32 #define AD7150_CH1_THR_HOLD_H      9
  33 #define AD7150_CH1_TIMEOUT         10
  34 #define AD7150_CH1_SETUP           11
  35 #define AD7150_CH2_SENSITIVITY     12
  36 #define AD7150_CH2_THR_HOLD_H      12
  37 #define AD7150_CH2_TIMEOUT         13
  38 #define AD7150_CH2_SETUP           14
  39 #define AD7150_CFG                 15
  40 #define AD7150_CFG_FIX             BIT(7)
  41 #define AD7150_PD_TIMER            16
  42 #define AD7150_CH1_CAPDAC          17
  43 #define AD7150_CH2_CAPDAC          18
  44 #define AD7150_SN3                 19
  45 #define AD7150_SN2                 20
  46 #define AD7150_SN1                 21
  47 #define AD7150_SN0                 22
  48 #define AD7150_ID                  23
  49
  50 /* AD7150 masks */
  51 #define AD7150_THRESHTYPE_MSK                   GENMASK(6, 5)
  52
  53 #define AD7150_CH_TIMEOUT_RECEDING              GENMASK(3, 0)
  54 #define AD7150_CH_TIMEOUT_APPROACHING           GENMASK(7, 4)
  55
  56 enum {
  57         AD7150,
  58         AD7151,
  59 };
  60
  61 /**
  62  * struct ad7150_chip_info - instance specific chip data
  63  * @client: i2c client for this device
  64  * @threshold: thresholds for simple capacitance value events
  65  * @thresh_sensitivity: threshold for simple capacitance offset
  66  *      from 'average' value.
  67  * @thresh_timeout: a timeout, in samples from the moment an
  68  *      adaptive threshold event occurs to when the average
  69  *      value jumps to current value.  Note made up of two fields,
  70  *      3:0 are for timeout receding - applies if below lower threshold
  71  *      7:4 are for timeout approaching - applies if above upper threshold
  72  * @state_lock: ensure consistent state of this structure wrt the
  73  *      hardware.
  74  * @interrupts: one or two interrupt numbers depending on device type.
  75  * @int_enabled: is a given interrupt currently enabled.
  76  * @type: threshold type
  77  * @dir: threshold direction
  78  */
  79 struct ad7150_chip_info {
  80         struct i2c_client *client;
  81         u16 threshold[2][2];
  82         u8 thresh_sensitivity[2][2];
  83         u8 thresh_timeout[2][2];
  84         struct mutex state_lock;
  85         int interrupts[2];
  86         bool int_enabled[2];
  87         enum iio_event_type type;
  88         enum iio_event_direction dir;
  89 };
  90
  91 /*
  92  * sysfs nodes
  93  */
  94
  95 static const u8 ad7150_addresses[][6] = {
  96         { AD7150_CH1_DATA_HIGH, AD7150_CH1_AVG_HIGH,
  97           AD7150_CH1_SETUP, AD7150_CH1_THR_HOLD_H,
  98           AD7150_CH1_SENSITIVITY, AD7150_CH1_TIMEOUT },
  99         { AD7150_CH2_DATA_HIGH, AD7150_CH2_AVG_HIGH,
 100           AD7150_CH2_SETUP, AD7150_CH2_THR_HOLD_H,
 101           AD7150_CH2_SENSITIVITY, AD7150_CH2_TIMEOUT },
 102 };
 103
 104 static int ad7150_read_raw(struct iio_dev *indio_dev,
 105                            struct iio_chan_spec const *chan,
 106                            int *val,
 107                            int *val2,
 108                            long mask)
 109 {
 110         int ret;
 111         struct ad7150_chip_info *chip = iio_priv(indio_dev);
 112         int channel = chan->channel;
 113
 114         switch (mask) {
 115         case IIO_CHAN_INFO_RAW:
 116                 ret = i2c_smbus_read_word_swapped(chip->client,
 117                                                   ad7150_addresses[channel][0]);
 118                 if (ret < 0)
 119                         return ret;
 120                 *val = ret;
 121
 122                 return IIO_VAL_INT;
 123         case IIO_CHAN_INFO_AVERAGE_RAW:
 124                 ret = i2c_smbus_read_word_swapped(chip->client,
 125                                                   ad7150_addresses[channel][1]);
 126                 if (ret < 0)
 127                         return ret;
 128                 *val = ret;
 129
 130                 return IIO_VAL_INT;
 131         case IIO_CHAN_INFO_SAMP_FREQ:
 132                 /* Strangely same for both 1 and 2 chan parts */
 133                 *val = 100;
 134                 return IIO_VAL_INT;
 135         default:
 136                 return -EINVAL;
 137         }
 138 }
 139
 140 static int ad7150_read_event_config(struct iio_dev *indio_dev,
 141                                     const struct iio_chan_spec *chan,
 142                                     enum iio_event_type type,
 143                                     enum iio_event_direction dir)
 144 {
 145         int ret;
 146         u8 threshtype;
 147         bool thrfixed;
 148         struct ad7150_chip_info *chip = iio_priv(indio_dev);
 149
 150         ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG);
 151         if (ret < 0)
 152                 return ret;
 153
 154         threshtype = FIELD_GET(AD7150_THRESHTYPE_MSK, ret);
 155
 156         /*check if threshold mode is fixed or adaptive*/
 157         thrfixed = FIELD_GET(AD7150_CFG_FIX, ret);
 158
 159         switch (type) {
 160         case IIO_EV_TYPE_THRESH_ADAPTIVE:
 161                 if (dir == IIO_EV_DIR_RISING)
 162                         return !thrfixed && (threshtype == 0x1);
 163                 return !thrfixed && (threshtype == 0x0);
 164         case IIO_EV_TYPE_THRESH:
 165                 if (dir == IIO_EV_DIR_RISING)
 166                         return thrfixed && (threshtype == 0x1);
 167                 return thrfixed && (threshtype == 0x0);
 168         default:
 169                 break;
 170         }
 171         return -EINVAL;
 172 }
 173
 174 /* state_lock should be held to ensure consistent state*/
 175
 176 static int ad7150_write_event_params(struct iio_dev *indio_dev,
 177                                      unsigned int chan,
 178                                      enum iio_event_type type,
 179                                      enum iio_event_direction dir)
 180 {
 181         struct ad7150_chip_info *chip = iio_priv(indio_dev);
 182         int rising = (dir == IIO_EV_DIR_RISING);
 183
 184         /* Only update value live, if parameter is in use */
 185         if ((type != chip->type) || (dir != chip->dir))
 186                 return 0;
 187
 188         switch (type) {
 189                 /* Note completely different from the adaptive versions */
 190         case IIO_EV_TYPE_THRESH: {
 191                 u16 value = chip->threshold[rising][chan];
 192                 return i2c_smbus_write_word_swapped(chip->client,
 193                                                     ad7150_addresses[chan][3],
 194                                                     value);
 195         }
 196         case IIO_EV_TYPE_THRESH_ADAPTIVE: {
 197                 int ret;
 198                 u8 sens, timeout;
 199
 200                 sens = chip->thresh_sensitivity[rising][chan];
 201                 ret = i2c_smbus_write_byte_data(chip->client,
 202                                                 ad7150_addresses[chan][4],
 203                                                 sens);
 204                 if (ret)
 205                         return ret;
 206
 207                 /*
 208                  * Single timeout register contains timeouts for both
 209                  * directions.
 210                  */
 211                 timeout = FIELD_PREP(AD7150_CH_TIMEOUT_APPROACHING,
 212                                      chip->thresh_timeout[1][chan]);
 213                 timeout |= FIELD_PREP(AD7150_CH_TIMEOUT_RECEDING,
 214                                       chip->thresh_timeout[0][chan]);
 215                 return i2c_smbus_write_byte_data(chip->client,
 216                                                  ad7150_addresses[chan][5],
 217                                                  timeout);
 218         }
 219         default:
 220                 return -EINVAL;
 221         }
 222 }
 223
 224 static int ad7150_write_event_config(struct iio_dev *indio_dev,
 225                                      const struct iio_chan_spec *chan,
 226                                      enum iio_event_type type,
 227                                      enum iio_event_direction dir, int state)
 228 {
 229         u8 thresh_type, cfg, adaptive;
 230         int ret;
 231         struct ad7150_chip_info *chip = iio_priv(indio_dev);
 232         int rising = (dir == IIO_EV_DIR_RISING);
 233
 234         /*
 235          * There is only a single shared control and no on chip
 236          * interrupt disables for the two interrupt lines.
 237          * So, enabling will switch the events configured to enable
 238          * whatever was most recently requested and if necessary enable_irq()
 239          * the interrupt and any disable will disable_irq() for that
 240          * channels interrupt.
 241          */
 242         if (!state) {
 243                 if ((chip->int_enabled[chan->channel]) &&
 244                     (type == chip->type) && (dir == chip->dir)) {
 245                         disable_irq(chip->interrupts[chan->channel]);
 246                         chip->int_enabled[chan->channel] = false;
 247                 }
 248                 return 0;
 249         }
 250
 251         mutex_lock(&chip->state_lock);
 252         if ((type != chip->type) || (dir != chip->dir)) {
 253
 254                 /*
 255                  * Need to temporarily disable both interrupts if
 256                  * enabled - this is to avoid races around changing
 257                  * config and thresholds.
 258                  * Note enable/disable_irq() are reference counted so
 259                  * no need to check if already enabled.
 260                  */
 261                 disable_irq(chip->interrupts[0]);
 262                 disable_irq(chip->interrupts[1]);
 263
 264                 ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG);
 265                 if (ret < 0)
 266                         goto error_ret;
 267
 268                 cfg = ret & ~((0x03 << 5) | BIT(7));
 269
 270                 switch (type) {
 271                 case IIO_EV_TYPE_THRESH_ADAPTIVE:
 272                         adaptive = 1;
 273                         if (rising)
 274                                 thresh_type = 0x1;
 275                         else
 276                                 thresh_type = 0x0;
 277                         break;
 278                 case IIO_EV_TYPE_THRESH:
 279                         adaptive = 0;
 280                         if (rising)
 281                                 thresh_type = 0x1;
 282                         else
 283                                 thresh_type = 0x0;
 284                         break;
 285                 default:
 286                         ret = -EINVAL;
 287                         goto error_ret;
 288                 }
 289
 290                 cfg |= (!adaptive << 7) | (thresh_type << 5);
 291
 292                 ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG, cfg);
 293                 if (ret < 0)
 294                         goto error_ret;
 295
 296                 /*
 297                  * There is a potential race condition here, but not easy
 298                  * to close given we can't disable the interrupt at the
 299                  * chip side of things. Rely on the status bit.
 300                  */
 301                 chip->type = type;
 302                 chip->dir = dir;
 303
 304                 /* update control attributes */
 305                 ret = ad7150_write_event_params(indio_dev, chan->channel, type,
 306                                                 dir);
 307                 if (ret)
 308                         goto error_ret;
 309                 /* reenable any irq's we disabled whilst changing mode */
 310                 enable_irq(chip->interrupts[0]);
 311                 enable_irq(chip->interrupts[1]);
 312         }
 313         if (!chip->int_enabled[chan->channel]) {
 314                 enable_irq(chip->interrupts[chan->channel]);
 315                 chip->int_enabled[chan->channel] = true;
 316         }
 317
 318 error_ret:
 319         mutex_unlock(&chip->state_lock);
 320
 321         return ret;
 322 }
 323
 324 static int ad7150_read_event_value(struct iio_dev *indio_dev,
 325                                    const struct iio_chan_spec *chan,
 326                                    enum iio_event_type type,
 327                                    enum iio_event_direction dir,
 328                                    enum iio_event_info info,
 329                                    int *val, int *val2)
 330 {
 331         struct ad7150_chip_info *chip = iio_priv(indio_dev);
 332         int rising = (dir == IIO_EV_DIR_RISING);
 333
 334         /* Complex register sharing going on here */
 335         switch (info) {
 336         case IIO_EV_INFO_VALUE:
 337                 switch (type) {
 338                 case IIO_EV_TYPE_THRESH_ADAPTIVE:
 339                         *val = chip->thresh_sensitivity[rising][chan->channel];
 340                         return IIO_VAL_INT;
 341                 case IIO_EV_TYPE_THRESH:
 342                         *val = chip->threshold[rising][chan->channel];
 343                         return IIO_VAL_INT;
 344                 default:
 345                         return -EINVAL;
 346                 }
 347         case IIO_EV_INFO_TIMEOUT:
 348                 *val = 0;
 349                 *val2 = chip->thresh_timeout[rising][chan->channel] * 10000;
 350                 return IIO_VAL_INT_PLUS_MICRO;
 351         default:
 352                 return -EINVAL;
 353         }
 354 }
 355
 356 static int ad7150_write_event_value(struct iio_dev *indio_dev,
 357                                     const struct iio_chan_spec *chan,
 358                                     enum iio_event_type type,
 359                                     enum iio_event_direction dir,
 360                                     enum iio_event_info info,
 361                                     int val, int val2)
 362 {
 363         int ret;
 364         struct ad7150_chip_info *chip = iio_priv(indio_dev);
 365         int rising = (dir == IIO_EV_DIR_RISING);
 366
 367         mutex_lock(&chip->state_lock);
 368         switch (info) {
 369         case IIO_EV_INFO_VALUE:
 370                 switch (type) {
 371                 case IIO_EV_TYPE_THRESH_ADAPTIVE:
 372                         chip->thresh_sensitivity[rising][chan->channel] = val;
 373                         break;
 374                 case IIO_EV_TYPE_THRESH:
 375                         chip->threshold[rising][chan->channel] = val;
 376                         break;
 377                 default:
 378                         ret = -EINVAL;
 379                         goto error_ret;
 380                 }
 381                 break;
 382         case IIO_EV_INFO_TIMEOUT: {
 383                 /*
 384                  * Raw timeout is in cycles of 10 msecs as long as both
 385                  * channels are enabled.
 386                  * In terms of INT_PLUS_MICRO, that is in units of 10,000
 387                  */
 388                 int timeout = val2 / 10000;
 389
 390                 if (val != 0 || timeout < 0 || timeout > 15 || val2 % 10000) {
 391                         ret = -EINVAL;
 392                         goto error_ret;
 393                 }
 394
 395                 chip->thresh_timeout[rising][chan->channel] = timeout;
 396                 break;
 397         }
 398         default:
 399                 ret = -EINVAL;
 400                 goto error_ret;
 401         }
 402
 403         /* write back if active */
 404         ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir);
 405
 406 error_ret:
 407         mutex_unlock(&chip->state_lock);
 408         return ret;
 409 }
 410
 411 static const struct iio_event_spec ad7150_events[] = {
 412         {
 413                 .type = IIO_EV_TYPE_THRESH,
 414                 .dir = IIO_EV_DIR_RISING,
 415                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 416                         BIT(IIO_EV_INFO_ENABLE),
 417         }, {
 418                 .type = IIO_EV_TYPE_THRESH,
 419                 .dir = IIO_EV_DIR_FALLING,
 420                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 421                         BIT(IIO_EV_INFO_ENABLE),
 422         }, {
 423                 .type = IIO_EV_TYPE_THRESH_ADAPTIVE,
 424                 .dir = IIO_EV_DIR_RISING,
 425                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 426                         BIT(IIO_EV_INFO_ENABLE) |
 427                         BIT(IIO_EV_INFO_TIMEOUT),
 428         }, {
 429                 .type = IIO_EV_TYPE_THRESH_ADAPTIVE,
 430                 .dir = IIO_EV_DIR_FALLING,
 431                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 432                         BIT(IIO_EV_INFO_ENABLE) |
 433                         BIT(IIO_EV_INFO_TIMEOUT),
 434         },
 435 };
 436
 437 #define AD7150_CAPACITANCE_CHAN(_chan)  {                       \
 438                 .type = IIO_CAPACITANCE,                        \
 439                 .indexed = 1,                                   \
 440                 .channel = _chan,                               \
 441                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
 442                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),                 \
 443                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 444                 .event_spec = ad7150_events,                    \
 445                 .num_event_specs = ARRAY_SIZE(ad7150_events),   \
 446         }
 447
 448 #define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan)   {               \
 449                 .type = IIO_CAPACITANCE,                        \
 450                 .indexed = 1,                                   \
 451                 .channel = _chan,                               \
 452                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
 453                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),                 \
 454                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 455         }
 456
 457 static const struct iio_chan_spec ad7150_channels[] = {
 458         AD7150_CAPACITANCE_CHAN(0),
 459         AD7150_CAPACITANCE_CHAN(1),
 460 };
 461
 462 static const struct iio_chan_spec ad7150_channels_no_irq[] = {
 463         AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
 464         AD7150_CAPACITANCE_CHAN_NO_IRQ(1),
 465 };
 466
 467 static const struct iio_chan_spec ad7151_channels[] = {
 468         AD7150_CAPACITANCE_CHAN(0),
 469 };
 470
 471 static const struct iio_chan_spec ad7151_channels_no_irq[] = {
 472         AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
 473 };
 474
 475 static irqreturn_t __ad7150_event_handler(void *private, u8 status_mask,
 476                                           int channel)
 477 {
 478         struct iio_dev *indio_dev = private;
 479         struct ad7150_chip_info *chip = iio_priv(indio_dev);
 480         s64 timestamp = iio_get_time_ns(indio_dev);
 481         int int_status;
 482
 483         int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS);
 484         if (int_status < 0)
 485                 return IRQ_HANDLED;
 486
 487         if (!(int_status & status_mask))
 488                 return IRQ_HANDLED;
 489
 490         iio_push_event(indio_dev,
 491                        IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, channel,
 492                                             chip->type, chip->dir),
 493                        timestamp);
 494
 495         return IRQ_HANDLED;
 496 }
 497
 498 static irqreturn_t ad7150_event_handler_ch1(int irq, void *private)
 499 {
 500         return __ad7150_event_handler(private, AD7150_STATUS_OUT1, 0);
 501 }
 502
 503 static irqreturn_t ad7150_event_handler_ch2(int irq, void *private)
 504 {
 505         return __ad7150_event_handler(private, AD7150_STATUS_OUT2, 1);
 506 }
 507
 508 static IIO_CONST_ATTR(in_capacitance_thresh_adaptive_timeout_available,
 509                       "[0 0.01 0.15]");
 510
 511 static struct attribute *ad7150_event_attributes[] = {
 512         &iio_const_attr_in_capacitance_thresh_adaptive_timeout_available
 513         .dev_attr.attr,
 514         NULL,
 515 };
 516
 517 static const struct attribute_group ad7150_event_attribute_group = {
 518         .attrs = ad7150_event_attributes,
 519         .name = "events",
 520 };
 521
 522 static const struct iio_info ad7150_info = {
 523         .event_attrs = &ad7150_event_attribute_group,
 524         .read_raw = &ad7150_read_raw,
 525         .read_event_config = &ad7150_read_event_config,
 526         .write_event_config = &ad7150_write_event_config,
 527         .read_event_value = &ad7150_read_event_value,
 528         .write_event_value = &ad7150_write_event_value,
 529 };
 530
 531 static const struct iio_info ad7150_info_no_irq = {
 532         .read_raw = &ad7150_read_raw,
 533 };
 534
 535 static int ad7150_probe(struct i2c_client *client,
 536                         const struct i2c_device_id *id)
 537 {
 538         int ret;
 539         struct ad7150_chip_info *chip;
 540         struct iio_dev *indio_dev;
 541
 542         indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
 543         if (!indio_dev)
 544                 return -ENOMEM;
 545
 546         chip = iio_priv(indio_dev);
 547         mutex_init(&chip->state_lock);
 548         chip->client = client;
 549
 550         indio_dev->name = id->name;
 551
 552         indio_dev->modes = INDIO_DIRECT_MODE;
 553
 554         chip->interrupts[0] = fwnode_irq_get(dev_fwnode(&client->dev), 0);
 555         if (chip->interrupts[0] < 0)
 556                 return chip->interrupts[0];
 557         if (id->driver_data == AD7150) {
 558                 chip->interrupts[1] = fwnode_irq_get(dev_fwnode(&client->dev), 1);
 559                 if (chip->interrupts[1] < 0)
 560                         return chip->interrupts[1];
 561         }
 562         if (chip->interrupts[0] &&
 563             (id->driver_data == AD7151 || chip->interrupts[1])) {
 564                 irq_set_status_flags(chip->interrupts[0], IRQ_NOAUTOEN);
 565                 ret = devm_request_threaded_irq(&client->dev,
 566                                                 chip->interrupts[0],
 567                                                 NULL,
 568                                                 &ad7150_event_handler_ch1,
 569                                                 IRQF_TRIGGER_RISING |
 570                                                 IRQF_ONESHOT,
 571                                                 "ad7150_irq1",
 572                                                 indio_dev);
 573                 if (ret)
 574                         return ret;
 575
 576                 indio_dev->info = &ad7150_info;
 577                 switch (id->driver_data) {
 578                 case AD7150:
 579                         indio_dev->channels = ad7150_channels;
 580                         indio_dev->num_channels = ARRAY_SIZE(ad7150_channels);
 581                         irq_set_status_flags(chip->interrupts[1], IRQ_NOAUTOEN);
 582                         ret = devm_request_threaded_irq(&client->dev,
 583                                                         chip->interrupts[1],
 584                                                         NULL,
 585                                                         &ad7150_event_handler_ch2,
 586                                                         IRQF_TRIGGER_RISING |
 587                                                         IRQF_ONESHOT,
 588                                                         "ad7150_irq2",
 589                                                         indio_dev);
 590                         if (ret)
 591                                 return ret;
 592                         break;
 593                 case AD7151:
 594                         indio_dev->channels = ad7151_channels;
 595                         indio_dev->num_channels = ARRAY_SIZE(ad7151_channels);
 596                         break;
 597                 default:
 598                         return -EINVAL;
 599                 }
 600
 601         } else {
 602                 indio_dev->info = &ad7150_info_no_irq;
 603                 switch (id->driver_data) {
 604                 case AD7150:
 605                         indio_dev->channels = ad7150_channels_no_irq;
 606                         indio_dev->num_channels =
 607                                 ARRAY_SIZE(ad7150_channels_no_irq);
 608                         break;
 609                 case AD7151:
 610                         indio_dev->channels = ad7151_channels_no_irq;
 611                         indio_dev->num_channels =
 612                                 ARRAY_SIZE(ad7151_channels_no_irq);
 613                         break;
 614                 default:
 615                         return -EINVAL;
 616                 }
 617         }
 618
 619         return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
 620 }
 621
 622 static const struct i2c_device_id ad7150_id[] = {
 623         { "ad7150", AD7150 },
 624         { "ad7151", AD7151 },
 625         { "ad7156", AD7150 },
 626         {}
 627 };
 628
 629 MODULE_DEVICE_TABLE(i2c, ad7150_id);
 630
 631 static struct i2c_driver ad7150_driver = {
 632         .driver = {
 633                 .name = "ad7150",
 634         },
 635         .probe = ad7150_probe,
 636         .id_table = ad7150_id,
 637 };
 638 module_i2c_driver(ad7150_driver);
 639
 640 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
 641 MODULE_DESCRIPTION("Analog Devices AD7150/1/6 capacitive sensor driver");
 642 MODULE_LICENSE("GPL v2");