1 // SPDX-License-Identifier: GPL-2.0+
3 #include <linux/kernel.h>
4 #include <linux/init.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/device.h>
8 #include <linux/string.h>
9 #include <linux/slab.h>
11 #include <linux/platform_device.h>
13 #include <linux/of_address.h>
14 #include <linux/firmware.h>
19 static inline void byte0_out(unsigned char data);
20 static inline void byte1_out(unsigned char data);
21 static inline void xl_cclk_b(int32_t i);
23 /* Assert and Deassert CCLK */
24 void xl_shift_cclk(int count)
28 for (i = 0; i < count; i++) {
34 int xl_supported_prog_bus_width(enum wbus bus_bytes)
42 pr_err("unsupported program bus width %d\n", bus_bytes);
49 /* Serialize byte and clock each bit on target's DIN and CCLK pins */
50 void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata)
53 * supports 1 and 2 bytes programming mode
55 if (likely(bus_byte == bus_2byte))
63 * generic bit swap for xilinx SYSTEMMAP FPGA programming
65 void xl_program_b(int32_t i)
69 void xl_rdwr_b(int32_t i)
73 void xl_csi_b(int32_t i)
77 int xl_get_init_b(void)
82 int xl_get_done_b(void)
87 static inline void byte0_out(unsigned char data)
91 static inline void byte1_out(unsigned char data)
95 static inline void xl_cclk_b(int32_t i)
100 * configurable per device type for different I/O config