1 /* Copyright (C) 2003-2005 SBE, Inc.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17 #include <linux/hdlc.h>
18 #include "pmcc4_sysdep.h"
19 #include "sbecom_inline_linux.h"
23 #include "comet_tables.h"
25 extern int cxt1e1_log_level;
27 #define COMET_NUM_SAMPLES 24 /* Number of entries in the waveform table */
28 #define COMET_NUM_UNITS 5 /* Number of points per entry in table */
30 /* forward references */
31 static void SetPwrLevel(comet_t *comet);
32 static void WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table);
33 static void WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
36 void *TWV_table[12] = {
37 TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
38 TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
39 TWVShortHaul4, TWVShortHaul5,
40 /** PORT POINT - 75 Ohm not supported **/
47 lbo_tbl_lkup(int t1, int lbo) {
48 /* error switches to default */
49 if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
51 /* default T1 waveform table */
54 /* default E1 waveform table */
57 /* make index ZERO relative */
61 void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
66 u_int8_t tix = CFG_LBO_LH0;
67 isT1mode = IS_FRAME_ANY_T1(port_mode);
70 /* Select T1 Mode & PIO output enabled */
71 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
72 /* default T1 waveform table */
73 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
75 /* Select E1 Mode & PIO output enabled */
76 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
77 /* default E1 waveform table */
78 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
81 if (moreParams & CFG_LBO_MASK)
82 /* dial-in requested waveform table */
83 tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
84 /* Tx line Intfc cfg Set for analog & no special patterns */
85 /* Transmit Line Interface Config. */
86 pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
87 /* master test Ignore Test settings for now */
88 /* making sure it's Default value */
89 pci_write_32((u_int32_t *) &comet->mtest, 0x00);
90 /* Turn on Center (CENT) and everything else off */
92 pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
93 /* Set Jitter Attenuation to recommend T1 values */
95 /* RJAT Divider N1 Control */
96 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
97 /* RJAT Divider N2 Control */
98 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
100 /* RJAT Divider N1 Control */
101 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
102 /* RJAT Divider N2 Control */
103 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
106 /* Turn on Center (CENT) and everything else off */
108 pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
110 /* Do not bypass jitter attenuation and bypass elastic store */
112 pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
114 /* TJAT ctrl & TJAT divider ctrl */
115 /* Set Jitter Attenuation to recommended T1 values */
117 /* TJAT Divider N1 Control */
118 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
119 /* TJAT Divider N2 Control */
120 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
122 /* TJAT Divider N1 Control */
123 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
124 /* TJAT Divider N2 Control */
125 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
128 /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
130 /* Select 193-bit frame format */
132 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
133 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
135 /* Select 256-bit frame format */
136 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
137 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
138 /* disable T1 data link receive */
139 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
140 /* disable T1 data link transmit */
141 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
144 /* the following is a default value */
145 /* Enable 8 out of 10 validation */
146 /* t1RBOC enable(BOC:BitOriented Code) */
147 pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
149 /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
150 /* 6 bit down, 5 bit up (assert) */
151 pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
152 /* line loopback activate pattern */
153 pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
154 /* deactivate code pattern (i.e.001) */
155 pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
157 /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
158 /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
159 /* 60: t1 ALMI cfg */
160 /* Configure Line Coding */
166 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
167 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
168 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
170 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
171 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
175 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
176 /* Bit 5: T1 DataLink Enable */
177 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
178 /* 5: T1 DataLink Enable */
179 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
181 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
183 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
185 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
187 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
190 case CFG_FRAME_E1PLAIN:
191 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
192 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
193 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
194 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
197 case CFG_FRAME_E1CAS:
198 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
199 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
200 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
201 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
204 case CFG_FRAME_E1CRC:
205 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
206 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
207 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
208 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
211 case CFG_FRAME_E1CRC_CAS:
212 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
213 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
214 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
215 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
218 case CFG_FRAME_SF_AMI:
219 /* Enable AMI Line Decoding */
220 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
221 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
222 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
223 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
224 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
227 case CFG_FRAME_ESF_AMI:
228 /* Enable AMI Line Decoding */
229 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
230 /* 5: T1 DataLink Enable */
231 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
232 /* 5: T1 DataLink Enable */
233 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
234 /* Bit 4:ESF 5:ESFFA */
235 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
237 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
239 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
241 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
244 case CFG_FRAME_E1PLAIN_AMI:
245 /* Enable AMI Line Decoding */
246 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
247 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
248 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
249 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
252 case CFG_FRAME_E1CAS_AMI:
253 /* Enable AMI Line Decoding */
254 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
255 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
256 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
257 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
260 case CFG_FRAME_E1CRC_AMI:
261 /* Enable AMI Line Decoding */
262 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
263 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
264 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
265 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
268 case CFG_FRAME_E1CRC_CAS_AMI:
269 /* Enable AMI Line Decoding */
270 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
271 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
272 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
273 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
278 * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
279 * CMODE=1: Clock slave mode with BRCLK as an input,
280 * DE=0: Use falling edge of BRCLK for data,
281 * FE=0: Use falling edge of BRCLK for frame,
282 * CMS=0: Use backplane freq,
287 /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
288 /* note "rate bits can only be set once after reset" */
291 /* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
292 /* rate = 1.544 Mb/s */
294 /* Comet 0 Master Mode(CMODE=0) */
295 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
296 /* rate = 2.048 Mb/s */
298 /* Comet 0 Master Mode(CMODE=0) */
299 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
301 /* 31: BRIF frame pulse cfg 06: tx timing options */
303 /* Master Mode i.e.FPMODE=0 (@0x20) */
304 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
305 if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
307 if (cxt1e1_log_level >= LOG_SBEBUG12)
308 pr_info(">> %s: clockmaster internal clock\n", __func__);
309 /* internal oscillator */
310 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
312 /* external clock source */
313 if (cxt1e1_log_level >= LOG_SBEBUG12)
314 pr_info(">> %s: clockmaster external clock\n", __func__);
315 /* loop timing(external) */
316 pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
322 /* Slave Mode(CMODE=1, see above) */
323 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
325 /* Slave Mode(CMODE=1)*/
326 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
327 /* Slave Mode i.e. FPMODE=1 (@0x20) */
328 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
329 if (cxt1e1_log_level >= LOG_SBEBUG12)
330 pr_info(">> %s: clockslave internal clock\n", __func__);
331 /* oscillator timing */
332 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
335 /* 32: BRIF parity F-bit cfg */
336 /* Totem-pole operation */
337 /* Receive Backplane Parity/F-bit */
338 pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
340 /* dc: RLPS equalizer V ref */
343 /* RLPS Equalizer Voltage */
344 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
346 /* RLPS Equalizer Voltage */
347 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
349 /* Reserved bit set and SQUELCH enabled */
350 /* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
351 /* RLPS Configuration Status */
352 pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
355 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
358 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
361 /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
362 /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
363 /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
364 /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
365 /*** Transmit side is always an Input, Slave Clock*/
366 /* 40: BTIF cfg 41: loop timing(external) */
367 /*BTIF frame pulse cfg */
369 /* BTIF Configuration Reg. */
370 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
372 /* BTIF Configuration Reg. */
373 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
374 /* BTIF Frame Pulse Config. */
375 pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
377 /* 0a: master diag 06: tx timing options */
378 /* if set Comet to loop back */
380 /* Comets set to normal */
381 pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
383 /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */
384 /* Store is enabled. */
386 WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
388 WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
390 WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
395 ** Name: WrtXmtWaveform
396 ** Description: Formulate the Data for the Pulse Waveform Storage
397 ** Write register, (F2), from the sample and unit inputs.
398 ** Write the data to the Pulse Waveform Storage Data register.
402 WrtXmtWaveform(ci_t *ci, comet_t *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
404 u_int8_t WaveformAddr;
406 WaveformAddr = (sample << 3) + (unit & 7);
407 pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
408 /* for write order preservation when Optimizing driver */
410 pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
414 ** Name: WrtXmtWaveformTbl
415 ** Description: Fill in the Transmit Waveform Values
416 ** for driving the transmitter DAC.
420 WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
421 u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
423 u_int32_t sample, unit;
425 for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
427 for (unit = 0; unit < COMET_NUM_UNITS; unit++)
428 WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
431 /* Enable transmitter and set output amplitude */
432 pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
437 ** Name: WrtXmtWaveform
438 ** Description: Fill in the Receive Equalizer RAM from the desired
442 ** Remarks: Per PM4351 Device Errata, Receive Equalizer RAM Initialization
443 ** is coded with early setup of indirect address.
447 WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
450 volatile u_int32_t value;
452 for (ramaddr = 0; ramaddr < 256; ramaddr++) {
453 /*** the following lines are per Errata 7, 2.5 ***/
455 /* Set up for a read operation */
456 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
457 /* for write order preservation when Optimizing driver */
459 /* write the addr, initiate a read */
460 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
461 /* for write order preservation when Optimizing driver */
464 * wait 3 line rate clock cycles to ensure address bits are
465 * captured by T1/E1 clock
468 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
473 pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
474 pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
475 pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
476 pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
477 /* for write order preservation when Optimizing driver */
480 /* Storing RAM address, causes RAM to be updated */
482 /* Set up for a write operation */
483 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
484 /* for write order preservation when optimizing driver */
486 /* write the addr, initiate a read */
487 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
488 /* for write order preservation when optimizing driver */
492 * wait 3 line rate clock cycles to ensure address bits are captured
495 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
499 /* Enable Equalizer & set it to use 256 periods */
500 pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
506 ** Description: Implement power level setting algorithm described below
511 SetPwrLevel(comet_t *comet)
513 volatile u_int32_t temp;
516 ** Algorithm to Balance the Power Distribution of Ttip Tring
519 ** Write 0x01 to register F4
520 ** Write another 0x01 to register F4
522 ** Remove the 0x01 bit by Anding register F4 with 0xFE
523 ** Write the resultant value to register F4
524 ** Repeat these steps for register F5
525 ** Write 0x01 to register F6
527 /* XLPG Fuse Data Select */
528 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
529 /* XLPG Analog Test Positive control */
530 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
531 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
532 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
533 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
534 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
535 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
536 /* XLPG Analog Test Negative control */
537 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
538 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
540 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
546 ** Description: Set up the selected Comet's clock edge drive for both
547 ** the transmit out the analog side and receive to the
553 SetCometOps(comet_t *comet)
555 volatile u_int8_t rd_value;
557 if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
559 /* read the BRIF Configuration */
560 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
562 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
563 /* read the BRIF Frame Pulse Configuration */
564 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
566 pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
568 /* read the BRIF Configuration */
569 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
571 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
572 /* read the BRIF Frame Pulse Configuration */
573 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
575 pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
580 /*** End-of-File ***/