2 * comedi/drivers/s626.c
3 * Sensoray s626 Comedi driver
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 * Based on Sensoray Model 626 Linux driver Version 0.2
9 * Copyright (C) 2002-2004 Sensoray Co., Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
24 * Description: Sensoray 626 driver
25 * Devices: [Sensoray] 626 (s626)
26 * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
27 * Updated: Fri, 15 Feb 2008 10:28:42 +0000
28 * Status: experimental
30 * Configuration options: not applicable, uses PCI auto config
32 * INSN_CONFIG instructions:
40 * s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
41 * supported configuration options:
42 * INSN_CONFIG_DIO_QUERY
47 * Every channel must be configured before reading.
51 * insn.insn=INSN_CONFIG; //configuration instruction
52 * insn.n=1; //number of operation (must be 1)
53 * insn.data=&initialvalue; //initial value loaded into encoder
54 * //during configuration
55 * insn.subdev=5; //encoder subdevice
56 * insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
59 * comedi_do_insn(cf,&insn); //executing configuration
62 #include <linux/module.h>
63 #include <linux/delay.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/kernel.h>
67 #include <linux/types.h>
69 #include "../comedidev.h"
71 #include "comedi_fc.h"
74 struct s626_buffer_dma {
75 dma_addr_t physical_base;
81 uint8_t ai_cmd_running; /* ai_cmd is running */
82 uint8_t ai_continuous; /* continuous acquisition */
83 int ai_sample_count; /* number of samples to acquire */
84 unsigned int ai_sample_timer; /* time between samples in
85 * units of the timer */
86 int ai_convert_count; /* conversion counter */
87 unsigned int ai_convert_timer; /* time between conversion in
88 * units of the timer */
89 uint16_t counter_int_enabs; /* counter interrupt enable mask
90 * for MISC2 register */
91 uint8_t adc_items; /* number of items in ADC poll list */
92 struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
94 struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
95 * and hold DAC data */
96 uint32_t *dac_wbuf; /* pointer to logical adrs of DMA buffer
97 * used to hold DAC data */
98 uint16_t dacpol; /* image of DAC polarity register */
99 uint8_t trim_setpoint[12]; /* images of TrimDAC setpoints */
100 uint32_t i2c_adrs; /* I2C device address for onboard EEPROM
101 * (board rev dependent) */
102 unsigned int ao_readback[S626_DAC_CHANNELS];
105 /* COUNTER OBJECT ------------------------------------------------ */
106 struct s626_enc_info {
107 /* Pointers to functions that differ for A and B counters: */
108 /* Return clock enable. */
109 uint16_t(*get_enable)(struct comedi_device *dev,
110 const struct s626_enc_info *k);
111 /* Return interrupt source. */
112 uint16_t(*get_int_src)(struct comedi_device *dev,
113 const struct s626_enc_info *k);
114 /* Return preload trigger source. */
115 uint16_t(*get_load_trig)(struct comedi_device *dev,
116 const struct s626_enc_info *k);
117 /* Return standardized operating mode. */
118 uint16_t(*get_mode)(struct comedi_device *dev,
119 const struct s626_enc_info *k);
120 /* Generate soft index strobe. */
121 void (*pulse_index)(struct comedi_device *dev,
122 const struct s626_enc_info *k);
123 /* Program clock enable. */
124 void (*set_enable)(struct comedi_device *dev,
125 const struct s626_enc_info *k, uint16_t enab);
126 /* Program interrupt source. */
127 void (*set_int_src)(struct comedi_device *dev,
128 const struct s626_enc_info *k, uint16_t int_source);
129 /* Program preload trigger source. */
130 void (*set_load_trig)(struct comedi_device *dev,
131 const struct s626_enc_info *k, uint16_t trig);
132 /* Program standardized operating mode. */
133 void (*set_mode)(struct comedi_device *dev,
134 const struct s626_enc_info *k, uint16_t setup,
135 uint16_t disable_int_src);
136 /* Reset event capture flags. */
137 void (*reset_cap_flags)(struct comedi_device *dev,
138 const struct s626_enc_info *k);
140 uint16_t my_cra; /* address of CRA register */
141 uint16_t my_crb; /* address of CRB register */
142 uint16_t my_latch_lsw; /* address of Latch least-significant-word
144 uint16_t my_event_bits[4]; /* bit translations for IntSrc -->RDMISC2 */
147 /* Counter overflow/index event flag masks for RDMISC2. */
148 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
149 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
150 #define S626_EVBITS(C) { 0, S626_OVERMASK(C), S626_INDXMASK(C), \
151 S626_OVERMASK(C) | S626_INDXMASK(C) }
154 * Translation table to map IntSrc into equivalent RDMISC2 event flag bits.
155 * static const uint16_t s626_event_bits[][4] =
156 * { S626_EVBITS(0), S626_EVBITS(1), S626_EVBITS(2), S626_EVBITS(3),
157 * S626_EVBITS(4), S626_EVBITS(5) };
161 * Enable/disable a function or test status bit(s) that are accessed
162 * through Main Control Registers 1 or 2.
164 static void s626_mc_enable(struct comedi_device *dev,
165 unsigned int cmd, unsigned int reg)
167 struct s626_private *devpriv = dev->private;
168 unsigned int val = (cmd << 16) | cmd;
171 writel(val, devpriv->mmio + reg);
174 static void s626_mc_disable(struct comedi_device *dev,
175 unsigned int cmd, unsigned int reg)
177 struct s626_private *devpriv = dev->private;
179 writel(cmd << 16 , devpriv->mmio + reg);
183 static bool s626_mc_test(struct comedi_device *dev,
184 unsigned int cmd, unsigned int reg)
186 struct s626_private *devpriv = dev->private;
189 val = readl(devpriv->mmio + reg);
191 return (val & cmd) ? true : false;
194 #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4)
196 /* Write a time slot control record to TSL2. */
197 #define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2))
199 static const struct comedi_lrange s626_range_table = {
207 * Execute a DEBI transfer. This must be called from within a critical section.
209 static void s626_debi_transfer(struct comedi_device *dev)
211 struct s626_private *devpriv = dev->private;
213 /* Initiate upload of shadow RAM to DEBI control register */
214 s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
217 * Wait for completion of upload from shadow RAM to
218 * DEBI control register.
220 while (!s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
223 /* Wait until DEBI transfer is done */
224 while (readl(devpriv->mmio + S626_P_PSR) & S626_PSR_DEBI_S)
229 * Read a value from a gate array register.
231 static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
233 struct s626_private *devpriv = dev->private;
235 /* Set up DEBI control register value in shadow RAM */
236 writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD);
238 /* Execute the DEBI transfer. */
239 s626_debi_transfer(dev);
241 return readl(devpriv->mmio + S626_P_DEBIAD);
245 * Write a value to a gate array register.
247 static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
250 struct s626_private *devpriv = dev->private;
252 /* Set up DEBI control register value in shadow RAM */
253 writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD);
254 writel(wdata, devpriv->mmio + S626_P_DEBIAD);
256 /* Execute the DEBI transfer. */
257 s626_debi_transfer(dev);
261 * Replace the specified bits in a gate array register. Imports: mask
262 * specifies bits that are to be preserved, wdata is new value to be
263 * or'd with the masked original.
265 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
266 unsigned int mask, unsigned int wdata)
268 struct s626_private *devpriv = dev->private;
272 writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD);
273 s626_debi_transfer(dev);
275 writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD);
276 val = readl(devpriv->mmio + S626_P_DEBIAD);
279 writel(val & 0xffff, devpriv->mmio + S626_P_DEBIAD);
280 s626_debi_transfer(dev);
283 /* ************** EEPROM ACCESS FUNCTIONS ************** */
285 static uint32_t s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
287 struct s626_private *devpriv = dev->private;
290 /* Write I2C command to I2C Transfer Control shadow register */
291 writel(val, devpriv->mmio + S626_P_I2CCTRL);
294 * Upload I2C shadow registers into working registers and
295 * wait for upload confirmation.
297 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
298 while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2))
301 /* Wait until I2C bus transfer is finished or an error occurs */
303 ctrl = readl(devpriv->mmio + S626_P_I2CCTRL);
304 } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
306 /* Return non-zero if I2C error occurred */
307 return ctrl & S626_I2C_ERR;
310 /* Read uint8_t from EEPROM. */
311 static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
313 struct s626_private *devpriv = dev->private;
316 * Send EEPROM target address:
317 * Byte2 = I2C command: write to I2C EEPROM device.
318 * Byte1 = EEPROM internal target address.
321 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
323 S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
324 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
325 /* Abort function and declare error if handshake failed. */
329 * Execute EEPROM read:
330 * Byte2 = I2C command: read from I2C EEPROM device.
331 * Byte1 receives uint8_t from EEPROM.
334 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
335 (devpriv->i2c_adrs | 1)) |
336 S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
337 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
338 /* Abort function and declare error if handshake failed. */
341 return (readl(devpriv->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
344 /* *********** DAC FUNCTIONS *********** */
346 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
347 static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
349 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
350 static const uint8_t s626_trimadrs[] = {
351 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
355 * Private helper function: Transmit serial data to DAC via Audio
356 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
357 * dacpol contains valid target image.
359 static void s626_send_dac(struct comedi_device *dev, uint32_t val)
361 struct s626_private *devpriv = dev->private;
363 /* START THE SERIAL CLOCK RUNNING ------------- */
366 * Assert DAC polarity control and enable gating of DAC serial clock
367 * and audio bit stream signals. At this point in time we must be
368 * assured of being in time slot 0. If we are not in slot 0, the
369 * serial clock and audio stream signals will be disabled; this is
370 * because the following s626_debi_write statement (which enables
371 * signals to be passed through the gate array) would execute before
372 * the trailing edge of WS1/WS3 (which turns off the signals), thus
373 * causing the signals to be inactive during the DAC write.
375 s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
377 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
379 /* Copy DAC setpoint value to DAC's output DMA buffer. */
380 /* writel(val, devpriv->mmio + (uint32_t)devpriv->dac_wbuf); */
381 *devpriv->dac_wbuf = val;
384 * Enable the output DMA transfer. This will cause the DMAC to copy
385 * the DAC's data value to A2's output FIFO. The DMA transfer will
386 * then immediately terminate because the protection address is
387 * reached upon transfer of the first DWORD value.
389 s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
391 /* While the DMA transfer is executing ... */
394 * Reset Audio2 output FIFO's underflow flag (along with any
395 * other FIFO underflow/overflow flags). When set, this flag
396 * will indicate that we have emerged from slot 0.
398 writel(S626_ISR_AFOU, devpriv->mmio + S626_P_ISR);
401 * Wait for the DMA transfer to finish so that there will be data
402 * available in the FIFO when time slot 1 tries to transfer a DWORD
403 * from the FIFO to the output buffer register. We test for DMA
404 * Done by polling the DMAC enable flag; this flag is automatically
405 * cleared when the transfer has finished.
407 while (readl(devpriv->mmio + S626_P_MC1) & S626_MC1_A2OUT)
410 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
413 * FIFO data is now available, so we enable execution of time slots
414 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
415 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
418 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
419 devpriv->mmio + S626_VECTPORT(0));
422 * Wait for slot 1 to execute to ensure that the Packet will be
423 * transmitted. This is detected by polling the Audio2 output FIFO
424 * underflow flag, which will be set when slot 1 execution has
425 * finished transferring the DAC's data DWORD from the output FIFO
426 * to the output buffer register.
428 while (!(readl(devpriv->mmio + S626_P_SSR) & S626_SSR_AF2_OUT))
432 * Set up to trap execution at slot 0 when the TSL sequencer cycles
433 * back to slot 0 after executing the EOS in slot 5. Also,
434 * simultaneously shift out and in the 0x00 that is ALWAYS the value
435 * stored in the last byte to be shifted out of the FIFO's DWORD
438 writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
439 devpriv->mmio + S626_VECTPORT(0));
441 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
444 * Wait for the TSL to finish executing all time slots before
445 * exiting this function. We must do this so that the next DAC
446 * write doesn't start, thereby enabling clock/chip select signals:
448 * 1. Before the TSL sequence cycles back to slot 0, which disables
449 * the clock/cs signal gating and traps slot // list execution.
450 * we have not yet finished slot 5 then the clock/cs signals are
451 * still gated and we have not finished transmitting the stream.
453 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
454 * this case, the slot sequence is currently repeating, but with
455 * clock/cs signals disabled. We must wait for slot 0 to trap
456 * execution before setting up the next DAC setpoint DMA transfer
457 * and enabling the clock/cs signals. To detect the end of slot 5,
458 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
459 * the TSL has not yet finished executing slot 5 ...
461 if (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
463 * The trap was set on time and we are still executing somewhere
464 * in slots 2-5, so we now wait for slot 0 to execute and trap
465 * TSL execution. This is detected when FB_BUFFER2 MSB changes
466 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
467 * out/in on SD2 the 0x00 that is always referenced by slot 5.
469 while (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000)
473 * Either (1) we were too late setting the slot 0 trap; the TSL
474 * sequencer restarted slot 0 before we could set the EOS trap flag,
475 * or (2) we were not late and execution is now trapped at slot 0.
476 * In either case, we must now change slot 0 so that it will store
477 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
478 * In order to do this, we reprogram slot 0 so that it will shift in
479 * SD3, which is driven only by a pull-up resistor.
481 writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
482 devpriv->mmio + S626_VECTPORT(0));
485 * Wait for slot 0 to execute, at which time the TSL is setup for
486 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
489 while (!(readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000))
494 * Private helper function: Write setpoint to an application DAC channel.
496 static void s626_set_dac(struct comedi_device *dev, uint16_t chan,
497 unsigned short dacdata)
499 struct s626_private *devpriv = dev->private;
505 * Adjust DAC data polarity and set up Polarity Control Register image.
507 signmask = 1 << chan;
510 devpriv->dacpol |= signmask;
512 devpriv->dacpol &= ~signmask;
515 /* Limit DAC setpoint value to valid range. */
516 if ((uint16_t)dacdata > 0x1FFF)
520 * Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
521 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
522 * data to a non-existent TrimDac channel just to keep the clock
523 * running after sending data to the target DAC. This is necessary
524 * to eliminate the clock glitch that would otherwise occur at the
525 * end of the target DAC's serial data stream. When the sequence
526 * restarts at V0 (after executing V5), the gate array automatically
527 * disables gating for the DAC clock and all DAC chip selects.
530 /* Choose DAC chip select to be asserted */
531 ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
532 /* Slot 2: Transmit high data byte to target DAC */
533 writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
534 devpriv->mmio + S626_VECTPORT(2));
535 /* Slot 3: Transmit low data byte to target DAC */
536 writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
537 devpriv->mmio + S626_VECTPORT(3));
538 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
539 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
540 devpriv->mmio + S626_VECTPORT(4));
541 /* Slot 5: running after writing target DAC's low data byte */
542 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
543 devpriv->mmio + S626_VECTPORT(5));
546 * Construct and transmit target DAC's serial packet:
547 * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
548 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
549 * to a non-existent TrimDac channel) that serves to keep the clock
550 * running after the packet has been sent to the target DAC.
552 val = 0x0F000000; /* Continue clock after target DAC data
553 * (write to non-existent trimdac). */
554 val |= 0x00004000; /* Address the two main dual-DAC devices
555 * (TSL's chip select enables target device). */
556 val |= ((uint32_t)(chan & 1) << 15); /* Address the DAC channel
557 * within the device. */
558 val |= (uint32_t)dacdata; /* Include DAC setpoint data. */
559 s626_send_dac(dev, val);
562 static void s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan,
565 struct s626_private *devpriv = dev->private;
569 * Save the new setpoint in case the application needs to read it back
572 devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
574 /* Map logical channel number to physical channel number. */
575 chan = s626_trimchan[logical_chan];
578 * Set up TSL2 records for TrimDac write operation. All slots shift
579 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
583 /* Slot 2: Send high uint8_t to target TrimDac */
584 writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
585 devpriv->mmio + S626_VECTPORT(2));
586 /* Slot 3: Send low uint8_t to target TrimDac */
587 writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
588 devpriv->mmio + S626_VECTPORT(3));
589 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
590 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
591 devpriv->mmio + S626_VECTPORT(4));
592 /* Slot 5: Send NOP low uint8_t to DAC0 */
593 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
594 devpriv->mmio + S626_VECTPORT(5));
597 * Construct and transmit target DAC's serial packet:
598 * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
599 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
600 * WORD value (that writes a channel 0 NOP command to a non-existent
601 * main DAC channel) that serves to keep the clock running after the
602 * packet has been sent to the target DAC.
606 * Address the DAC channel within the trimdac device.
607 * Include DAC setpoint data.
609 s626_send_dac(dev, (chan << 8) | dac_data);
612 static void s626_load_trim_dacs(struct comedi_device *dev)
616 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
617 for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++)
618 s626_write_trim_dac(dev, i,
619 s626_i2c_read(dev, s626_trimadrs[i]));
622 /* ****** COUNTER FUNCTIONS ******* */
625 * All counter functions address a specific counter by means of the
626 * "Counter" argument, which is a logical counter number. The Counter
627 * argument may have any of the following legal values: 0=0A, 1=1A,
628 * 2=2A, 3=0B, 4=1B, 5=2B.
632 * Read a counter's output latch.
634 static uint32_t s626_read_latch(struct comedi_device *dev,
635 const struct s626_enc_info *k)
639 /* Latch counts and fetch LSW of latched counts value. */
640 value = s626_debi_read(dev, k->my_latch_lsw);
642 /* Fetch MSW of latched counts and combine with LSW. */
643 value |= ((uint32_t)s626_debi_read(dev, k->my_latch_lsw + 2) << 16);
645 /* Return latched counts. */
650 * Return/set a counter pair's latch trigger source. 0: On read
651 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
654 static void s626_set_latch_source(struct comedi_device *dev,
655 const struct s626_enc_info *k, uint16_t value)
657 s626_debi_replace(dev, k->my_crb,
658 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
659 S626_SET_CRB_LATCHSRC(value));
663 * Write value into counter preload register.
665 static void s626_preload(struct comedi_device *dev,
666 const struct s626_enc_info *k, uint32_t value)
668 s626_debi_write(dev, k->my_latch_lsw, value);
669 s626_debi_write(dev, k->my_latch_lsw + 2, value >> 16);
672 /* ****** PRIVATE COUNTER FUNCTIONS ****** */
675 * Reset a counter's index and overflow event capture flags.
677 static void s626_reset_cap_flags_a(struct comedi_device *dev,
678 const struct s626_enc_info *k)
680 s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
681 (S626_SET_CRB_INTRESETCMD(1) |
682 S626_SET_CRB_INTRESET_A(1)));
685 static void s626_reset_cap_flags_b(struct comedi_device *dev,
686 const struct s626_enc_info *k)
688 s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
689 (S626_SET_CRB_INTRESETCMD(1) |
690 S626_SET_CRB_INTRESET_B(1)));
694 * Return counter setup in a format (COUNTER_SETUP) that is consistent
695 * for both A and B counters.
697 static uint16_t s626_get_mode_a(struct comedi_device *dev,
698 const struct s626_enc_info *k)
703 unsigned cntsrc, clkmult, clkpol, encmode;
705 /* Fetch CRA and CRB register images. */
706 cra = s626_debi_read(dev, k->my_cra);
707 crb = s626_debi_read(dev, k->my_crb);
710 * Populate the standardized counter setup bit fields.
713 /* LoadSrc = LoadSrcA. */
714 S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
715 /* LatchSrc = LatchSrcA. */
716 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
717 /* IntSrc = IntSrcA. */
718 S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
719 /* IndxSrc = IndxSrcA. */
720 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
721 /* IndxPol = IndxPolA. */
722 S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
723 /* ClkEnab = ClkEnabA. */
724 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
726 /* Adjust mode-dependent parameters. */
727 cntsrc = S626_GET_CRA_CNTSRC_A(cra);
728 if (cntsrc & S626_CNTSRC_SYSCLK) {
729 /* Timer mode (CntSrcA<1> == 1): */
730 encmode = S626_ENCMODE_TIMER;
731 /* Set ClkPol to indicate count direction (CntSrcA<0>). */
733 /* ClkMult must be 1x in Timer mode. */
734 clkmult = S626_CLKMULT_1X;
736 /* Counter mode (CntSrcA<1> == 0): */
737 encmode = S626_ENCMODE_COUNTER;
738 /* Pass through ClkPol. */
739 clkpol = S626_GET_CRA_CLKPOL_A(cra);
740 /* Force ClkMult to 1x if not legal, else pass through. */
741 clkmult = S626_GET_CRA_CLKMULT_A(cra);
742 if (clkmult == S626_CLKMULT_SPECIAL)
743 clkmult = S626_CLKMULT_1X;
745 setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
746 S626_SET_STD_CLKPOL(clkpol);
748 /* Return adjusted counter setup. */
752 static uint16_t s626_get_mode_b(struct comedi_device *dev,
753 const struct s626_enc_info *k)
758 unsigned cntsrc, clkmult, clkpol, encmode;
760 /* Fetch CRA and CRB register images. */
761 cra = s626_debi_read(dev, k->my_cra);
762 crb = s626_debi_read(dev, k->my_crb);
765 * Populate the standardized counter setup bit fields.
768 /* IntSrc = IntSrcB. */
769 S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
770 /* LatchSrc = LatchSrcB. */
771 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
772 /* LoadSrc = LoadSrcB. */
773 S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
774 /* IndxPol = IndxPolB. */
775 S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
776 /* ClkEnab = ClkEnabB. */
777 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
778 /* IndxSrc = IndxSrcB. */
779 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
781 /* Adjust mode-dependent parameters. */
782 cntsrc = S626_GET_CRA_CNTSRC_B(cra);
783 clkmult = S626_GET_CRB_CLKMULT_B(crb);
784 if (clkmult == S626_CLKMULT_SPECIAL) {
785 /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
786 encmode = S626_ENCMODE_EXTENDER;
787 /* Indicate multiplier is 1x. */
788 clkmult = S626_CLKMULT_1X;
789 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
791 } else if (cntsrc & S626_CNTSRC_SYSCLK) {
792 /* Timer mode (CntSrcB<1> == 1): */
793 encmode = S626_ENCMODE_TIMER;
794 /* Indicate multiplier is 1x. */
795 clkmult = S626_CLKMULT_1X;
796 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
799 /* If Counter mode (CntSrcB<1> == 0): */
800 encmode = S626_ENCMODE_COUNTER;
801 /* Clock multiplier is passed through. */
802 /* Clock polarity is passed through. */
803 clkpol = S626_GET_CRB_CLKPOL_B(crb);
805 setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
806 S626_SET_STD_CLKPOL(clkpol);
808 /* Return adjusted counter setup. */
813 * Set the operating mode for the specified counter. The setup
814 * parameter is treated as a COUNTER_SETUP data type. The following
815 * parameters are programmable (all other parms are ignored): ClkMult,
816 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
818 static void s626_set_mode_a(struct comedi_device *dev,
819 const struct s626_enc_info *k, uint16_t setup,
820 uint16_t disable_int_src)
822 struct s626_private *devpriv = dev->private;
825 unsigned cntsrc, clkmult, clkpol;
827 /* Initialize CRA and CRB images. */
828 /* Preload trigger is passed through. */
829 cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
830 /* IndexSrc is passed through. */
831 cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
833 /* Reset any pending CounterA event captures. */
834 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
835 /* Clock enable is passed through. */
836 crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
838 /* Force IntSrc to Disabled if disable_int_src is asserted. */
839 if (!disable_int_src)
840 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
842 /* Populate all mode-dependent attributes of CRA & CRB images. */
843 clkpol = S626_GET_STD_CLKPOL(setup);
844 switch (S626_GET_STD_ENCMODE(setup)) {
845 case S626_ENCMODE_EXTENDER: /* Extender Mode: */
846 /* Force to Timer mode (Extender valid only for B counters). */
847 /* Fall through to case S626_ENCMODE_TIMER: */
848 case S626_ENCMODE_TIMER: /* Timer Mode: */
849 /* CntSrcA<1> selects system clock */
850 cntsrc = S626_CNTSRC_SYSCLK;
851 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
853 /* ClkPolA behaves as always-on clock enable. */
855 /* ClkMult must be 1x. */
856 clkmult = S626_CLKMULT_1X;
858 default: /* Counter Mode: */
859 /* Select ENC_C and ENC_D as clock/direction inputs. */
860 cntsrc = S626_CNTSRC_ENCODER;
861 /* Clock polarity is passed through. */
862 /* Force multiplier to x1 if not legal, else pass through. */
863 clkmult = S626_GET_STD_CLKMULT(setup);
864 if (clkmult == S626_CLKMULT_SPECIAL)
865 clkmult = S626_CLKMULT_1X;
868 cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
869 S626_SET_CRA_CLKMULT_A(clkmult);
872 * Force positive index polarity if IndxSrc is software-driven only,
873 * otherwise pass it through.
875 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
876 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
879 * If IntSrc has been forced to Disabled, update the MISC2 interrupt
880 * enable mask to indicate the counter interrupt is disabled.
883 devpriv->counter_int_enabs &= ~k->my_event_bits[3];
886 * While retaining CounterB and LatchSrc configurations, program the
887 * new counter operating mode.
889 s626_debi_replace(dev, k->my_cra,
890 S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
891 s626_debi_replace(dev, k->my_crb,
892 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
895 static void s626_set_mode_b(struct comedi_device *dev,
896 const struct s626_enc_info *k, uint16_t setup,
897 uint16_t disable_int_src)
899 struct s626_private *devpriv = dev->private;
902 unsigned cntsrc, clkmult, clkpol;
904 /* Initialize CRA and CRB images. */
905 /* IndexSrc is passed through. */
906 cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
908 /* Reset event captures and disable interrupts. */
909 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
910 /* Clock enable is passed through. */
911 crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
912 /* Preload trigger source is passed through. */
913 crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
915 /* Force IntSrc to Disabled if disable_int_src is asserted. */
916 if (!disable_int_src)
917 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
919 /* Populate all mode-dependent attributes of CRA & CRB images. */
920 clkpol = S626_GET_STD_CLKPOL(setup);
921 switch (S626_GET_STD_ENCMODE(setup)) {
922 case S626_ENCMODE_TIMER: /* Timer Mode: */
923 /* CntSrcB<1> selects system clock */
924 cntsrc = S626_CNTSRC_SYSCLK;
925 /* with direction (CntSrcB<0>) obtained from ClkPol. */
927 /* ClkPolB behaves as always-on clock enable. */
929 /* ClkMultB must be 1x. */
930 clkmult = S626_CLKMULT_1X;
932 case S626_ENCMODE_EXTENDER: /* Extender Mode: */
933 /* CntSrcB source is OverflowA (same as "timer") */
934 cntsrc = S626_CNTSRC_SYSCLK;
935 /* with direction obtained from ClkPol. */
937 /* ClkPolB controls IndexB -- always set to active. */
939 /* ClkMultB selects OverflowA as the clock source. */
940 clkmult = S626_CLKMULT_SPECIAL;
942 default: /* Counter Mode: */
943 /* Select ENC_C and ENC_D as clock/direction inputs. */
944 cntsrc = S626_CNTSRC_ENCODER;
945 /* ClkPol is passed through. */
946 /* Force ClkMult to x1 if not legal, otherwise pass through. */
947 clkmult = S626_GET_STD_CLKMULT(setup);
948 if (clkmult == S626_CLKMULT_SPECIAL)
949 clkmult = S626_CLKMULT_1X;
952 cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
953 crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
956 * Force positive index polarity if IndxSrc is software-driven only,
957 * otherwise pass it through.
959 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
960 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
963 * If IntSrc has been forced to Disabled, update the MISC2 interrupt
964 * enable mask to indicate the counter interrupt is disabled.
967 devpriv->counter_int_enabs &= ~k->my_event_bits[3];
970 * While retaining CounterA and LatchSrc configurations, program the
971 * new counter operating mode.
973 s626_debi_replace(dev, k->my_cra,
974 ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
975 s626_debi_replace(dev, k->my_crb,
976 S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
980 * Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index.
982 static void s626_set_enable_a(struct comedi_device *dev,
983 const struct s626_enc_info *k, uint16_t enab)
985 s626_debi_replace(dev, k->my_crb,
986 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A),
987 S626_SET_CRB_CLKENAB_A(enab));
990 static void s626_set_enable_b(struct comedi_device *dev,
991 const struct s626_enc_info *k, uint16_t enab)
993 s626_debi_replace(dev, k->my_crb,
994 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_B),
995 S626_SET_CRB_CLKENAB_B(enab));
998 static uint16_t s626_get_enable_a(struct comedi_device *dev,
999 const struct s626_enc_info *k)
1001 return S626_GET_CRB_CLKENAB_A(s626_debi_read(dev, k->my_crb));
1004 static uint16_t s626_get_enable_b(struct comedi_device *dev,
1005 const struct s626_enc_info *k)
1007 return S626_GET_CRB_CLKENAB_B(s626_debi_read(dev, k->my_crb));
1011 static uint16_t s626_get_latch_source(struct comedi_device *dev,
1012 const struct s626_enc_info *k)
1014 return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, k->my_crb));
1019 * Return/set the event that will trigger transfer of the preload
1020 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
1021 * 2=OverflowA (B counters only), 3=disabled.
1023 static void s626_set_load_trig_a(struct comedi_device *dev,
1024 const struct s626_enc_info *k, uint16_t trig)
1026 s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_LOADSRC_A,
1027 S626_SET_CRA_LOADSRC_A(trig));
1030 static void s626_set_load_trig_b(struct comedi_device *dev,
1031 const struct s626_enc_info *k, uint16_t trig)
1033 s626_debi_replace(dev, k->my_crb,
1034 ~(S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL),
1035 S626_SET_CRB_LOADSRC_B(trig));
1038 static uint16_t s626_get_load_trig_a(struct comedi_device *dev,
1039 const struct s626_enc_info *k)
1041 return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev, k->my_cra));
1044 static uint16_t s626_get_load_trig_b(struct comedi_device *dev,
1045 const struct s626_enc_info *k)
1047 return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev, k->my_crb));
1051 * Return/set counter interrupt source and clear any captured
1052 * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly,
1053 * 2=IndexOnly, 3=IndexAndOverflow.
1055 static void s626_set_int_src_a(struct comedi_device *dev,
1056 const struct s626_enc_info *k,
1057 uint16_t int_source)
1059 struct s626_private *devpriv = dev->private;
1061 /* Reset any pending counter overflow or index captures. */
1062 s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
1063 (S626_SET_CRB_INTRESETCMD(1) |
1064 S626_SET_CRB_INTRESET_A(1)));
1066 /* Program counter interrupt source. */
1067 s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_INTSRC_A,
1068 S626_SET_CRA_INTSRC_A(int_source));
1070 /* Update MISC2 interrupt enable mask. */
1071 devpriv->counter_int_enabs =
1072 (devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
1073 k->my_event_bits[int_source];
1076 static void s626_set_int_src_b(struct comedi_device *dev,
1077 const struct s626_enc_info *k,
1078 uint16_t int_source)
1080 struct s626_private *devpriv = dev->private;
1083 /* Cache writeable CRB register image. */
1084 crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL;
1086 /* Reset any pending counter overflow or index captures. */
1087 s626_debi_write(dev, k->my_crb, (crb | S626_SET_CRB_INTRESETCMD(1) |
1088 S626_SET_CRB_INTRESET_B(1)));
1090 /* Program counter interrupt source. */
1091 s626_debi_write(dev, k->my_crb, ((crb & ~S626_CRBMSK_INTSRC_B) |
1092 S626_SET_CRB_INTSRC_B(int_source)));
1094 /* Update MISC2 interrupt enable mask. */
1095 devpriv->counter_int_enabs =
1096 (devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
1097 k->my_event_bits[int_source];
1100 static uint16_t s626_get_int_src_a(struct comedi_device *dev,
1101 const struct s626_enc_info *k)
1103 return S626_GET_CRA_INTSRC_A(s626_debi_read(dev, k->my_cra));
1106 static uint16_t s626_get_int_src_b(struct comedi_device *dev,
1107 const struct s626_enc_info *k)
1109 return S626_GET_CRB_INTSRC_B(s626_debi_read(dev, k->my_crb));
1114 * Return/set the clock multiplier.
1116 static void s626_set_clk_mult(struct comedi_device *dev,
1117 const struct s626_enc_info *k, uint16_t value)
1119 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKMULT) |
1120 S626_SET_STD_CLKMULT(value)), false);
1123 static uint16_t s626_get_clk_mult(struct comedi_device *dev,
1124 const struct s626_enc_info *k)
1126 return S626_GET_STD_CLKMULT(k->get_mode(dev, k));
1130 * Return/set the clock polarity.
1132 static void s626_set_clk_pol(struct comedi_device *dev,
1133 const struct s626_enc_info *k, uint16_t value)
1135 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKPOL) |
1136 S626_SET_STD_CLKPOL(value)), false);
1139 static uint16_t s626_get_clk_pol(struct comedi_device *dev,
1140 const struct s626_enc_info *k)
1142 return S626_GET_STD_CLKPOL(k->get_mode(dev, k));
1146 * Return/set the encoder mode.
1148 static void s626_set_enc_mode(struct comedi_device *dev,
1149 const struct s626_enc_info *k, uint16_t value)
1151 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_ENCMODE) |
1152 S626_SET_STD_ENCMODE(value)), false);
1155 static uint16_t s626_get_enc_mode(struct comedi_device *dev,
1156 const struct s626_enc_info *k)
1158 return S626_GET_STD_ENCMODE(k->get_mode(dev, k));
1162 * Return/set the index polarity.
1164 static void s626_set_index_pol(struct comedi_device *dev,
1165 const struct s626_enc_info *k, uint16_t value)
1167 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXPOL) |
1168 S626_SET_STD_INDXPOL(value != 0)), false);
1171 static uint16_t s626_get_index_pol(struct comedi_device *dev,
1172 const struct s626_enc_info *k)
1174 return S626_GET_STD_INDXPOL(k->get_mode(dev, k));
1178 * Return/set the index source.
1180 static void s626_set_index_src(struct comedi_device *dev,
1181 const struct s626_enc_info *k, uint16_t value)
1183 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXSRC) |
1184 S626_SET_STD_INDXSRC(value != 0)), false);
1187 static uint16_t s626_get_index_src(struct comedi_device *dev,
1188 const struct s626_enc_info *k)
1190 return S626_GET_STD_INDXSRC(k->get_mode(dev, k));
1195 * Generate an index pulse.
1197 static void s626_pulse_index_a(struct comedi_device *dev,
1198 const struct s626_enc_info *k)
1202 cra = s626_debi_read(dev, k->my_cra);
1204 s626_debi_write(dev, k->my_cra, (cra ^ S626_CRAMSK_INDXPOL_A));
1205 s626_debi_write(dev, k->my_cra, cra);
1208 static void s626_pulse_index_b(struct comedi_device *dev,
1209 const struct s626_enc_info *k)
1213 crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL;
1215 s626_debi_write(dev, k->my_crb, (crb ^ S626_CRBMSK_INDXPOL_B));
1216 s626_debi_write(dev, k->my_crb, crb);
1219 static const struct s626_enc_info s626_enc_chan_info[] = {
1221 .get_enable = s626_get_enable_a,
1222 .get_int_src = s626_get_int_src_a,
1223 .get_load_trig = s626_get_load_trig_a,
1224 .get_mode = s626_get_mode_a,
1225 .pulse_index = s626_pulse_index_a,
1226 .set_enable = s626_set_enable_a,
1227 .set_int_src = s626_set_int_src_a,
1228 .set_load_trig = s626_set_load_trig_a,
1229 .set_mode = s626_set_mode_a,
1230 .reset_cap_flags = s626_reset_cap_flags_a,
1231 .my_cra = S626_LP_CR0A,
1232 .my_crb = S626_LP_CR0B,
1233 .my_latch_lsw = S626_LP_CNTR0ALSW,
1234 .my_event_bits = S626_EVBITS(0),
1236 .get_enable = s626_get_enable_a,
1237 .get_int_src = s626_get_int_src_a,
1238 .get_load_trig = s626_get_load_trig_a,
1239 .get_mode = s626_get_mode_a,
1240 .pulse_index = s626_pulse_index_a,
1241 .set_enable = s626_set_enable_a,
1242 .set_int_src = s626_set_int_src_a,
1243 .set_load_trig = s626_set_load_trig_a,
1244 .set_mode = s626_set_mode_a,
1245 .reset_cap_flags = s626_reset_cap_flags_a,
1246 .my_cra = S626_LP_CR1A,
1247 .my_crb = S626_LP_CR1B,
1248 .my_latch_lsw = S626_LP_CNTR1ALSW,
1249 .my_event_bits = S626_EVBITS(1),
1251 .get_enable = s626_get_enable_a,
1252 .get_int_src = s626_get_int_src_a,
1253 .get_load_trig = s626_get_load_trig_a,
1254 .get_mode = s626_get_mode_a,
1255 .pulse_index = s626_pulse_index_a,
1256 .set_enable = s626_set_enable_a,
1257 .set_int_src = s626_set_int_src_a,
1258 .set_load_trig = s626_set_load_trig_a,
1259 .set_mode = s626_set_mode_a,
1260 .reset_cap_flags = s626_reset_cap_flags_a,
1261 .my_cra = S626_LP_CR2A,
1262 .my_crb = S626_LP_CR2B,
1263 .my_latch_lsw = S626_LP_CNTR2ALSW,
1264 .my_event_bits = S626_EVBITS(2),
1266 .get_enable = s626_get_enable_b,
1267 .get_int_src = s626_get_int_src_b,
1268 .get_load_trig = s626_get_load_trig_b,
1269 .get_mode = s626_get_mode_b,
1270 .pulse_index = s626_pulse_index_b,
1271 .set_enable = s626_set_enable_b,
1272 .set_int_src = s626_set_int_src_b,
1273 .set_load_trig = s626_set_load_trig_b,
1274 .set_mode = s626_set_mode_b,
1275 .reset_cap_flags = s626_reset_cap_flags_b,
1276 .my_cra = S626_LP_CR0A,
1277 .my_crb = S626_LP_CR0B,
1278 .my_latch_lsw = S626_LP_CNTR0BLSW,
1279 .my_event_bits = S626_EVBITS(3),
1281 .get_enable = s626_get_enable_b,
1282 .get_int_src = s626_get_int_src_b,
1283 .get_load_trig = s626_get_load_trig_b,
1284 .get_mode = s626_get_mode_b,
1285 .pulse_index = s626_pulse_index_b,
1286 .set_enable = s626_set_enable_b,
1287 .set_int_src = s626_set_int_src_b,
1288 .set_load_trig = s626_set_load_trig_b,
1289 .set_mode = s626_set_mode_b,
1290 .reset_cap_flags = s626_reset_cap_flags_b,
1291 .my_cra = S626_LP_CR1A,
1292 .my_crb = S626_LP_CR1B,
1293 .my_latch_lsw = S626_LP_CNTR1BLSW,
1294 .my_event_bits = S626_EVBITS(4),
1296 .get_enable = s626_get_enable_b,
1297 .get_int_src = s626_get_int_src_b,
1298 .get_load_trig = s626_get_load_trig_b,
1299 .get_mode = s626_get_mode_b,
1300 .pulse_index = s626_pulse_index_b,
1301 .set_enable = s626_set_enable_b,
1302 .set_int_src = s626_set_int_src_b,
1303 .set_load_trig = s626_set_load_trig_b,
1304 .set_mode = s626_set_mode_b,
1305 .reset_cap_flags = s626_reset_cap_flags_b,
1306 .my_cra = S626_LP_CR2A,
1307 .my_crb = S626_LP_CR2B,
1308 .my_latch_lsw = S626_LP_CNTR2BLSW,
1309 .my_event_bits = S626_EVBITS(5),
1313 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1315 return ((data >> 18) & 0x3fff) ^ 0x2000;
1318 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1320 unsigned int group = chan / 16;
1321 unsigned int mask = 1 << (chan - (16 * group));
1322 unsigned int status;
1324 /* set channel to capture positive edge */
1325 status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1326 s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1328 /* enable interrupt on selected channel */
1329 status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1330 s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1332 /* enable edge capture write command */
1333 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1335 /* enable edge capture on selected channel */
1336 status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1337 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1342 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1345 /* disable edge capture write command */
1346 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1348 /* enable edge capture on selected channel */
1349 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1354 static int s626_dio_clear_irq(struct comedi_device *dev)
1358 /* disable edge capture write command */
1359 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1361 /* clear all dio pending events and interrupt */
1362 for (group = 0; group < S626_DIO_BANKS; group++)
1363 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1368 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1369 uint16_t irqbit, uint8_t group)
1371 struct s626_private *devpriv = dev->private;
1372 struct comedi_subdevice *s = dev->read_subdev;
1373 struct comedi_cmd *cmd = &s->async->cmd;
1375 s626_dio_reset_irq(dev, group, irqbit);
1377 if (devpriv->ai_cmd_running) {
1378 /* check if interrupt is an ai acquisition start trigger */
1379 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1380 cmd->start_src == TRIG_EXT) {
1381 /* Start executing the RPS program */
1382 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1384 if (cmd->scan_begin_src == TRIG_EXT)
1385 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1387 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1388 cmd->scan_begin_src == TRIG_EXT) {
1389 /* Trigger ADC scan loop start */
1390 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1392 if (cmd->convert_src == TRIG_EXT) {
1393 devpriv->ai_convert_count = cmd->chanlist_len;
1395 s626_dio_set_irq(dev, cmd->convert_arg);
1398 if (cmd->convert_src == TRIG_TIMER) {
1399 const struct s626_enc_info *k =
1400 &s626_enc_chan_info[5];
1402 devpriv->ai_convert_count = cmd->chanlist_len;
1403 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
1406 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1407 cmd->convert_src == TRIG_EXT) {
1408 /* Trigger ADC scan loop start */
1409 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1411 devpriv->ai_convert_count--;
1412 if (devpriv->ai_convert_count > 0)
1413 s626_dio_set_irq(dev, cmd->convert_arg);
1418 static void s626_check_dio_interrupts(struct comedi_device *dev)
1423 for (group = 0; group < S626_DIO_BANKS; group++) {
1425 /* read interrupt type */
1426 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1428 /* check if interrupt is generated from dio channels */
1430 s626_handle_dio_interrupt(dev, irqbit, group);
1436 static void s626_check_counter_interrupts(struct comedi_device *dev)
1438 struct s626_private *devpriv = dev->private;
1439 struct comedi_subdevice *s = dev->read_subdev;
1440 struct comedi_async *async = s->async;
1441 struct comedi_cmd *cmd = &async->cmd;
1442 const struct s626_enc_info *k;
1445 /* read interrupt type */
1446 irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1448 /* check interrupt on counters */
1449 if (irqbit & S626_IRQ_COINT1A) {
1450 k = &s626_enc_chan_info[0];
1452 /* clear interrupt capture flag */
1453 k->reset_cap_flags(dev, k);
1455 if (irqbit & S626_IRQ_COINT2A) {
1456 k = &s626_enc_chan_info[1];
1458 /* clear interrupt capture flag */
1459 k->reset_cap_flags(dev, k);
1461 if (irqbit & S626_IRQ_COINT3A) {
1462 k = &s626_enc_chan_info[2];
1464 /* clear interrupt capture flag */
1465 k->reset_cap_flags(dev, k);
1467 if (irqbit & S626_IRQ_COINT1B) {
1468 k = &s626_enc_chan_info[3];
1470 /* clear interrupt capture flag */
1471 k->reset_cap_flags(dev, k);
1473 if (irqbit & S626_IRQ_COINT2B) {
1474 k = &s626_enc_chan_info[4];
1476 /* clear interrupt capture flag */
1477 k->reset_cap_flags(dev, k);
1479 if (devpriv->ai_convert_count > 0) {
1480 devpriv->ai_convert_count--;
1481 if (devpriv->ai_convert_count == 0)
1482 k->set_enable(dev, k, S626_CLKENAB_INDEX);
1484 if (cmd->convert_src == TRIG_TIMER) {
1485 /* Trigger ADC scan loop start */
1486 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1491 if (irqbit & S626_IRQ_COINT3B) {
1492 k = &s626_enc_chan_info[5];
1494 /* clear interrupt capture flag */
1495 k->reset_cap_flags(dev, k);
1497 if (cmd->scan_begin_src == TRIG_TIMER) {
1498 /* Trigger ADC scan loop start */
1499 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1502 if (cmd->convert_src == TRIG_TIMER) {
1503 k = &s626_enc_chan_info[4];
1504 devpriv->ai_convert_count = cmd->chanlist_len;
1505 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
1510 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1512 struct s626_private *devpriv = dev->private;
1513 struct comedi_subdevice *s = dev->read_subdev;
1514 struct comedi_async *async = s->async;
1515 struct comedi_cmd *cmd = &async->cmd;
1517 * Init ptr to DMA buffer that holds new ADC data. We skip the
1518 * first uint16_t in the buffer because it contains junk data
1519 * from the final ADC of the previous poll list scan.
1521 uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1522 bool finished = false;
1525 /* get the data and hand it over to comedi */
1526 for (i = 0; i < cmd->chanlist_len; i++) {
1527 unsigned short tempdata;
1530 * Convert ADC data to 16-bit integer values and copy
1531 * to application buffer.
1533 tempdata = s626_ai_reg_to_uint(*readaddr);
1536 /* put data into read buffer */
1537 /* comedi_buf_put(async, tempdata); */
1538 cfc_write_to_buffer(s, tempdata);
1541 /* end of scan occurs */
1542 async->events |= COMEDI_CB_EOS;
1544 if (!devpriv->ai_continuous)
1545 devpriv->ai_sample_count--;
1546 if (devpriv->ai_sample_count <= 0) {
1547 devpriv->ai_cmd_running = 0;
1549 /* Stop RPS program */
1550 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1552 /* send end of acquisition */
1553 async->events |= COMEDI_CB_EOA;
1555 /* disable master interrupt */
1559 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1560 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1562 /* tell comedi that data is there */
1563 comedi_event(dev, s);
1568 static irqreturn_t s626_irq_handler(int irq, void *d)
1570 struct comedi_device *dev = d;
1571 struct s626_private *devpriv = dev->private;
1572 unsigned long flags;
1573 uint32_t irqtype, irqstatus;
1577 /* lock to avoid race with comedi_poll */
1578 spin_lock_irqsave(&dev->spinlock, flags);
1580 /* save interrupt enable register state */
1581 irqstatus = readl(devpriv->mmio + S626_P_IER);
1583 /* read interrupt type */
1584 irqtype = readl(devpriv->mmio + S626_P_ISR);
1586 /* disable master interrupt */
1587 writel(0, devpriv->mmio + S626_P_IER);
1589 /* clear interrupt */
1590 writel(irqtype, devpriv->mmio + S626_P_ISR);
1593 case S626_IRQ_RPS1: /* end_of_scan occurs */
1594 if (s626_handle_eos_interrupt(dev))
1597 case S626_IRQ_GPIO3: /* check dio and counter interrupt */
1598 /* s626_dio_clear_irq(dev); */
1599 s626_check_dio_interrupts(dev);
1600 s626_check_counter_interrupts(dev);
1604 /* enable interrupt */
1605 writel(irqstatus, devpriv->mmio + S626_P_IER);
1607 spin_unlock_irqrestore(&dev->spinlock, flags);
1612 * This function builds the RPS program for hardware driven acquisition.
1614 static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1616 struct s626_private *devpriv = dev->private;
1622 struct comedi_cmd *cmd = &dev->subdevices->async->cmd;
1624 /* Stop RPS program in case it is currently running */
1625 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1627 /* Set starting logical address to write RPS commands. */
1628 rps = (uint32_t *)devpriv->rps_buf.logical_base;
1630 /* Initialize RPS instruction pointer */
1631 writel((uint32_t)devpriv->rps_buf.physical_base,
1632 devpriv->mmio + S626_P_RPSADDR1);
1634 /* Construct RPS program in rps_buf DMA buffer */
1635 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1636 /* Wait for Start trigger. */
1637 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1638 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1642 * SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1643 * because the first RPS DEBI Write following a non-RPS DEBI write
1644 * seems to always fail. If we don't do this dummy write, the ADC
1645 * gain might not be set to the value required for the first slot in
1646 * the poll list; the ADC gain would instead remain unchanged from
1647 * the previously programmed value.
1649 /* Write DEBI Write command and address to shadow RAM. */
1650 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1651 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1652 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1653 /* Write DEBI immediate data to shadow RAM: */
1654 *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */
1655 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1656 /* Reset "shadow RAM uploaded" flag. */
1657 /* Invoke shadow RAM upload. */
1658 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1659 /* Wait for shadow upload to finish. */
1660 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1663 * Digitize all slots in the poll list. This is implemented as a
1664 * for loop to limit the slot count to 16 in case the application
1665 * forgot to set the S626_EOPL flag in the final slot.
1667 for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1668 devpriv->adc_items++) {
1670 * Convert application's poll list item to private board class
1671 * format. Each app poll list item is an uint8_t with form
1672 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1673 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1675 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1676 S626_GSEL_BIPOLAR10V);
1678 /* Switch ADC analog gain. */
1679 /* Write DEBI command and address to shadow RAM. */
1680 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1681 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1682 /* Write DEBI immediate data to shadow RAM. */
1683 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1685 /* Reset "shadow RAM uploaded" flag. */
1686 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1687 /* Invoke shadow RAM upload. */
1688 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1689 /* Wait for shadow upload to finish. */
1690 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1691 /* Select ADC analog input channel. */
1692 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1693 /* Write DEBI command and address to shadow RAM. */
1694 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1695 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1696 /* Write DEBI immediate data to shadow RAM. */
1698 /* Reset "shadow RAM uploaded" flag. */
1699 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1700 /* Invoke shadow RAM upload. */
1701 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1702 /* Wait for shadow upload to finish. */
1703 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1706 * Delay at least 10 microseconds for analog input settling.
1707 * Instead of padding with NOPs, we use S626_RPS_JUMP
1708 * instructions here; this allows us to produce a longer delay
1709 * than is possible with NOPs because each S626_RPS_JUMP
1710 * flushes the RPS' instruction prefetch pipeline.
1713 (uint32_t)devpriv->rps_buf.physical_base +
1714 (uint32_t)((unsigned long)rps -
1715 (unsigned long)devpriv->
1716 rps_buf.logical_base);
1717 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1718 jmp_adrs += 8; /* Repeat to implement time delay: */
1719 /* Jump to next RPS instruction. */
1720 *rps++ = S626_RPS_JUMP;
1724 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1725 /* Wait for Start trigger. */
1726 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1727 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1729 /* Start ADC by pulsing GPIO1. */
1730 /* Begin ADC Start pulse. */
1731 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1732 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1733 *rps++ = S626_RPS_NOP;
1734 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1735 /* End ADC Start pulse. */
1736 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1737 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1739 * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1740 * busy) and for data from previous conversion to shift into FB
1741 * BUFFER 1 register.
1743 /* Wait for ADC done. */
1744 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1746 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1747 *rps++ = S626_RPS_STREG |
1748 (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1749 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1750 (devpriv->adc_items << 2);
1753 * If this slot's EndOfPollList flag is set, all channels have
1754 * now been processed.
1756 if (*ppl++ & S626_EOPL) {
1757 devpriv->adc_items++; /* Adjust poll list item count. */
1758 break; /* Exit poll list processing loop. */
1763 * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1764 * ADC to stabilize for 2 microseconds before starting the final
1765 * (dummy) conversion. This delay is necessary to allow sufficient
1766 * time between last conversion finished and the start of the dummy
1767 * conversion. Without this delay, the last conversion's data value
1768 * is sometimes set to the previous conversion's data value.
1770 for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1771 *rps++ = S626_RPS_NOP;
1774 * Start a dummy conversion to cause the data from the last
1775 * conversion of interest to be shifted in.
1777 /* Begin ADC Start pulse. */
1778 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1779 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1780 *rps++ = S626_RPS_NOP;
1781 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1782 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1783 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1786 * Wait for the data from the last conversion of interest to arrive
1787 * in FB BUFFER 1 register.
1789 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */
1791 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1792 *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1793 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1794 (devpriv->adc_items << 2);
1796 /* Indicate ADC scan loop is finished. */
1797 /* Signal ReadADC() that scan is done. */
1798 /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1800 /* invoke interrupt */
1801 if (devpriv->ai_cmd_running == 1)
1802 *rps++ = S626_RPS_IRQ;
1804 /* Restart RPS program at its beginning. */
1805 *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1806 *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1808 /* End of RPS program build */
1812 static int s626_ai_rinsn(struct comedi_device *dev,
1813 struct comedi_subdevice *s,
1814 struct comedi_insn *insn,
1817 struct s626_private *devpriv = dev->private;
1821 /* Trigger ADC scan loop start */
1822 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1824 /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1825 while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1829 * Init ptr to DMA buffer that holds new ADC data. We skip the
1830 * first uint16_t in the buffer because it contains junk data from
1831 * the final ADC of the previous poll list scan.
1833 readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1836 * Convert ADC data to 16-bit integer values and
1837 * copy to application buffer.
1839 for (i = 0; i < devpriv->adc_items; i++) {
1840 *data = s626_ai_reg_to_uint(*readaddr++);
1848 static int s626_ai_insn_read(struct comedi_device *dev,
1849 struct comedi_subdevice *s,
1850 struct comedi_insn *insn, unsigned int *data)
1852 struct s626_private *devpriv = dev->private;
1853 uint16_t chan = CR_CHAN(insn->chanspec);
1854 uint16_t range = CR_RANGE(insn->chanspec);
1855 uint16_t adc_spec = 0;
1856 uint32_t gpio_image;
1861 * Convert application's ADC specification into form
1862 * appropriate for register programming.
1865 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1867 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1869 /* Switch ADC analog gain. */
1870 s626_debi_write(dev, S626_LP_GSEL, adc_spec); /* Set gain. */
1872 /* Select ADC analog input channel. */
1873 s626_debi_write(dev, S626_LP_ISEL, adc_spec); /* Select channel. */
1875 for (n = 0; n < insn->n; n++) {
1876 /* Delay 10 microseconds for analog input settling. */
1879 /* Start ADC by pulsing GPIO1 low */
1880 gpio_image = readl(devpriv->mmio + S626_P_GPIO);
1881 /* Assert ADC Start command */
1882 writel(gpio_image & ~S626_GPIO1_HI,
1883 devpriv->mmio + S626_P_GPIO);
1884 /* and stretch it out */
1885 writel(gpio_image & ~S626_GPIO1_HI,
1886 devpriv->mmio + S626_P_GPIO);
1887 writel(gpio_image & ~S626_GPIO1_HI,
1888 devpriv->mmio + S626_P_GPIO);
1889 /* Negate ADC Start command */
1890 writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
1893 * Wait for ADC to complete (GPIO2 is asserted high when
1894 * ADC not busy) and for data from previous conversion to
1895 * shift into FB BUFFER 1 register.
1898 /* Wait for ADC done */
1899 while (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_GPIO2))
1902 /* Fetch ADC data */
1904 tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1);
1905 data[n - 1] = s626_ai_reg_to_uint(tmp);
1909 * Allow the ADC to stabilize for 4 microseconds before
1910 * starting the next (final) conversion. This delay is
1911 * necessary to allow sufficient time between last
1912 * conversion finished and the start of the next
1913 * conversion. Without this delay, the last conversion's
1914 * data value is sometimes set to the previous
1915 * conversion's data value.
1921 * Start a dummy conversion to cause the data from the
1922 * previous conversion to be shifted in.
1924 gpio_image = readl(devpriv->mmio + S626_P_GPIO);
1925 /* Assert ADC Start command */
1926 writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
1927 /* and stretch it out */
1928 writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
1929 writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
1930 /* Negate ADC Start command */
1931 writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
1933 /* Wait for the data to arrive in FB BUFFER 1 register. */
1935 /* Wait for ADC done */
1936 while (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_GPIO2))
1939 /* Fetch ADC data from audio interface's input shift register. */
1941 /* Fetch ADC data */
1943 tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1);
1944 data[n - 1] = s626_ai_reg_to_uint(tmp);
1950 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1954 for (n = 0; n < cmd->chanlist_len; n++) {
1955 if (CR_RANGE(cmd->chanlist[n]) == 0)
1956 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1958 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1961 ppl[n - 1] |= S626_EOPL;
1966 static int s626_ai_inttrig(struct comedi_device *dev,
1967 struct comedi_subdevice *s, unsigned int trignum)
1972 /* Start executing the RPS program */
1973 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1975 s->async->inttrig = NULL;
1981 * This function doesn't require a particular form, this is just what
1982 * happens to be used in some of the drivers. It should convert ns
1983 * nanoseconds to a counter value suitable for programming the device.
1984 * Also, it should adjust ns so that it cooresponds to the actual time
1985 * that the device will use.
1987 static int s626_ns_to_timer(int *nanosec, int round_mode)
1991 base = 500; /* 2MHz internal clock */
1993 switch (round_mode) {
1994 case TRIG_ROUND_NEAREST:
1996 divider = (*nanosec + base / 2) / base;
1998 case TRIG_ROUND_DOWN:
1999 divider = (*nanosec) / base;
2002 divider = (*nanosec + base - 1) / base;
2006 *nanosec = base * divider;
2010 static void s626_timer_load(struct comedi_device *dev,
2011 const struct s626_enc_info *k, int tick)
2014 /* Preload upon index. */
2015 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2016 /* Disable hardware index. */
2017 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2018 /* Operating mode is Timer. */
2019 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
2020 /* Count direction is Down. */
2021 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
2022 /* Clock multiplier is 1x. */
2023 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2024 /* Enabled by index */
2025 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2026 uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
2027 /* uint16_t enab = S626_CLKENAB_ALWAYS; */
2029 k->set_mode(dev, k, setup, false);
2031 /* Set the preload register */
2032 s626_preload(dev, k, tick);
2035 * Software index pulse forces the preload register to load
2038 k->set_load_trig(dev, k, 0);
2039 k->pulse_index(dev, k);
2041 /* set reload on counter overflow */
2042 k->set_load_trig(dev, k, 1);
2044 /* set interrupt on overflow */
2045 k->set_int_src(dev, k, S626_INTSRC_OVER);
2047 s626_set_latch_source(dev, k, value_latchsrc);
2048 /* k->set_enable(dev, k, (uint16_t)(enab != 0)); */
2052 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2054 struct s626_private *devpriv = dev->private;
2056 struct comedi_cmd *cmd = &s->async->cmd;
2057 const struct s626_enc_info *k;
2060 if (devpriv->ai_cmd_running) {
2061 dev_err(dev->class_dev,
2062 "s626_ai_cmd: Another ai_cmd is running\n");
2065 /* disable interrupt */
2066 writel(0, devpriv->mmio + S626_P_IER);
2068 /* clear interrupt request */
2069 writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, devpriv->mmio + S626_P_ISR);
2071 /* clear any pending interrupt */
2072 s626_dio_clear_irq(dev);
2073 /* s626_enc_clear_irq(dev); */
2075 /* reset ai_cmd_running flag */
2076 devpriv->ai_cmd_running = 0;
2078 /* test if cmd is valid */
2082 if (dev->irq == 0) {
2084 "s626_ai_cmd: cannot run command without an irq");
2088 s626_ai_load_polllist(ppl, cmd);
2089 devpriv->ai_cmd_running = 1;
2090 devpriv->ai_convert_count = 0;
2092 switch (cmd->scan_begin_src) {
2097 * set a counter to generate adc trigger at scan_begin_arg
2100 k = &s626_enc_chan_info[5];
2101 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
2102 cmd->flags & TRIG_ROUND_MASK);
2104 /* load timer value and enable interrupt */
2105 s626_timer_load(dev, k, tick);
2106 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
2109 /* set the digital line and interrupt for scan trigger */
2110 if (cmd->start_src != TRIG_EXT)
2111 s626_dio_set_irq(dev, cmd->scan_begin_arg);
2115 switch (cmd->convert_src) {
2120 * set a counter to generate adc trigger at convert_arg
2123 k = &s626_enc_chan_info[4];
2124 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
2125 cmd->flags & TRIG_ROUND_MASK);
2127 /* load timer value and enable interrupt */
2128 s626_timer_load(dev, k, tick);
2129 k->set_enable(dev, k, S626_CLKENAB_INDEX);
2132 /* set the digital line and interrupt for convert trigger */
2133 if (cmd->scan_begin_src != TRIG_EXT &&
2134 cmd->start_src == TRIG_EXT)
2135 s626_dio_set_irq(dev, cmd->convert_arg);
2139 switch (cmd->stop_src) {
2141 /* data arrives as one packet */
2142 devpriv->ai_sample_count = cmd->stop_arg;
2143 devpriv->ai_continuous = 0;
2146 /* continuous acquisition */
2147 devpriv->ai_continuous = 1;
2148 devpriv->ai_sample_count = 1;
2152 s626_reset_adc(dev, ppl);
2154 switch (cmd->start_src) {
2156 /* Trigger ADC scan loop start */
2157 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2159 /* Start executing the RPS program */
2160 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2161 s->async->inttrig = NULL;
2164 /* configure DIO channel for acquisition trigger */
2165 s626_dio_set_irq(dev, cmd->start_arg);
2166 s->async->inttrig = NULL;
2169 s->async->inttrig = s626_ai_inttrig;
2173 /* enable interrupt */
2174 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, devpriv->mmio + S626_P_IER);
2179 static int s626_ai_cmdtest(struct comedi_device *dev,
2180 struct comedi_subdevice *s, struct comedi_cmd *cmd)
2185 /* Step 1 : check if triggers are trivially valid */
2187 err |= cfc_check_trigger_src(&cmd->start_src,
2188 TRIG_NOW | TRIG_INT | TRIG_EXT);
2189 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2190 TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2191 err |= cfc_check_trigger_src(&cmd->convert_src,
2192 TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2193 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2194 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2199 /* Step 2a : make sure trigger sources are unique */
2201 err |= cfc_check_trigger_is_unique(cmd->start_src);
2202 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2203 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2204 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2206 /* Step 2b : and mutually compatible */
2211 /* step 3: make sure arguments are trivially compatible */
2213 if (cmd->start_src != TRIG_EXT)
2214 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2215 if (cmd->start_src == TRIG_EXT)
2216 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
2217 if (cmd->scan_begin_src == TRIG_EXT)
2218 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2219 if (cmd->convert_src == TRIG_EXT)
2220 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
2222 #define S626_MAX_SPEED 200000 /* in nanoseconds */
2223 #define S626_MIN_SPEED 2000000000 /* in nanoseconds */
2225 if (cmd->scan_begin_src == TRIG_TIMER) {
2226 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2228 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2231 /* external trigger */
2232 /* should be level/edge, hi/lo specification here */
2233 /* should specify multiple external triggers */
2234 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2236 if (cmd->convert_src == TRIG_TIMER) {
2237 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2239 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2242 /* external trigger */
2244 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2247 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2249 if (cmd->stop_src == TRIG_COUNT)
2250 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
2251 else /* TRIG_NONE */
2252 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2257 /* step 4: fix up any arguments */
2259 if (cmd->scan_begin_src == TRIG_TIMER) {
2260 tmp = cmd->scan_begin_arg;
2261 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
2262 cmd->flags & TRIG_ROUND_MASK);
2263 if (tmp != cmd->scan_begin_arg)
2266 if (cmd->convert_src == TRIG_TIMER) {
2267 tmp = cmd->convert_arg;
2268 s626_ns_to_timer((int *)&cmd->convert_arg,
2269 cmd->flags & TRIG_ROUND_MASK);
2270 if (tmp != cmd->convert_arg)
2272 if (cmd->scan_begin_src == TRIG_TIMER &&
2273 cmd->scan_begin_arg < cmd->convert_arg *
2274 cmd->scan_end_arg) {
2275 cmd->scan_begin_arg = cmd->convert_arg *
2287 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2289 struct s626_private *devpriv = dev->private;
2291 /* Stop RPS program in case it is currently running */
2292 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2294 /* disable master interrupt */
2295 writel(0, devpriv->mmio + S626_P_IER);
2297 devpriv->ai_cmd_running = 0;
2302 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
2303 struct comedi_insn *insn, unsigned int *data)
2305 struct s626_private *devpriv = dev->private;
2307 uint16_t chan = CR_CHAN(insn->chanspec);
2310 for (i = 0; i < insn->n; i++) {
2311 dacdata = (int16_t) data[i];
2312 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2313 dacdata -= (0x1fff);
2315 s626_set_dac(dev, chan, dacdata);
2321 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
2322 struct comedi_insn *insn, unsigned int *data)
2324 struct s626_private *devpriv = dev->private;
2327 for (i = 0; i < insn->n; i++)
2328 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
2333 /* *************** DIGITAL I/O FUNCTIONS *************** */
2336 * All DIO functions address a group of DIO channels by means of
2337 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
2338 * ports A, B and C, respectively.
2341 static void s626_dio_init(struct comedi_device *dev)
2345 /* Prepare to treat writes to WRCapSel as capture disables. */
2346 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2348 /* For each group of sixteen channels ... */
2349 for (group = 0; group < S626_DIO_BANKS; group++) {
2350 /* Disable all interrupts */
2351 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2352 /* Disable all event captures */
2353 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2354 /* Init all DIOs to default edge polarity */
2355 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2356 /* Program all outputs to inactive state */
2357 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2361 static int s626_dio_insn_bits(struct comedi_device *dev,
2362 struct comedi_subdevice *s,
2363 struct comedi_insn *insn,
2366 unsigned long group = (unsigned long)s->private;
2368 if (comedi_dio_update_state(s, data))
2369 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2371 data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2376 static int s626_dio_insn_config(struct comedi_device *dev,
2377 struct comedi_subdevice *s,
2378 struct comedi_insn *insn,
2381 unsigned long group = (unsigned long)s->private;
2384 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2388 s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2394 * Now this function initializes the value of the counter (data[0])
2395 * and set the subdevice. To complete with trigger and interrupt
2398 * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2399 * what is being configured, but this function appears to be using data[0]
2402 static int s626_enc_insn_config(struct comedi_device *dev,
2403 struct comedi_subdevice *s,
2404 struct comedi_insn *insn, unsigned int *data)
2407 /* Preload upon index. */
2408 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2409 /* Disable hardware index. */
2410 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2411 /* Operating mode is Counter. */
2412 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2413 /* Active high clock. */
2414 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2415 /* Clock multiplier is 1x. */
2416 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2417 /* Enabled by index */
2418 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2419 /* uint16_t disable_int_src = true; */
2420 /* uint32_t Preloadvalue; //Counter initial value */
2421 uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2422 uint16_t enab = S626_CLKENAB_ALWAYS;
2423 const struct s626_enc_info *k =
2424 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2426 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2428 k->set_mode(dev, k, setup, true);
2429 s626_preload(dev, k, data[0]);
2430 k->pulse_index(dev, k);
2431 s626_set_latch_source(dev, k, value_latchsrc);
2432 k->set_enable(dev, k, (enab != 0));
2437 static int s626_enc_insn_read(struct comedi_device *dev,
2438 struct comedi_subdevice *s,
2439 struct comedi_insn *insn, unsigned int *data)
2442 const struct s626_enc_info *k =
2443 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2445 for (n = 0; n < insn->n; n++)
2446 data[n] = s626_read_latch(dev, k);
2451 static int s626_enc_insn_write(struct comedi_device *dev,
2452 struct comedi_subdevice *s,
2453 struct comedi_insn *insn, unsigned int *data)
2455 const struct s626_enc_info *k =
2456 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2458 /* Set the preload register */
2459 s626_preload(dev, k, data[0]);
2462 * Software index pulse forces the preload register to load
2465 k->set_load_trig(dev, k, 0);
2466 k->pulse_index(dev, k);
2467 k->set_load_trig(dev, k, 2);
2472 static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2474 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2475 s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2476 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2479 static void s626_close_dma_b(struct comedi_device *dev,
2480 struct s626_buffer_dma *pdma, size_t bsize)
2482 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2489 /* find the matching allocation from the board struct */
2490 vbptr = pdma->logical_base;
2491 vpptr = pdma->physical_base;
2493 pci_free_consistent(pcidev, bsize, vbptr, vpptr);
2494 pdma->logical_base = NULL;
2495 pdma->physical_base = 0;
2499 static void s626_counters_init(struct comedi_device *dev)
2502 const struct s626_enc_info *k;
2504 /* Preload upon index. */
2505 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2506 /* Disable hardware index. */
2507 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2508 /* Operating mode is counter. */
2509 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2510 /* Active high clock. */
2511 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2512 /* Clock multiplier is 1x. */
2513 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2514 /* Enabled by index */
2515 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2518 * Disable all counter interrupts and clear any captured counter events.
2520 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2521 k = &s626_enc_chan_info[chan];
2522 k->set_mode(dev, k, setup, true);
2523 k->set_int_src(dev, k, 0);
2524 k->reset_cap_flags(dev, k);
2525 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
2529 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2531 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2532 struct s626_private *devpriv = dev->private;
2536 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2539 devpriv->ana_buf.logical_base = addr;
2540 devpriv->ana_buf.physical_base = appdma;
2542 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2545 devpriv->rps_buf.logical_base = addr;
2546 devpriv->rps_buf.physical_base = appdma;
2551 static void s626_initialize(struct comedi_device *dev)
2553 struct s626_private *devpriv = dev->private;
2554 dma_addr_t phys_buf;
2558 /* Enable DEBI and audio pins, enable I2C interface */
2559 s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2563 * Configure DEBI operating mode
2565 * Local bus is 16 bits wide
2566 * Declare DEBI transfer timeout interval
2567 * Set up byte lane steering
2568 * Intel-compatible local bus (DEBI never times out)
2570 writel(S626_DEBI_CFG_SLAVE16 |
2571 (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2572 S626_DEBI_CFG_INTEL, devpriv->mmio + S626_P_DEBICFG);
2574 /* Disable MMU paging */
2575 writel(S626_DEBI_PAGE_DISABLE, devpriv->mmio + S626_P_DEBIPAGE);
2577 /* Init GPIO so that ADC Start* is negated */
2578 writel(S626_GPIO_BASE | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2580 /* I2C device address for onboard eeprom (revb) */
2581 devpriv->i2c_adrs = 0xA0;
2584 * Issue an I2C ABORT command to halt any I2C
2585 * operation in progress and reset BUSY flag.
2587 writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2588 devpriv->mmio + S626_P_I2CSTAT);
2589 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2590 while (!(readl(devpriv->mmio + S626_P_MC2) & S626_MC2_UPLD_IIC))
2594 * Per SAA7146 data sheet, write to STATUS
2595 * reg twice to reset all I2C error flags.
2597 for (i = 0; i < 2; i++) {
2598 writel(S626_I2C_CLKSEL, devpriv->mmio + S626_P_I2CSTAT);
2599 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2600 while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2))
2605 * Init audio interface functional attributes: set DAC/ADC
2606 * serial clock rates, invert DAC serial clock so that
2607 * DAC data setup times are satisfied, enable DAC serial
2610 writel(S626_ACON2_INIT, devpriv->mmio + S626_P_ACON2);
2613 * Set up TSL1 slot list, which is used to control the
2614 * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2615 * S626_SIB_A1 = store data uint8_t at next available location
2616 * in FB BUFFER1 register.
2618 writel(S626_RSD1 | S626_SIB_A1, devpriv->mmio + S626_P_TSL1);
2619 writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2620 devpriv->mmio + S626_P_TSL1 + 4);
2622 /* Enable TSL1 slot list so that it executes all the time */
2623 writel(S626_ACON1_ADCSTART, devpriv->mmio + S626_P_ACON1);
2626 * Initialize RPS registers used for ADC
2629 /* Physical start of RPS program */
2630 writel((uint32_t)devpriv->rps_buf.physical_base,
2631 devpriv->mmio + S626_P_RPSADDR1);
2632 /* RPS program performs no explicit mem writes */
2633 writel(0, devpriv->mmio + S626_P_RPSPAGE1);
2634 /* Disable RPS timeouts */
2635 writel(0, devpriv->mmio + S626_P_RPS1_TOUT);
2639 * SAA7146 BUG WORKAROUND
2641 * Initialize SAA7146 ADC interface to a known state by
2642 * invoking ADCs until FB BUFFER 1 register shows that it
2643 * is correctly receiving ADC data. This is necessary
2644 * because the SAA7146 ADC interface does not start up in
2645 * a defined state after a PCI reset.
2652 unsigned int data[16];
2654 /* Create a simple polling list for analog input channel 0 */
2655 poll_list = S626_EOPL;
2656 s626_reset_adc(dev, &poll_list);
2658 /* Get initial ADC value */
2659 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2660 start_val = data[0];
2663 * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2666 * Invoke ADCs until the new ADC value differs from the initial
2667 * value or a timeout occurs. The timeout protects against the
2668 * possibility that the driver is restarting and the ADC data is
2669 * a fixed value resulting from the applied ADC analog input
2670 * being unusually quiet or at the rail.
2672 for (index = 0; index < 500; index++) {
2673 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2675 if (adc_data != start_val)
2679 #endif /* SAA7146 BUG WORKAROUND */
2682 * Initialize the DAC interface
2686 * Init Audio2's output DMAC attributes:
2687 * burst length = 1 DWORD
2688 * threshold = 1 DWORD.
2690 writel(0, devpriv->mmio + S626_P_PCI_BT_A);
2693 * Init Audio2's output DMA physical addresses. The protection
2694 * address is set to 1 DWORD past the base address so that a
2695 * single DWORD will be transferred each time a DMA transfer is
2698 phys_buf = devpriv->ana_buf.physical_base +
2699 (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2700 writel((uint32_t)phys_buf, devpriv->mmio + S626_P_BASEA2_OUT);
2701 writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2702 devpriv->mmio + S626_P_PROTA2_OUT);
2705 * Cache Audio2's output DMA buffer logical address. This is
2706 * where DAC data is buffered for A2 output DMA transfers.
2708 devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2709 S626_DAC_WDMABUF_OS;
2712 * Audio2's output channels does not use paging. The
2713 * protection violation handling bit is set so that the
2714 * DMAC will automatically halt and its PCI address pointer
2715 * will be reset when the protection address is reached.
2717 writel(8, devpriv->mmio + S626_P_PAGEA2_OUT);
2720 * Initialize time slot list 2 (TSL2), which is used to control
2721 * the clock generation for and serialization of data to be sent
2722 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
2723 * execution; this permits other slots to be safely modified
2724 * without first turning off the TSL sequencer (which is
2725 * apparently impossible to do). Also, SD3 (which is driven by a
2726 * pull-up resistor) is shifted in and stored to the MSB of
2727 * FB_BUFFER2 to be used as evidence that the slot sequence has
2728 * not yet finished executing.
2731 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2732 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2733 devpriv->mmio + S626_VECTPORT(0));
2736 * Initialize slot 1, which is constant. Slot 1 causes a
2737 * DWORD to be transferred from audio channel 2's output FIFO
2738 * to the FIFO's output buffer so that it can be serialized
2739 * and sent to the DAC during subsequent slots. All remaining
2740 * slots are dynamically populated as required by the target
2744 /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2745 writel(S626_LF_A2, devpriv->mmio + S626_VECTPORT(1));
2747 /* Start DAC's audio interface (TSL2) running */
2748 writel(S626_ACON1_DACSTART, devpriv->mmio + S626_P_ACON1);
2751 * Init Trim DACs to calibrated values. Do it twice because the
2752 * SAA7146 audio channel does not always reset properly and
2753 * sometimes causes the first few TrimDAC writes to malfunction.
2755 s626_load_trim_dacs(dev);
2756 s626_load_trim_dacs(dev);
2759 * Manually init all gate array hardware in case this is a soft
2760 * reset (we have no way of determining whether this is a warm
2761 * or cold start). This is necessary because the gate array will
2762 * reset only in response to a PCI hard reset; there is no soft
2767 * Init all DAC outputs to 0V and init all DAC setpoint and
2770 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
2771 s626_set_dac(dev, chan, 0);
2774 s626_counters_init(dev);
2777 * Without modifying the state of the Battery Backup enab, disable
2778 * the watchdog timer, set DIO channels 0-5 to operate in the
2779 * standard DIO (vs. counter overflow) mode, disable the battery
2780 * charger, and reset the watchdog interval selector to zero.
2782 s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2783 S626_MISC2_BATT_ENABLE));
2785 /* Initialize the digital I/O subsystem */
2789 static int s626_auto_attach(struct comedi_device *dev,
2790 unsigned long context_unused)
2792 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2793 struct s626_private *devpriv;
2794 struct comedi_subdevice *s;
2797 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2801 ret = comedi_pci_enable(dev);
2805 devpriv->mmio = pci_ioremap_bar(pcidev, 0);
2809 /* disable master interrupt */
2810 writel(0, devpriv->mmio + S626_P_IER);
2813 writel(S626_MC1_SOFT_RESET, devpriv->mmio + S626_P_MC1);
2815 /* DMA FIXME DMA// */
2817 ret = s626_allocate_dma_buffers(dev);
2822 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2823 dev->board_name, dev);
2826 dev->irq = pcidev->irq;
2829 ret = comedi_alloc_subdevices(dev, 6);
2833 s = &dev->subdevices[0];
2834 /* analog input subdevice */
2835 s->type = COMEDI_SUBD_AI;
2836 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
2837 s->n_chan = S626_ADC_CHANNELS;
2838 s->maxdata = 0x3fff;
2839 s->range_table = &s626_range_table;
2840 s->len_chanlist = S626_ADC_CHANNELS;
2841 s->insn_read = s626_ai_insn_read;
2843 dev->read_subdev = s;
2844 s->do_cmd = s626_ai_cmd;
2845 s->do_cmdtest = s626_ai_cmdtest;
2846 s->cancel = s626_ai_cancel;
2849 s = &dev->subdevices[1];
2850 /* analog output subdevice */
2851 s->type = COMEDI_SUBD_AO;
2852 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2853 s->n_chan = S626_DAC_CHANNELS;
2854 s->maxdata = 0x3fff;
2855 s->range_table = &range_bipolar10;
2856 s->insn_write = s626_ao_winsn;
2857 s->insn_read = s626_ao_rinsn;
2859 s = &dev->subdevices[2];
2860 /* digital I/O subdevice */
2861 s->type = COMEDI_SUBD_DIO;
2862 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2865 s->io_bits = 0xffff;
2866 s->private = (void *)0; /* DIO group 0 */
2867 s->range_table = &range_digital;
2868 s->insn_config = s626_dio_insn_config;
2869 s->insn_bits = s626_dio_insn_bits;
2871 s = &dev->subdevices[3];
2872 /* digital I/O subdevice */
2873 s->type = COMEDI_SUBD_DIO;
2874 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2877 s->io_bits = 0xffff;
2878 s->private = (void *)1; /* DIO group 1 */
2879 s->range_table = &range_digital;
2880 s->insn_config = s626_dio_insn_config;
2881 s->insn_bits = s626_dio_insn_bits;
2883 s = &dev->subdevices[4];
2884 /* digital I/O subdevice */
2885 s->type = COMEDI_SUBD_DIO;
2886 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2889 s->io_bits = 0xffff;
2890 s->private = (void *)2; /* DIO group 2 */
2891 s->range_table = &range_digital;
2892 s->insn_config = s626_dio_insn_config;
2893 s->insn_bits = s626_dio_insn_bits;
2895 s = &dev->subdevices[5];
2896 /* encoder (counter) subdevice */
2897 s->type = COMEDI_SUBD_COUNTER;
2898 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2899 s->n_chan = S626_ENCODER_CHANNELS;
2900 s->maxdata = 0xffffff;
2901 s->range_table = &range_unknown;
2902 s->insn_config = s626_enc_insn_config;
2903 s->insn_read = s626_enc_insn_read;
2904 s->insn_write = s626_enc_insn_write;
2906 s626_initialize(dev);
2908 dev_info(dev->class_dev, "%s attached\n", dev->board_name);
2913 static void s626_detach(struct comedi_device *dev)
2915 struct s626_private *devpriv = dev->private;
2918 /* stop ai_command */
2919 devpriv->ai_cmd_running = 0;
2921 if (devpriv->mmio) {
2922 /* interrupt mask */
2923 /* Disable master interrupt */
2924 writel(0, devpriv->mmio + S626_P_IER);
2925 /* Clear board's IRQ status flag */
2926 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2927 devpriv->mmio + S626_P_ISR);
2929 /* Disable the watchdog timer and battery charger. */
2930 s626_write_misc2(dev, 0);
2932 /* Close all interfaces on 7146 device */
2933 writel(S626_MC1_SHUTDOWN, devpriv->mmio + S626_P_MC1);
2934 writel(S626_ACON1_BASE, devpriv->mmio + S626_P_ACON1);
2936 s626_close_dma_b(dev, &devpriv->rps_buf,
2938 s626_close_dma_b(dev, &devpriv->ana_buf,
2943 free_irq(dev->irq, dev);
2945 iounmap(devpriv->mmio);
2947 comedi_pci_disable(dev);
2950 static struct comedi_driver s626_driver = {
2951 .driver_name = "s626",
2952 .module = THIS_MODULE,
2953 .auto_attach = s626_auto_attach,
2954 .detach = s626_detach,
2957 static int s626_pci_probe(struct pci_dev *dev,
2958 const struct pci_device_id *id)
2960 return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2964 * For devices with vendor:device id == 0x1131:0x7146 you must specify
2965 * also subvendor:subdevice ids, because otherwise it will conflict with
2966 * Philips SAA7146 media/dvb based cards.
2968 static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
2969 { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2973 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2975 static struct pci_driver s626_pci_driver = {
2977 .id_table = s626_pci_table,
2978 .probe = s626_pci_probe,
2979 .remove = comedi_pci_auto_unconfig,
2981 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2983 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2984 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2985 MODULE_LICENSE("GPL");