2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
29 Interrupt support originally added by Truxton Fulton
32 References (from ftp://ftp.natinst.com/support/manuals):
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
40 Other possibly relevant info:
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
45 320906c.pdf maximum signal ratings
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
54 - the interrupt routine needs to be cleaned up
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
68 #include "comedi_fc.h"
71 #define MDPRINTK(format, args...)
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
192 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
200 static const struct comedi_lrange *const ni_range_lkup[] = {
201 [ai_gain_16] = &range_ni_E_ai,
202 [ai_gain_8] = &range_ni_E_ai_limited,
203 [ai_gain_14] = &range_ni_E_ai_limited14,
204 [ai_gain_4] = &range_ni_E_ai_bipolar4,
205 [ai_gain_611x] = &range_ni_E_ai_611x,
206 [ai_gain_622x] = &range_ni_M_ai_622x,
207 [ai_gain_628x] = &range_ni_M_ai_628x,
208 [ai_gain_6143] = &range_bipolar5
211 static int ni_dio_insn_config(struct comedi_device *dev,
212 struct comedi_subdevice *s,
213 struct comedi_insn *insn, unsigned int *data);
214 static int ni_dio_insn_bits(struct comedi_device *dev,
215 struct comedi_subdevice *s,
216 struct comedi_insn *insn, unsigned int *data);
217 static int ni_cdio_cmdtest(struct comedi_device *dev,
218 struct comedi_subdevice *s, struct comedi_cmd *cmd);
219 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
220 static int ni_cdio_cancel(struct comedi_device *dev,
221 struct comedi_subdevice *s);
222 static void handle_cdio_interrupt(struct comedi_device *dev);
223 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
224 unsigned int trignum);
226 static int ni_serial_insn_config(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_insn *insn, unsigned int *data);
229 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 unsigned char data_out,
232 unsigned char *data_in);
233 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 unsigned char data_out,
236 unsigned char *data_in);
238 static int ni_calib_insn_read(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 struct comedi_insn *insn, unsigned int *data);
241 static int ni_calib_insn_write(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_insn *insn, unsigned int *data);
245 static int ni_eeprom_insn_read(struct comedi_device *dev,
246 struct comedi_subdevice *s,
247 struct comedi_insn *insn, unsigned int *data);
248 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
249 struct comedi_subdevice *s,
250 struct comedi_insn *insn,
253 static int ni_pfi_insn_bits(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn, unsigned int *data);
256 static int ni_pfi_insn_config(struct comedi_device *dev,
257 struct comedi_subdevice *s,
258 struct comedi_insn *insn, unsigned int *data);
259 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
262 static void ni_rtsi_init(struct comedi_device *dev);
263 static int ni_rtsi_insn_bits(struct comedi_device *dev,
264 struct comedi_subdevice *s,
265 struct comedi_insn *insn, unsigned int *data);
266 static int ni_rtsi_insn_config(struct comedi_device *dev,
267 struct comedi_subdevice *s,
268 struct comedi_insn *insn, unsigned int *data);
270 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
271 static int ni_read_eeprom(struct comedi_device *dev, int addr);
273 #ifdef DEBUG_STATUS_A
274 static void ni_mio_print_status_a(int status);
276 #define ni_mio_print_status_a(a)
278 #ifdef DEBUG_STATUS_B
279 static void ni_mio_print_status_b(int status);
281 #define ni_mio_print_status_b(a)
284 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
286 static void ni_handle_fifo_half_full(struct comedi_device *dev);
287 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
288 struct comedi_subdevice *s);
290 static void ni_handle_fifo_dregs(struct comedi_device *dev);
291 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
292 unsigned int trignum);
293 static void ni_load_channelgain_list(struct comedi_device *dev,
294 unsigned int n_chan, unsigned int *list);
295 static void shutdown_ai_command(struct comedi_device *dev);
297 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
298 unsigned int trignum);
300 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
302 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
304 static int ni_gpct_insn_write(struct comedi_device *dev,
305 struct comedi_subdevice *s,
306 struct comedi_insn *insn, unsigned int *data);
307 static int ni_gpct_insn_read(struct comedi_device *dev,
308 struct comedi_subdevice *s,
309 struct comedi_insn *insn, unsigned int *data);
310 static int ni_gpct_insn_config(struct comedi_device *dev,
311 struct comedi_subdevice *s,
312 struct comedi_insn *insn, unsigned int *data);
313 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
314 static int ni_gpct_cmdtest(struct comedi_device *dev,
315 struct comedi_subdevice *s, struct comedi_cmd *cmd);
316 static int ni_gpct_cancel(struct comedi_device *dev,
317 struct comedi_subdevice *s);
318 static void handle_gpct_interrupt(struct comedi_device *dev,
319 unsigned short counter_index);
321 static int init_cs5529(struct comedi_device *dev);
322 static int cs5529_do_conversion(struct comedi_device *dev,
323 unsigned short *data);
324 static int cs5529_ai_insn_read(struct comedi_device *dev,
325 struct comedi_subdevice *s,
326 struct comedi_insn *insn, unsigned int *data);
327 #ifdef NI_CS5529_DEBUG
328 static unsigned int cs5529_config_read(struct comedi_device *dev,
329 unsigned int reg_select_bits);
331 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
332 unsigned int reg_select_bits);
334 static int ni_m_series_pwm_config(struct comedi_device *dev,
335 struct comedi_subdevice *s,
336 struct comedi_insn *insn, unsigned int *data);
337 static int ni_6143_pwm_config(struct comedi_device *dev,
338 struct comedi_subdevice *s,
339 struct comedi_insn *insn, unsigned int *data);
341 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
343 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
344 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
348 AIMODE_HALF_FULL = 1,
353 enum ni_common_subdevices {
359 NI_CALIBRATION_SUBDEV,
362 NI_CS5529_CALIBRATION_SUBDEV,
370 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
372 switch (counter_index) {
374 return NI_GPCT0_SUBDEV;
377 return NI_GPCT1_SUBDEV;
383 return NI_GPCT0_SUBDEV;
386 enum timebase_nanoseconds {
388 TIMEBASE_2_NS = 10000
391 #define SERIAL_DISABLED 0
392 #define SERIAL_600NS 600
393 #define SERIAL_1_2US 1200
394 #define SERIAL_10US 10000
396 static const int num_adc_stages_611x = 3;
398 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
399 unsigned ai_mite_status);
400 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
401 unsigned ao_mite_status);
402 static void get_last_sample_611x(struct comedi_device *dev);
403 static void get_last_sample_6143(struct comedi_device *dev);
405 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
406 unsigned bit_mask, unsigned bit_values)
408 struct ni_private *devpriv = dev->private;
411 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
413 case Interrupt_A_Enable_Register:
414 devpriv->int_a_enable_reg &= ~bit_mask;
415 devpriv->int_a_enable_reg |= bit_values & bit_mask;
416 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
417 Interrupt_A_Enable_Register);
419 case Interrupt_B_Enable_Register:
420 devpriv->int_b_enable_reg &= ~bit_mask;
421 devpriv->int_b_enable_reg |= bit_values & bit_mask;
422 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
423 Interrupt_B_Enable_Register);
425 case IO_Bidirection_Pin_Register:
426 devpriv->io_bidirection_pin_reg &= ~bit_mask;
427 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
428 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
429 IO_Bidirection_Pin_Register);
432 devpriv->ai_ao_select_reg &= ~bit_mask;
433 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
434 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
437 devpriv->g0_g1_select_reg &= ~bit_mask;
438 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
439 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
442 printk("Warning %s() called with invalid register\n", __func__);
443 printk("reg is %d\n", reg);
447 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
451 static int ni_ai_drain_dma(struct comedi_device *dev);
453 /* DMA channel setup */
455 /* negative channel means no channel */
456 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
462 (ni_stc_dma_channel_select_bitfield(channel) <<
463 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
467 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
470 /* negative channel means no channel */
471 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
477 (ni_stc_dma_channel_select_bitfield(channel) <<
478 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
482 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
485 /* negative mite_channel means no channel */
486 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
492 if (mite_channel >= 0) {
493 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
497 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
501 /* negative mite_channel means no channel */
502 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
505 struct ni_private *devpriv = dev->private;
508 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
509 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
510 if (mite_channel >= 0) {
511 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
512 under the assumption the cdio dma selection works just like ai/ao/gpct.
513 Definitely works for dma channels 0 and 1. */
514 devpriv->cdio_dma_select_reg |=
515 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
516 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
518 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
520 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
523 static int ni_request_ai_mite_channel(struct comedi_device *dev)
525 struct ni_private *devpriv = dev->private;
528 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
529 BUG_ON(devpriv->ai_mite_chan);
530 devpriv->ai_mite_chan =
531 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
532 if (devpriv->ai_mite_chan == NULL) {
533 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
535 "failed to reserve mite dma channel for analog input.");
538 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
539 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
540 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
544 static int ni_request_ao_mite_channel(struct comedi_device *dev)
546 struct ni_private *devpriv = dev->private;
549 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
550 BUG_ON(devpriv->ao_mite_chan);
551 devpriv->ao_mite_chan =
552 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
553 if (devpriv->ao_mite_chan == NULL) {
554 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
556 "failed to reserve mite dma channel for analog outut.");
559 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
560 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
561 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
565 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
567 enum comedi_io_direction direction)
569 struct ni_private *devpriv = dev->private;
571 struct mite_channel *mite_chan;
573 BUG_ON(gpct_index >= NUM_GPCT);
574 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
575 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
577 mite_request_channel(devpriv->mite,
578 devpriv->gpct_mite_ring[gpct_index]);
579 if (mite_chan == NULL) {
580 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
582 "failed to reserve mite dma channel for counter.");
585 mite_chan->dir = direction;
586 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
588 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
589 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
595 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
598 struct ni_private *devpriv = dev->private;
601 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
602 BUG_ON(devpriv->cdo_mite_chan);
603 devpriv->cdo_mite_chan =
604 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
605 if (devpriv->cdo_mite_chan == NULL) {
606 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
608 "failed to reserve mite dma channel for correlated digital outut.");
611 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
612 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
613 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
618 static void ni_release_ai_mite_channel(struct comedi_device *dev)
621 struct ni_private *devpriv = dev->private;
624 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
625 if (devpriv->ai_mite_chan) {
626 ni_set_ai_dma_channel(dev, -1);
627 mite_release_channel(devpriv->ai_mite_chan);
628 devpriv->ai_mite_chan = NULL;
630 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
634 static void ni_release_ao_mite_channel(struct comedi_device *dev)
637 struct ni_private *devpriv = dev->private;
640 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
641 if (devpriv->ao_mite_chan) {
642 ni_set_ao_dma_channel(dev, -1);
643 mite_release_channel(devpriv->ao_mite_chan);
644 devpriv->ao_mite_chan = NULL;
646 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
651 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
654 struct ni_private *devpriv = dev->private;
657 BUG_ON(gpct_index >= NUM_GPCT);
658 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
659 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
660 struct mite_channel *mite_chan =
661 devpriv->counter_dev->counters[gpct_index].mite_chan;
663 ni_set_gpct_dma_channel(dev, gpct_index, -1);
664 ni_tio_set_mite_channel(&devpriv->
665 counter_dev->counters[gpct_index],
667 mite_release_channel(mite_chan);
669 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
673 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
676 struct ni_private *devpriv = dev->private;
679 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
680 if (devpriv->cdo_mite_chan) {
681 ni_set_cdo_dma_channel(dev, -1);
682 mite_release_channel(devpriv->cdo_mite_chan);
683 devpriv->cdo_mite_chan = NULL;
685 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
689 /* e-series boards use the second irq signals to generate dma requests for their counters */
691 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
692 unsigned gpct_index, short enable)
694 const struct ni_board_struct *board = comedi_board(dev);
695 struct ni_private *devpriv = dev->private;
697 if (board->reg_type & ni_reg_m_series_mask)
699 switch (gpct_index) {
702 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
703 Second_IRQ_A_Enable_Register);
705 devpriv->stc_writew(dev, 0,
706 Second_IRQ_A_Enable_Register);
711 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
712 Second_IRQ_B_Enable_Register);
714 devpriv->stc_writew(dev, 0,
715 Second_IRQ_B_Enable_Register);
725 static void ni_clear_ai_fifo(struct comedi_device *dev)
727 const struct ni_board_struct *board = comedi_board(dev);
728 struct ni_private *devpriv = dev->private;
730 if (board->reg_type == ni_reg_6143) {
731 /* Flush the 6143 data FIFO */
732 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
733 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
734 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
736 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
737 if (board->reg_type == ni_reg_625x) {
738 ni_writeb(0, M_Offset_Static_AI_Control(0));
739 ni_writeb(1, M_Offset_Static_AI_Control(0));
741 /* the NI example code does 3 convert pulses for 625x boards,
742 but that appears to be wrong in practice. */
743 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
744 AI_Command_1_Register);
745 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
746 AI_Command_1_Register);
747 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
748 AI_Command_1_Register);
754 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
756 struct ni_private *devpriv = dev->private;
758 devpriv->stc_writew(dev, data >> 16, reg);
759 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
762 static uint32_t win_in2(struct comedi_device *dev, int reg)
764 struct ni_private *devpriv = dev->private;
767 bits = devpriv->stc_readw(dev, reg) << 16;
768 bits |= devpriv->stc_readw(dev, reg + 1);
772 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
773 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
776 struct ni_private *devpriv = dev->private;
779 spin_lock_irqsave(&devpriv->window_lock, flags);
780 ni_writew(addr, AO_Window_Address_611x);
781 ni_writew(data, AO_Window_Data_611x);
782 spin_unlock_irqrestore(&devpriv->window_lock, flags);
785 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
788 struct ni_private *devpriv = dev->private;
791 spin_lock_irqsave(&devpriv->window_lock, flags);
792 ni_writew(addr, AO_Window_Address_611x);
793 ni_writel(data, AO_Window_Data_611x);
794 spin_unlock_irqrestore(&devpriv->window_lock, flags);
797 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
799 struct ni_private *devpriv = dev->private;
803 spin_lock_irqsave(&devpriv->window_lock, flags);
804 ni_writew(addr, AO_Window_Address_611x);
805 data = ni_readw(AO_Window_Data_611x);
806 spin_unlock_irqrestore(&devpriv->window_lock, flags);
810 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
811 * share registers (such as Interrupt_A_Register) without interfering with
814 * NOTE: the switch/case statements are optimized out for a constant argument
815 * so this is actually quite fast--- If you must wrap another function around this
816 * make it inline to avoid a large speed penalty.
818 * value should only be 1 or 0.
820 static inline void ni_set_bits(struct comedi_device *dev, int reg,
821 unsigned bits, unsigned value)
829 ni_set_bitfield(dev, reg, bits, bit_values);
832 static irqreturn_t ni_E_interrupt(int irq, void *d)
834 struct comedi_device *dev = d;
835 struct ni_private *devpriv = dev->private;
836 unsigned short a_status;
837 unsigned short b_status;
838 unsigned int ai_mite_status = 0;
839 unsigned int ao_mite_status = 0;
842 struct mite_struct *mite = devpriv->mite;
847 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
849 /* lock to avoid race with comedi_poll */
850 spin_lock_irqsave(&dev->spinlock, flags);
851 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
852 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
855 unsigned long flags_too;
857 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
858 if (devpriv->ai_mite_chan) {
859 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
860 if (ai_mite_status & CHSR_LINKC)
862 devpriv->mite->mite_io_addr +
864 ai_mite_chan->channel));
866 if (devpriv->ao_mite_chan) {
867 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
868 if (ao_mite_status & CHSR_LINKC)
872 ao_mite_chan->channel));
874 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
877 ack_a_interrupt(dev, a_status);
878 ack_b_interrupt(dev, b_status);
879 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
880 handle_a_interrupt(dev, a_status, ai_mite_status);
881 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
882 handle_b_interrupt(dev, b_status, ao_mite_status);
883 handle_gpct_interrupt(dev, 0);
884 handle_gpct_interrupt(dev, 1);
885 handle_cdio_interrupt(dev);
887 spin_unlock_irqrestore(&dev->spinlock, flags);
892 static void ni_sync_ai_dma(struct comedi_device *dev)
894 struct ni_private *devpriv = dev->private;
895 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
898 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
899 if (devpriv->ai_mite_chan)
900 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
901 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
904 static void mite_handle_b_linkc(struct mite_struct *mite,
905 struct comedi_device *dev)
907 struct ni_private *devpriv = dev->private;
908 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
911 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
912 if (devpriv->ao_mite_chan) {
913 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
915 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
918 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
920 struct ni_private *devpriv = dev->private;
921 static const int timeout = 10000;
923 for (i = 0; i < timeout; i++) {
924 unsigned short b_status;
926 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
927 if (b_status & AO_FIFO_Half_Full_St)
929 /* if we poll too often, the pci bus activity seems
930 to slow the dma transfer down */
934 comedi_error(dev, "timed out waiting for dma load");
941 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
943 struct ni_private *devpriv = dev->private;
945 if (devpriv->aimode == AIMODE_SCAN) {
947 static const int timeout = 10;
950 for (i = 0; i < timeout; i++) {
952 if ((s->async->events & COMEDI_CB_EOS))
957 ni_handle_fifo_dregs(dev);
958 s->async->events |= COMEDI_CB_EOS;
961 /* handle special case of single scan using AI_End_On_End_Of_Scan */
962 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
963 shutdown_ai_command(dev);
967 static void shutdown_ai_command(struct comedi_device *dev)
969 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
972 ni_ai_drain_dma(dev);
974 ni_handle_fifo_dregs(dev);
975 get_last_sample_611x(dev);
976 get_last_sample_6143(dev);
978 s->async->events |= COMEDI_CB_EOA;
981 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
984 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
993 case NI_GPCT0_SUBDEV:
994 case NI_GPCT1_SUBDEV:
995 ni_gpct_cancel(dev, s);
998 ni_cdio_cancel(dev, s);
1004 comedi_event(dev, s);
1007 static void handle_gpct_interrupt(struct comedi_device *dev,
1008 unsigned short counter_index)
1011 struct ni_private *devpriv = dev->private;
1012 struct comedi_subdevice *s;
1014 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1016 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1018 if (s->async->events)
1023 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1025 struct ni_private *devpriv = dev->private;
1026 unsigned short ack = 0;
1028 if (a_status & AI_SC_TC_St) {
1029 ack |= AI_SC_TC_Interrupt_Ack;
1031 if (a_status & AI_START1_St) {
1032 ack |= AI_START1_Interrupt_Ack;
1034 if (a_status & AI_START_St) {
1035 ack |= AI_START_Interrupt_Ack;
1037 if (a_status & AI_STOP_St) {
1038 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1039 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1042 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1045 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1046 unsigned ai_mite_status)
1048 struct ni_private *devpriv = dev->private;
1049 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1051 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1052 if (s->type == COMEDI_SUBD_UNUSED)
1055 #ifdef DEBUG_INTERRUPT
1057 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1058 status, ai_mite_status);
1059 ni_mio_print_status_a(status);
1062 if (ai_mite_status & CHSR_LINKC) {
1063 ni_sync_ai_dma(dev);
1066 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1067 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1068 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1070 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1072 /* mite_print_chsr(ai_mite_status); */
1073 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1074 /* disable_irq(dev->irq); */
1078 /* test for all uncommon interrupt events at the same time */
1079 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1080 AI_SC_TC_St | AI_START1_St)) {
1081 if (status == 0xffff) {
1083 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1084 /* we probably aren't even running a command now,
1085 * so it's a good idea to be careful. */
1086 if (comedi_is_subdevice_running(s)) {
1088 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1093 if (status & (AI_Overrun_St | AI_Overflow_St |
1094 AI_SC_TC_Error_St)) {
1095 printk("ni_mio_common: ai error a_status=%04x\n",
1097 ni_mio_print_status_a(status);
1099 shutdown_ai_command(dev);
1101 s->async->events |= COMEDI_CB_ERROR;
1102 if (status & (AI_Overrun_St | AI_Overflow_St))
1103 s->async->events |= COMEDI_CB_OVERFLOW;
1109 if (status & AI_SC_TC_St) {
1110 #ifdef DEBUG_INTERRUPT
1111 printk("ni_mio_common: SC_TC interrupt\n");
1113 if (!devpriv->ai_continuous) {
1114 shutdown_ai_command(dev);
1119 if (status & AI_FIFO_Half_Full_St) {
1121 static const int timeout = 10;
1122 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1123 *fail to get the fifo less than half full, so loop to be sure.*/
1124 for (i = 0; i < timeout; ++i) {
1125 ni_handle_fifo_half_full(dev);
1126 if ((devpriv->stc_readw(dev,
1127 AI_Status_1_Register) &
1128 AI_FIFO_Half_Full_St) == 0)
1132 #endif /* !PCIDMA */
1134 if ((status & AI_STOP_St)) {
1135 ni_handle_eos(dev, s);
1140 #ifdef DEBUG_INTERRUPT
1141 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1142 if (status & Interrupt_A_St) {
1144 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1150 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1152 struct ni_private *devpriv = dev->private;
1153 unsigned short ack = 0;
1155 if (b_status & AO_BC_TC_St) {
1156 ack |= AO_BC_TC_Interrupt_Ack;
1158 if (b_status & AO_Overrun_St) {
1159 ack |= AO_Error_Interrupt_Ack;
1161 if (b_status & AO_START_St) {
1162 ack |= AO_START_Interrupt_Ack;
1164 if (b_status & AO_START1_St) {
1165 ack |= AO_START1_Interrupt_Ack;
1167 if (b_status & AO_UC_TC_St) {
1168 ack |= AO_UC_TC_Interrupt_Ack;
1170 if (b_status & AO_UI2_TC_St) {
1171 ack |= AO_UI2_TC_Interrupt_Ack;
1173 if (b_status & AO_UPDATE_St) {
1174 ack |= AO_UPDATE_Interrupt_Ack;
1177 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1180 static void handle_b_interrupt(struct comedi_device *dev,
1181 unsigned short b_status, unsigned ao_mite_status)
1183 struct ni_private *devpriv = dev->private;
1184 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1185 /* unsigned short ack=0; */
1187 #ifdef DEBUG_INTERRUPT
1188 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1189 b_status, ao_mite_status);
1190 ni_mio_print_status_b(b_status);
1194 /* Currently, mite.c requires us to handle LINKC */
1195 if (ao_mite_status & CHSR_LINKC) {
1196 mite_handle_b_linkc(devpriv->mite, dev);
1199 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1200 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1201 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1203 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1205 /* mite_print_chsr(ao_mite_status); */
1206 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1210 if (b_status == 0xffff)
1212 if (b_status & AO_Overrun_St) {
1214 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1215 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1216 s->async->events |= COMEDI_CB_OVERFLOW;
1219 if (b_status & AO_BC_TC_St) {
1221 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1222 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1223 s->async->events |= COMEDI_CB_EOA;
1226 if (b_status & AO_FIFO_Request_St) {
1229 ret = ni_ao_fifo_half_empty(dev, s);
1231 printk("ni_mio_common: AO buffer underrun\n");
1232 ni_set_bits(dev, Interrupt_B_Enable_Register,
1233 AO_FIFO_Interrupt_Enable |
1234 AO_Error_Interrupt_Enable, 0);
1235 s->async->events |= COMEDI_CB_OVERFLOW;
1243 #ifdef DEBUG_STATUS_A
1244 static const char *const status_a_strings[] = {
1245 "passthru0", "fifo", "G0_gate", "G0_TC",
1246 "stop", "start", "sc_tc", "start1",
1247 "start2", "sc_tc_error", "overflow", "overrun",
1248 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1251 static void ni_mio_print_status_a(int status)
1255 printk("A status:");
1256 for (i = 15; i >= 0; i--) {
1257 if (status & (1 << i)) {
1258 printk(" %s", status_a_strings[i]);
1265 #ifdef DEBUG_STATUS_B
1266 static const char *const status_b_strings[] = {
1267 "passthru1", "fifo", "G1_gate", "G1_TC",
1268 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1269 "start1", "overrun", "start", "bc_tc_error",
1270 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1273 static void ni_mio_print_status_b(int status)
1277 printk("B status:");
1278 for (i = 15; i >= 0; i--) {
1279 if (status & (1 << i)) {
1280 printk(" %s", status_b_strings[i]);
1289 static void ni_ao_fifo_load(struct comedi_device *dev,
1290 struct comedi_subdevice *s, int n)
1292 const struct ni_board_struct *board = comedi_board(dev);
1293 struct comedi_async *async = s->async;
1294 struct comedi_cmd *cmd = &async->cmd;
1302 chan = async->cur_chan;
1303 for (i = 0; i < n; i++) {
1304 err &= comedi_buf_get(async, &d);
1308 range = CR_RANGE(cmd->chanlist[chan]);
1310 if (board->reg_type & ni_reg_6xxx_mask) {
1311 packed_data = d & 0xffff;
1312 /* 6711 only has 16 bit wide ao fifo */
1313 if (board->reg_type != ni_reg_6711) {
1314 err &= comedi_buf_get(async, &d);
1319 packed_data |= (d << 16) & 0xffff0000;
1321 ni_writel(packed_data, DAC_FIFO_Data_611x);
1323 ni_writew(d, DAC_FIFO_Data);
1326 chan %= cmd->chanlist_len;
1328 async->cur_chan = chan;
1330 async->events |= COMEDI_CB_OVERFLOW;
1335 * There's a small problem if the FIFO gets really low and we
1336 * don't have the data to fill it. Basically, if after we fill
1337 * the FIFO with all the data available, the FIFO is _still_
1338 * less than half full, we never clear the interrupt. If the
1339 * IRQ is in edge mode, we never get another interrupt, because
1340 * this one wasn't cleared. If in level mode, we get flooded
1341 * with interrupts that we can't fulfill, because nothing ever
1342 * gets put into the buffer.
1344 * This kind of situation is recoverable, but it is easier to
1345 * just pretend we had a FIFO underrun, since there is a good
1346 * chance it will happen anyway. This is _not_ the case for
1347 * RT code, as RT code might purposely be running close to the
1348 * metal. Needs to be fixed eventually.
1350 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1351 struct comedi_subdevice *s)
1353 const struct ni_board_struct *board = comedi_board(dev);
1356 n = comedi_buf_read_n_available(s->async);
1358 s->async->events |= COMEDI_CB_OVERFLOW;
1363 if (n > board->ao_fifo_depth / 2)
1364 n = board->ao_fifo_depth / 2;
1366 ni_ao_fifo_load(dev, s, n);
1368 s->async->events |= COMEDI_CB_BLOCK;
1373 static int ni_ao_prep_fifo(struct comedi_device *dev,
1374 struct comedi_subdevice *s)
1376 const struct ni_board_struct *board = comedi_board(dev);
1377 struct ni_private *devpriv = dev->private;
1381 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1382 if (board->reg_type & ni_reg_6xxx_mask)
1383 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1385 /* load some data */
1386 n = comedi_buf_read_n_available(s->async);
1391 if (n > board->ao_fifo_depth)
1392 n = board->ao_fifo_depth;
1394 ni_ao_fifo_load(dev, s, n);
1399 static void ni_ai_fifo_read(struct comedi_device *dev,
1400 struct comedi_subdevice *s, int n)
1402 const struct ni_board_struct *board = comedi_board(dev);
1403 struct ni_private *devpriv = dev->private;
1404 struct comedi_async *async = s->async;
1407 if (board->reg_type == ni_reg_611x) {
1411 for (i = 0; i < n / 2; i++) {
1412 dl = ni_readl(ADC_FIFO_Data_611x);
1413 /* This may get the hi/lo data in the wrong order */
1414 data[0] = (dl >> 16) & 0xffff;
1415 data[1] = dl & 0xffff;
1416 cfc_write_array_to_buffer(s, data, sizeof(data));
1418 /* Check if there's a single sample stuck in the FIFO */
1420 dl = ni_readl(ADC_FIFO_Data_611x);
1421 data[0] = dl & 0xffff;
1422 cfc_write_to_buffer(s, data[0]);
1424 } else if (board->reg_type == ni_reg_6143) {
1428 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1429 for (i = 0; i < n / 2; i++) {
1430 dl = ni_readl(AIFIFO_Data_6143);
1432 data[0] = (dl >> 16) & 0xffff;
1433 data[1] = dl & 0xffff;
1434 cfc_write_array_to_buffer(s, data, sizeof(data));
1437 /* Assume there is a single sample stuck in the FIFO */
1438 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1439 dl = ni_readl(AIFIFO_Data_6143);
1440 data[0] = (dl >> 16) & 0xffff;
1441 cfc_write_to_buffer(s, data[0]);
1444 if (n > sizeof(devpriv->ai_fifo_buffer) /
1445 sizeof(devpriv->ai_fifo_buffer[0])) {
1446 comedi_error(dev, "bug! ai_fifo_buffer too small");
1447 async->events |= COMEDI_CB_ERROR;
1450 for (i = 0; i < n; i++) {
1451 devpriv->ai_fifo_buffer[i] =
1452 ni_readw(ADC_FIFO_Data_Register);
1454 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1456 sizeof(devpriv->ai_fifo_buffer[0]));
1460 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1462 const struct ni_board_struct *board = comedi_board(dev);
1463 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1466 n = board->ai_fifo_depth / 2;
1468 ni_ai_fifo_read(dev, s, n);
1473 static int ni_ai_drain_dma(struct comedi_device *dev)
1475 struct ni_private *devpriv = dev->private;
1477 static const int timeout = 10000;
1478 unsigned long flags;
1481 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1482 if (devpriv->ai_mite_chan) {
1483 for (i = 0; i < timeout; i++) {
1484 if ((devpriv->stc_readw(dev,
1485 AI_Status_1_Register) &
1487 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1493 printk("ni_mio_common: wait for dma drain timed out\n");
1495 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1496 mite_bytes_in_transit(devpriv->ai_mite_chan),
1497 devpriv->stc_readw(dev, AI_Status_1_Register));
1501 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1503 ni_sync_ai_dma(dev);
1511 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1513 const struct ni_board_struct *board = comedi_board(dev);
1514 struct ni_private *devpriv = dev->private;
1515 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1521 if (board->reg_type == ni_reg_611x) {
1522 while ((devpriv->stc_readw(dev,
1523 AI_Status_1_Register) &
1524 AI_FIFO_Empty_St) == 0) {
1525 dl = ni_readl(ADC_FIFO_Data_611x);
1527 /* This may get the hi/lo data in the wrong order */
1528 data[0] = (dl >> 16);
1529 data[1] = (dl & 0xffff);
1530 cfc_write_array_to_buffer(s, data, sizeof(data));
1532 } else if (board->reg_type == ni_reg_6143) {
1534 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1535 dl = ni_readl(AIFIFO_Data_6143);
1537 /* This may get the hi/lo data in the wrong order */
1538 data[0] = (dl >> 16);
1539 data[1] = (dl & 0xffff);
1540 cfc_write_array_to_buffer(s, data, sizeof(data));
1543 /* Check if stranded sample is present */
1544 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1545 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1546 dl = ni_readl(AIFIFO_Data_6143);
1547 data[0] = (dl >> 16) & 0xffff;
1548 cfc_write_to_buffer(s, data[0]);
1553 devpriv->stc_readw(dev,
1554 AI_Status_1_Register) & AI_FIFO_Empty_St;
1555 while (fifo_empty == 0) {
1558 sizeof(devpriv->ai_fifo_buffer) /
1559 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1561 devpriv->stc_readw(dev,
1562 AI_Status_1_Register) &
1566 devpriv->ai_fifo_buffer[i] =
1567 ni_readw(ADC_FIFO_Data_Register);
1569 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1572 ai_fifo_buffer[0]));
1577 static void get_last_sample_611x(struct comedi_device *dev)
1579 const struct ni_board_struct *board = comedi_board(dev);
1580 struct ni_private *devpriv __maybe_unused = dev->private;
1581 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1585 if (board->reg_type != ni_reg_611x)
1588 /* Check if there's a single sample stuck in the FIFO */
1589 if (ni_readb(XXX_Status) & 0x80) {
1590 dl = ni_readl(ADC_FIFO_Data_611x);
1591 data = (dl & 0xffff);
1592 cfc_write_to_buffer(s, data);
1596 static void get_last_sample_6143(struct comedi_device *dev)
1598 const struct ni_board_struct *board = comedi_board(dev);
1599 struct ni_private *devpriv __maybe_unused = dev->private;
1600 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1604 if (board->reg_type != ni_reg_6143)
1607 /* Check if there's a single sample stuck in the FIFO */
1608 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1609 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1610 dl = ni_readl(AIFIFO_Data_6143);
1612 /* This may get the hi/lo data in the wrong order */
1613 data = (dl >> 16) & 0xffff;
1614 cfc_write_to_buffer(s, data);
1618 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1619 void *data, unsigned int num_bytes,
1620 unsigned int chan_index)
1622 struct ni_private *devpriv = dev->private;
1623 struct comedi_async *async = s->async;
1625 unsigned int length = num_bytes / bytes_per_sample(s);
1626 short *array = data;
1627 unsigned int *larray = data;
1629 for (i = 0; i < length; i++) {
1631 if (s->subdev_flags & SDF_LSAMPL)
1632 larray[i] = le32_to_cpu(larray[i]);
1634 array[i] = le16_to_cpu(array[i]);
1636 if (s->subdev_flags & SDF_LSAMPL)
1637 larray[i] += devpriv->ai_offset[chan_index];
1639 array[i] += devpriv->ai_offset[chan_index];
1641 chan_index %= async->cmd.chanlist_len;
1647 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1649 const struct ni_board_struct *board = comedi_board(dev);
1650 struct ni_private *devpriv = dev->private;
1651 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1653 unsigned long flags;
1655 retval = ni_request_ai_mite_channel(dev);
1658 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1660 /* write alloc the entire buffer */
1661 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1663 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1664 if (devpriv->ai_mite_chan == NULL) {
1665 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1669 switch (board->reg_type) {
1672 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1675 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1678 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1682 mite_dma_arm(devpriv->ai_mite_chan);
1683 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1688 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1690 const struct ni_board_struct *board = comedi_board(dev);
1691 struct ni_private *devpriv = dev->private;
1692 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1694 unsigned long flags;
1696 retval = ni_request_ao_mite_channel(dev);
1700 /* read alloc the entire buffer */
1701 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1703 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1704 if (devpriv->ao_mite_chan) {
1705 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1706 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1708 /* doing 32 instead of 16 bit wide transfers from memory
1709 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1710 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1712 mite_dma_arm(devpriv->ao_mite_chan);
1715 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1723 used for both cancel ioctl and board initialization
1725 this is pretty harsh for a cancel, but it works...
1728 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1730 const struct ni_board_struct *board = comedi_board(dev);
1731 struct ni_private *devpriv = dev->private;
1733 ni_release_ai_mite_channel(dev);
1734 /* ai configuration */
1735 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1736 Joint_Reset_Register);
1738 ni_set_bits(dev, Interrupt_A_Enable_Register,
1739 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1740 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1741 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1742 AI_FIFO_Interrupt_Enable, 0);
1744 ni_clear_ai_fifo(dev);
1746 if (board->reg_type != ni_reg_6143)
1747 ni_writeb(0, Misc_Command);
1749 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1750 devpriv->stc_writew(dev,
1751 AI_Start_Stop | AI_Mode_1_Reserved
1752 /*| AI_Trigger_Once */ ,
1753 AI_Mode_1_Register);
1754 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1755 /* generate FIFO interrupts on non-empty */
1756 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1757 if (board->reg_type == ni_reg_611x) {
1758 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1760 AI_LOCALMUX_CLK_Pulse_Width,
1761 AI_Personal_Register);
1762 devpriv->stc_writew(dev,
1763 AI_SCAN_IN_PROG_Output_Select(3) |
1764 AI_EXTMUX_CLK_Output_Select(0) |
1765 AI_LOCALMUX_CLK_Output_Select(2) |
1766 AI_SC_TC_Output_Select(3) |
1767 AI_CONVERT_Output_Select
1768 (AI_CONVERT_Output_Enable_High),
1769 AI_Output_Control_Register);
1770 } else if (board->reg_type == ni_reg_6143) {
1771 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1773 AI_LOCALMUX_CLK_Pulse_Width,
1774 AI_Personal_Register);
1775 devpriv->stc_writew(dev,
1776 AI_SCAN_IN_PROG_Output_Select(3) |
1777 AI_EXTMUX_CLK_Output_Select(0) |
1778 AI_LOCALMUX_CLK_Output_Select(2) |
1779 AI_SC_TC_Output_Select(3) |
1780 AI_CONVERT_Output_Select
1781 (AI_CONVERT_Output_Enable_Low),
1782 AI_Output_Control_Register);
1784 unsigned ai_output_control_bits;
1785 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1787 AI_CONVERT_Pulse_Width |
1788 AI_LOCALMUX_CLK_Pulse_Width,
1789 AI_Personal_Register);
1790 ai_output_control_bits =
1791 AI_SCAN_IN_PROG_Output_Select(3) |
1792 AI_EXTMUX_CLK_Output_Select(0) |
1793 AI_LOCALMUX_CLK_Output_Select(2) |
1794 AI_SC_TC_Output_Select(3);
1795 if (board->reg_type == ni_reg_622x)
1796 ai_output_control_bits |=
1797 AI_CONVERT_Output_Select
1798 (AI_CONVERT_Output_Enable_High);
1800 ai_output_control_bits |=
1801 AI_CONVERT_Output_Select
1802 (AI_CONVERT_Output_Enable_Low);
1803 devpriv->stc_writew(dev, ai_output_control_bits,
1804 AI_Output_Control_Register);
1806 /* the following registers should not be changed, because there
1807 * are no backup registers in devpriv. If you want to change
1808 * any of these, add a backup register and other appropriate code:
1809 * AI_Mode_1_Register
1810 * AI_Mode_3_Register
1811 * AI_Personal_Register
1812 * AI_Output_Control_Register
1814 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1816 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1821 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1823 unsigned long flags;
1826 /* lock to avoid race with interrupt handler */
1827 spin_lock_irqsave(&dev->spinlock, flags);
1829 ni_handle_fifo_dregs(dev);
1831 ni_sync_ai_dma(dev);
1833 count = s->async->buf_write_count - s->async->buf_read_count;
1834 spin_unlock_irqrestore(&dev->spinlock, flags);
1839 static int ni_ai_insn_read(struct comedi_device *dev,
1840 struct comedi_subdevice *s, struct comedi_insn *insn,
1843 const struct ni_board_struct *board = comedi_board(dev);
1844 struct ni_private *devpriv = dev->private;
1846 const unsigned int mask = (1 << board->adbits) - 1;
1851 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1853 ni_clear_ai_fifo(dev);
1855 signbits = devpriv->ai_offset[0];
1856 if (board->reg_type == ni_reg_611x) {
1857 for (n = 0; n < num_adc_stages_611x; n++) {
1858 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1859 AI_Command_1_Register);
1862 for (n = 0; n < insn->n; n++) {
1863 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1864 AI_Command_1_Register);
1865 /* The 611x has screwy 32-bit FIFOs. */
1867 for (i = 0; i < NI_TIMEOUT; i++) {
1868 if (ni_readb(XXX_Status) & 0x80) {
1869 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1873 if (!(devpriv->stc_readw(dev,
1874 AI_Status_1_Register) &
1875 AI_FIFO_Empty_St)) {
1876 d = ni_readl(ADC_FIFO_Data_611x) &
1881 if (i == NI_TIMEOUT) {
1883 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1889 } else if (board->reg_type == ni_reg_6143) {
1890 for (n = 0; n < insn->n; n++) {
1891 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1892 AI_Command_1_Register);
1894 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1896 for (i = 0; i < NI_TIMEOUT; i++) {
1897 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1898 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1899 dl = ni_readl(AIFIFO_Data_6143);
1903 if (i == NI_TIMEOUT) {
1905 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1908 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1911 for (n = 0; n < insn->n; n++) {
1912 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1913 AI_Command_1_Register);
1914 for (i = 0; i < NI_TIMEOUT; i++) {
1915 if (!(devpriv->stc_readw(dev,
1916 AI_Status_1_Register) &
1920 if (i == NI_TIMEOUT) {
1922 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1925 if (board->reg_type & ni_reg_m_series_mask) {
1927 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1929 d = ni_readw(ADC_FIFO_Data_Register);
1930 d += signbits; /* subtle: needs to be short addition */
1938 static void ni_prime_channelgain_list(struct comedi_device *dev)
1940 struct ni_private *devpriv = dev->private;
1943 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1944 for (i = 0; i < NI_TIMEOUT; ++i) {
1945 if (!(devpriv->stc_readw(dev,
1946 AI_Status_1_Register) &
1947 AI_FIFO_Empty_St)) {
1948 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1953 printk("ni_mio_common: timeout loading channel/gain list\n");
1956 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1957 unsigned int n_chan,
1960 const struct ni_board_struct *board = comedi_board(dev);
1961 struct ni_private *devpriv = dev->private;
1962 unsigned int chan, range, aref;
1965 unsigned int dither;
1966 unsigned range_code;
1968 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1970 /* offset = 1 << (board->adbits - 1); */
1971 if ((list[0] & CR_ALT_SOURCE)) {
1972 unsigned bypass_bits;
1973 chan = CR_CHAN(list[0]);
1974 range = CR_RANGE(list[0]);
1975 range_code = ni_gainlkup[board->gainlkup][range];
1976 dither = ((list[0] & CR_ALT_FILTER) != 0);
1977 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1978 bypass_bits |= chan;
1980 (devpriv->ai_calib_source) &
1981 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1982 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1983 MSeries_AI_Bypass_Mode_Mux_Mask |
1984 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1985 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1987 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1988 /* don't use 2's complement encoding */
1989 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1990 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1992 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1995 for (i = 0; i < n_chan; i++) {
1996 unsigned config_bits = 0;
1997 chan = CR_CHAN(list[i]);
1998 aref = CR_AREF(list[i]);
1999 range = CR_RANGE(list[i]);
2000 dither = ((list[i] & CR_ALT_FILTER) != 0);
2002 range_code = ni_gainlkup[board->gainlkup][range];
2003 devpriv->ai_offset[i] = offset;
2007 MSeries_AI_Config_Channel_Type_Differential_Bits;
2011 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2015 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2020 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2022 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2023 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2024 if (i == n_chan - 1)
2025 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2027 config_bits |= MSeries_AI_Config_Dither_Bit;
2028 /* don't use 2's complement encoding */
2029 config_bits |= MSeries_AI_Config_Polarity_Bit;
2030 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2032 ni_prime_channelgain_list(dev);
2036 * Notes on the 6110 and 6111:
2037 * These boards a slightly different than the rest of the series, since
2038 * they have multiple A/D converters.
2039 * From the driver side, the configuration memory is a
2041 * Configuration Memory Low:
2043 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2044 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2045 * 1001 gain=0.1 (+/- 50)
2054 * Configuration Memory High:
2055 * bits 12-14: Channel Type
2056 * 001 for differential
2057 * 000 for calibration
2058 * bit 11: coupling (this is not currently handled)
2062 * valid channels are 0-3
2064 static void ni_load_channelgain_list(struct comedi_device *dev,
2065 unsigned int n_chan, unsigned int *list)
2067 const struct ni_board_struct *board = comedi_board(dev);
2068 struct ni_private *devpriv = dev->private;
2069 unsigned int chan, range, aref;
2071 unsigned int hi, lo;
2073 unsigned int dither;
2075 if (board->reg_type & ni_reg_m_series_mask) {
2076 ni_m_series_load_channelgain_list(dev, n_chan, list);
2079 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2080 && (board->reg_type != ni_reg_6143)) {
2081 if (devpriv->changain_state
2082 && devpriv->changain_spec == list[0]) {
2086 devpriv->changain_state = 1;
2087 devpriv->changain_spec = list[0];
2089 devpriv->changain_state = 0;
2092 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2094 /* Set up Calibration mode if required */
2095 if (board->reg_type == ni_reg_6143) {
2096 if ((list[0] & CR_ALT_SOURCE)
2097 && !devpriv->ai_calib_source_enabled) {
2098 /* Strobe Relay enable bit */
2099 ni_writew(devpriv->ai_calib_source |
2100 Calibration_Channel_6143_RelayOn,
2101 Calibration_Channel_6143);
2102 ni_writew(devpriv->ai_calib_source,
2103 Calibration_Channel_6143);
2104 devpriv->ai_calib_source_enabled = 1;
2105 msleep_interruptible(100); /* Allow relays to change */
2106 } else if (!(list[0] & CR_ALT_SOURCE)
2107 && devpriv->ai_calib_source_enabled) {
2108 /* Strobe Relay disable bit */
2109 ni_writew(devpriv->ai_calib_source |
2110 Calibration_Channel_6143_RelayOff,
2111 Calibration_Channel_6143);
2112 ni_writew(devpriv->ai_calib_source,
2113 Calibration_Channel_6143);
2114 devpriv->ai_calib_source_enabled = 0;
2115 msleep_interruptible(100); /* Allow relays to change */
2119 offset = 1 << (board->adbits - 1);
2120 for (i = 0; i < n_chan; i++) {
2121 if ((board->reg_type != ni_reg_6143)
2122 && (list[i] & CR_ALT_SOURCE)) {
2123 chan = devpriv->ai_calib_source;
2125 chan = CR_CHAN(list[i]);
2127 aref = CR_AREF(list[i]);
2128 range = CR_RANGE(list[i]);
2129 dither = ((list[i] & CR_ALT_FILTER) != 0);
2131 /* fix the external/internal range differences */
2132 range = ni_gainlkup[board->gainlkup][range];
2133 if (board->reg_type == ni_reg_611x)
2134 devpriv->ai_offset[i] = offset;
2136 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2139 if ((list[i] & CR_ALT_SOURCE)) {
2140 if (board->reg_type == ni_reg_611x)
2141 ni_writew(CR_CHAN(list[i]) & 0x0003,
2142 Calibration_Channel_Select_611x);
2144 if (board->reg_type == ni_reg_611x)
2146 else if (board->reg_type == ni_reg_6143)
2150 hi |= AI_DIFFERENTIAL;
2162 hi |= AI_CONFIG_CHANNEL(chan);
2164 ni_writew(hi, Configuration_Memory_High);
2166 if (board->reg_type != ni_reg_6143) {
2168 if (i == n_chan - 1)
2169 lo |= AI_LAST_CHANNEL;
2173 ni_writew(lo, Configuration_Memory_Low);
2177 /* prime the channel/gain list */
2178 if ((board->reg_type != ni_reg_611x)
2179 && (board->reg_type != ni_reg_6143)) {
2180 ni_prime_channelgain_list(dev);
2184 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2187 struct ni_private *devpriv = dev->private;
2190 switch (round_mode) {
2191 case TRIG_ROUND_NEAREST:
2193 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2195 case TRIG_ROUND_DOWN:
2196 divider = (nanosec) / devpriv->clock_ns;
2199 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2205 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2207 struct ni_private *devpriv = dev->private;
2209 return devpriv->clock_ns * (timer + 1);
2212 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2213 unsigned num_channels)
2215 const struct ni_board_struct *board = comedi_board(dev);
2217 switch (board->reg_type) {
2220 /* simultaneously-sampled inputs */
2221 return board->ai_speed;
2224 /* multiplexed inputs */
2227 return board->ai_speed * num_channels;
2230 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2231 struct comedi_cmd *cmd)
2233 const struct ni_board_struct *board = comedi_board(dev);
2234 struct ni_private *devpriv = dev->private;
2237 unsigned int sources;
2239 /* Step 1 : check if triggers are trivially valid */
2241 if ((cmd->flags & CMDF_WRITE))
2242 cmd->flags &= ~CMDF_WRITE;
2244 err |= cfc_check_trigger_src(&cmd->start_src,
2245 TRIG_NOW | TRIG_INT | TRIG_EXT);
2246 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2247 TRIG_TIMER | TRIG_EXT);
2249 sources = TRIG_TIMER | TRIG_EXT;
2250 if (board->reg_type == ni_reg_611x ||
2251 board->reg_type == ni_reg_6143)
2252 sources |= TRIG_NOW;
2253 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2255 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2256 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2261 /* Step 2a : make sure trigger sources are unique */
2263 err |= cfc_check_trigger_is_unique(cmd->start_src);
2264 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2265 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2266 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2268 /* Step 2b : and mutually compatible */
2273 /* Step 3: check if arguments are trivially valid */
2275 if (cmd->start_src == TRIG_EXT) {
2276 /* external trigger */
2277 unsigned int tmp = CR_CHAN(cmd->start_arg);
2281 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2282 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2284 /* true for both TRIG_NOW and TRIG_INT */
2285 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2288 if (cmd->scan_begin_src == TRIG_TIMER) {
2289 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2290 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2291 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2292 devpriv->clock_ns * 0xffffff);
2293 } else if (cmd->scan_begin_src == TRIG_EXT) {
2294 /* external trigger */
2295 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2299 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2300 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2301 } else { /* TRIG_OTHER */
2302 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2305 if (cmd->convert_src == TRIG_TIMER) {
2306 if ((board->reg_type == ni_reg_611x)
2307 || (board->reg_type == ni_reg_6143)) {
2308 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2310 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2312 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2313 devpriv->clock_ns * 0xffff);
2315 } else if (cmd->convert_src == TRIG_EXT) {
2316 /* external trigger */
2317 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2321 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2322 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2323 } else if (cmd->convert_src == TRIG_NOW) {
2324 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2327 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2329 if (cmd->stop_src == TRIG_COUNT) {
2330 unsigned int max_count = 0x01000000;
2332 if (board->reg_type == ni_reg_611x)
2333 max_count -= num_adc_stages_611x;
2334 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2335 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2338 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2344 /* step 4: fix up any arguments */
2346 if (cmd->scan_begin_src == TRIG_TIMER) {
2347 tmp = cmd->scan_begin_arg;
2348 cmd->scan_begin_arg =
2349 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2350 cmd->scan_begin_arg,
2354 if (tmp != cmd->scan_begin_arg)
2357 if (cmd->convert_src == TRIG_TIMER) {
2358 if ((board->reg_type != ni_reg_611x)
2359 && (board->reg_type != ni_reg_6143)) {
2360 tmp = cmd->convert_arg;
2362 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2367 if (tmp != cmd->convert_arg)
2369 if (cmd->scan_begin_src == TRIG_TIMER &&
2370 cmd->scan_begin_arg <
2371 cmd->convert_arg * cmd->scan_end_arg) {
2372 cmd->scan_begin_arg =
2373 cmd->convert_arg * cmd->scan_end_arg;
2385 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2387 const struct ni_board_struct *board = comedi_board(dev);
2388 struct ni_private *devpriv = dev->private;
2389 const struct comedi_cmd *cmd = &s->async->cmd;
2391 int mode1 = 0; /* mode1 is needed for both stop and convert */
2393 int start_stop_select = 0;
2394 unsigned int stop_count;
2395 int interrupt_a_enable = 0;
2397 MDPRINTK("ni_ai_cmd\n");
2398 if (dev->irq == 0) {
2399 comedi_error(dev, "cannot run command without an irq");
2402 ni_clear_ai_fifo(dev);
2404 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2406 /* start configuration */
2407 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2409 /* disable analog triggering for now, since it
2410 * interferes with the use of pfi0 */
2411 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2412 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2413 Analog_Trigger_Etc_Register);
2415 switch (cmd->start_src) {
2418 devpriv->stc_writew(dev, AI_START2_Select(0) |
2419 AI_START1_Sync | AI_START1_Edge |
2420 AI_START1_Select(0),
2421 AI_Trigger_Select_Register);
2425 int chan = CR_CHAN(cmd->start_arg);
2426 unsigned int bits = AI_START2_Select(0) |
2427 AI_START1_Sync | AI_START1_Select(chan + 1);
2429 if (cmd->start_arg & CR_INVERT)
2430 bits |= AI_START1_Polarity;
2431 if (cmd->start_arg & CR_EDGE)
2432 bits |= AI_START1_Edge;
2433 devpriv->stc_writew(dev, bits,
2434 AI_Trigger_Select_Register);
2439 mode2 &= ~AI_Pre_Trigger;
2440 mode2 &= ~AI_SC_Initial_Load_Source;
2441 mode2 &= ~AI_SC_Reload_Mode;
2442 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2444 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2445 || (board->reg_type == ni_reg_6143)) {
2446 start_stop_select |= AI_STOP_Polarity;
2447 start_stop_select |= AI_STOP_Select(31); /* logic low */
2448 start_stop_select |= AI_STOP_Sync;
2450 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2452 devpriv->stc_writew(dev, start_stop_select,
2453 AI_START_STOP_Select_Register);
2455 devpriv->ai_cmd2 = 0;
2456 switch (cmd->stop_src) {
2458 stop_count = cmd->stop_arg - 1;
2460 if (board->reg_type == ni_reg_611x) {
2461 /* have to take 3 stage adc pipeline into account */
2462 stop_count += num_adc_stages_611x;
2464 /* stage number of scans */
2465 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2467 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2468 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2469 /* load SC (Scan Count) */
2470 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2472 devpriv->ai_continuous = 0;
2473 if (stop_count == 0) {
2474 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2475 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2476 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2477 if (cmd->chanlist_len > 1)
2478 start_stop_select |=
2479 AI_STOP_Polarity | AI_STOP_Edge;
2483 /* stage number of scans */
2484 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2486 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2487 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2489 /* load SC (Scan Count) */
2490 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2492 devpriv->ai_continuous = 1;
2497 switch (cmd->scan_begin_src) {
2500 stop bits for non 611x boards
2501 AI_SI_Special_Trigger_Delay=0
2503 AI_START_STOP_Select_Register:
2504 AI_START_Polarity=0 (?) rising edge
2505 AI_START_Edge=1 edge triggered
2507 AI_START_Select=0 SI_TC
2508 AI_STOP_Polarity=0 rising edge
2509 AI_STOP_Edge=0 level
2511 AI_STOP_Select=19 external pin (configuration mem)
2513 start_stop_select |= AI_START_Edge | AI_START_Sync;
2514 devpriv->stc_writew(dev, start_stop_select,
2515 AI_START_STOP_Select_Register);
2517 mode2 |= AI_SI_Reload_Mode(0);
2518 /* AI_SI_Initial_Load_Source=A */
2519 mode2 &= ~AI_SI_Initial_Load_Source;
2520 /* mode2 |= AI_SC_Reload_Mode; */
2521 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2524 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2525 TRIG_ROUND_NEAREST);
2526 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2527 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2530 if (cmd->scan_begin_arg & CR_EDGE)
2531 start_stop_select |= AI_START_Edge;
2532 /* AI_START_Polarity==1 is falling edge */
2533 if (cmd->scan_begin_arg & CR_INVERT)
2534 start_stop_select |= AI_START_Polarity;
2535 if (cmd->scan_begin_src != cmd->convert_src ||
2536 (cmd->scan_begin_arg & ~CR_EDGE) !=
2537 (cmd->convert_arg & ~CR_EDGE))
2538 start_stop_select |= AI_START_Sync;
2539 start_stop_select |=
2540 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2541 devpriv->stc_writew(dev, start_stop_select,
2542 AI_START_STOP_Select_Register);
2546 switch (cmd->convert_src) {
2549 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2552 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2553 TRIG_ROUND_NEAREST);
2554 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2555 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2557 /* AI_SI2_Reload_Mode = alternate */
2558 /* AI_SI2_Initial_Load_Source = A */
2559 mode2 &= ~AI_SI2_Initial_Load_Source;
2560 mode2 |= AI_SI2_Reload_Mode;
2561 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2564 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2566 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2567 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2569 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2572 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2573 if ((cmd->convert_arg & CR_INVERT) == 0)
2574 mode1 |= AI_CONVERT_Source_Polarity;
2575 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2577 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2578 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2585 /* interrupt on FIFO, errors, SC_TC */
2586 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2587 AI_SC_TC_Interrupt_Enable;
2590 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2593 if (cmd->flags & TRIG_WAKE_EOS
2594 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2595 /* wake on end-of-scan */
2596 devpriv->aimode = AIMODE_SCAN;
2598 devpriv->aimode = AIMODE_HALF_FULL;
2601 switch (devpriv->aimode) {
2602 case AIMODE_HALF_FULL:
2603 /*generate FIFO interrupts and DMA requests on half-full */
2605 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2606 AI_Mode_3_Register);
2608 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2609 AI_Mode_3_Register);
2613 /*generate FIFO interrupts on non-empty */
2614 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2615 AI_Mode_3_Register);
2619 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2620 AI_Mode_3_Register);
2622 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2623 AI_Mode_3_Register);
2625 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2631 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2633 ni_set_bits(dev, Interrupt_A_Enable_Register,
2634 interrupt_a_enable, 1);
2636 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2637 devpriv->int_a_enable_reg);
2639 /* interrupt on nothing */
2640 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2642 /* XXX start polling if necessary */
2643 MDPRINTK("interrupting on nothing\n");
2646 /* end configuration */
2647 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2649 switch (cmd->scan_begin_src) {
2651 devpriv->stc_writew(dev,
2652 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2653 AI_SC_Arm, AI_Command_1_Register);
2656 /* XXX AI_SI_Arm? */
2657 devpriv->stc_writew(dev,
2658 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2659 AI_SC_Arm, AI_Command_1_Register);
2665 int retval = ni_ai_setup_MITE_dma(dev);
2669 /* mite_dump_regs(devpriv->mite); */
2672 switch (cmd->start_src) {
2674 /* AI_START1_Pulse */
2675 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2676 AI_Command_2_Register);
2677 s->async->inttrig = NULL;
2680 s->async->inttrig = NULL;
2683 s->async->inttrig = &ni_ai_inttrig;
2687 MDPRINTK("exit ni_ai_cmd\n");
2692 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2693 unsigned int trignum)
2695 struct ni_private *devpriv = dev->private;
2700 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2701 AI_Command_2_Register);
2702 s->async->inttrig = NULL;
2707 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2708 struct comedi_subdevice *s,
2709 struct comedi_insn *insn,
2710 unsigned int *data);
2712 static int ni_ai_insn_config(struct comedi_device *dev,
2713 struct comedi_subdevice *s,
2714 struct comedi_insn *insn, unsigned int *data)
2716 const struct ni_board_struct *board = comedi_board(dev);
2717 struct ni_private *devpriv = dev->private;
2723 case INSN_CONFIG_ANALOG_TRIG:
2724 return ni_ai_config_analog_trig(dev, s, insn, data);
2725 case INSN_CONFIG_ALT_SOURCE:
2726 if (board->reg_type & ni_reg_m_series_mask) {
2727 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2728 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2729 MSeries_AI_Bypass_Mode_Mux_Mask |
2730 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2733 devpriv->ai_calib_source = data[1];
2734 } else if (board->reg_type == ni_reg_6143) {
2735 unsigned int calib_source;
2737 calib_source = data[1] & 0xf;
2739 if (calib_source > 0xF)
2742 devpriv->ai_calib_source = calib_source;
2743 ni_writew(calib_source, Calibration_Channel_6143);
2745 unsigned int calib_source;
2746 unsigned int calib_source_adjust;
2748 calib_source = data[1] & 0xf;
2749 calib_source_adjust = (data[1] >> 4) & 0xff;
2751 if (calib_source >= 8)
2753 devpriv->ai_calib_source = calib_source;
2754 if (board->reg_type == ni_reg_611x) {
2755 ni_writeb(calib_source_adjust,
2756 Cal_Gain_Select_611x);
2767 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2768 struct comedi_subdevice *s,
2769 struct comedi_insn *insn,
2772 const struct ni_board_struct *board = comedi_board(dev);
2773 struct ni_private *devpriv = dev->private;
2774 unsigned int a, b, modebits;
2778 * data[2] is analog line
2779 * data[3] is set level
2780 * data[4] is reset level */
2781 if (!board->has_analog_trig)
2783 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2784 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2787 if (data[2] >= board->n_adchan) {
2788 data[2] = board->n_adchan - 1;
2791 if (data[3] > 255) { /* a */
2795 if (data[4] > 255) { /* b */
2806 * high mode 00 00 01 10
2807 * low mode 00 00 10 01
2809 * hysteresis low mode 10 00 00 01
2810 * hysteresis high mode 01 00 00 10
2811 * middle mode 10 01 01 10
2816 modebits = data[1] & 0xff;
2817 if (modebits & 0xf0) {
2818 /* two level mode */
2824 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2826 devpriv->atrig_low = a;
2827 devpriv->atrig_high = b;
2829 case 0x81: /* low hysteresis mode */
2830 devpriv->atrig_mode = 6;
2832 case 0x42: /* high hysteresis mode */
2833 devpriv->atrig_mode = 3;
2835 case 0x96: /* middle window mode */
2836 devpriv->atrig_mode = 2;
2843 /* one level mode */
2849 case 0x06: /* high window mode */
2850 devpriv->atrig_high = a;
2851 devpriv->atrig_mode = 0;
2853 case 0x09: /* low window mode */
2854 devpriv->atrig_low = a;
2855 devpriv->atrig_mode = 1;
2867 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2868 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2869 void *data, unsigned int num_bytes,
2870 unsigned int chan_index)
2872 const struct ni_board_struct *board = comedi_board(dev);
2873 struct comedi_async *async = s->async;
2876 unsigned int offset;
2877 unsigned int length = num_bytes / sizeof(short);
2878 short *array = data;
2880 offset = 1 << (board->aobits - 1);
2881 for (i = 0; i < length; i++) {
2882 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2883 if (board->ao_unipolar == 0 || (range & 1) == 0)
2886 array[i] = cpu_to_le16(array[i]);
2889 chan_index %= async->cmd.chanlist_len;
2893 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2894 struct comedi_subdevice *s,
2895 unsigned int chanspec[],
2896 unsigned int n_chans, int timed)
2898 const struct ni_board_struct *board = comedi_board(dev);
2899 struct ni_private *devpriv = dev->private;
2907 for (i = 0; i < board->n_aochan; ++i) {
2908 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2909 ni_writeb(devpriv->ao_conf[i],
2910 M_Offset_AO_Config_Bank(i));
2911 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2914 for (i = 0; i < n_chans; i++) {
2915 const struct comedi_krange *krange;
2916 chan = CR_CHAN(chanspec[i]);
2917 range = CR_RANGE(chanspec[i]);
2918 krange = s->range_table->range + range;
2921 switch (krange->max - krange->min) {
2923 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2924 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2927 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2928 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2931 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2932 ni_writeb(MSeries_Attenuate_x5_Bit,
2933 M_Offset_AO_Reference_Attenuation(chan));
2936 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2937 ni_writeb(MSeries_Attenuate_x5_Bit,
2938 M_Offset_AO_Reference_Attenuation(chan));
2941 printk("%s: bug! unhandled ao reference voltage\n",
2945 switch (krange->max + krange->min) {
2947 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2950 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2953 printk("%s: bug! unhandled ao offset voltage\n",
2958 conf |= MSeries_AO_Update_Timed_Bit;
2959 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2960 devpriv->ao_conf[chan] = conf;
2961 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2966 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2967 struct comedi_subdevice *s,
2968 unsigned int chanspec[],
2969 unsigned int n_chans)
2971 const struct ni_board_struct *board = comedi_board(dev);
2972 struct ni_private *devpriv = dev->private;
2979 for (i = 0; i < n_chans; i++) {
2980 chan = CR_CHAN(chanspec[i]);
2981 range = CR_RANGE(chanspec[i]);
2982 conf = AO_Channel(chan);
2984 if (board->ao_unipolar) {
2985 if ((range & 1) == 0) {
2987 invert = (1 << (board->aobits - 1));
2995 invert = (1 << (board->aobits - 1));
2998 /* not all boards can deglitch, but this shouldn't hurt */
2999 if (chanspec[i] & CR_DEGLITCH)
3000 conf |= AO_Deglitch;
3002 /* analog reference */
3003 /* AREF_OTHER connects AO ground to AI ground, i think */
3004 conf |= (CR_AREF(chanspec[i]) ==
3005 AREF_OTHER) ? AO_Ground_Ref : 0;
3007 ni_writew(conf, AO_Configuration);
3008 devpriv->ao_conf[chan] = conf;
3013 static int ni_ao_config_chanlist(struct comedi_device *dev,
3014 struct comedi_subdevice *s,
3015 unsigned int chanspec[], unsigned int n_chans,
3018 const struct ni_board_struct *board = comedi_board(dev);
3020 if (board->reg_type & ni_reg_m_series_mask)
3021 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3024 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3027 static int ni_ao_insn_read(struct comedi_device *dev,
3028 struct comedi_subdevice *s, struct comedi_insn *insn,
3031 struct ni_private *devpriv = dev->private;
3033 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3038 static int ni_ao_insn_write(struct comedi_device *dev,
3039 struct comedi_subdevice *s,
3040 struct comedi_insn *insn, unsigned int *data)
3042 const struct ni_board_struct *board = comedi_board(dev);
3043 struct ni_private *devpriv = dev->private;
3044 unsigned int chan = CR_CHAN(insn->chanspec);
3045 unsigned int invert;
3047 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3049 devpriv->ao[chan] = data[0];
3051 if (board->reg_type & ni_reg_m_series_mask) {
3052 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3054 ni_writew(data[0] ^ invert,
3055 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3060 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3061 struct comedi_subdevice *s,
3062 struct comedi_insn *insn, unsigned int *data)
3064 const struct ni_board_struct *board = comedi_board(dev);
3065 struct ni_private *devpriv = dev->private;
3066 unsigned int chan = CR_CHAN(insn->chanspec);
3067 unsigned int invert;
3069 ao_win_out(1 << chan, AO_Immediate_671x);
3070 invert = 1 << (board->aobits - 1);
3072 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3074 devpriv->ao[chan] = data[0];
3075 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3080 static int ni_ao_insn_config(struct comedi_device *dev,
3081 struct comedi_subdevice *s,
3082 struct comedi_insn *insn, unsigned int *data)
3084 const struct ni_board_struct *board = comedi_board(dev);
3085 struct ni_private *devpriv = dev->private;
3088 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3091 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3093 data[2] += devpriv->mite->fifo_size;
3110 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3111 unsigned int trignum)
3113 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3114 struct ni_private *devpriv = dev->private;
3116 int interrupt_b_bits;
3118 static const int timeout = 1000;
3123 /* Null trig at beginning prevent ao start trigger from executing more than
3124 once per command (and doing things like trying to allocate the ao dma channel
3126 s->async->inttrig = NULL;
3128 ni_set_bits(dev, Interrupt_B_Enable_Register,
3129 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3130 interrupt_b_bits = AO_Error_Interrupt_Enable;
3132 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3133 if (board->reg_type & ni_reg_6xxx_mask)
3134 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3135 ret = ni_ao_setup_MITE_dma(dev);
3138 ret = ni_ao_wait_for_dma_load(dev);
3142 ret = ni_ao_prep_fifo(dev, s);
3146 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3149 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3150 AO_Mode_3_Register);
3151 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3152 /* wait for DACs to be loaded */
3153 for (i = 0; i < timeout; i++) {
3155 if ((devpriv->stc_readw(dev,
3156 Joint_Status_2_Register) &
3157 AO_TMRDACWRs_In_Progress_St) == 0)
3162 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3165 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3166 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3167 Interrupt_B_Ack_Register);
3169 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3171 devpriv->stc_writew(dev,
3172 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3173 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3174 AO_Command_1_Register);
3176 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3177 AO_Command_2_Register);
3182 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3184 const struct ni_board_struct *board = comedi_board(dev);
3185 struct ni_private *devpriv = dev->private;
3186 const struct comedi_cmd *cmd = &s->async->cmd;
3191 if (dev->irq == 0) {
3192 comedi_error(dev, "cannot run command without an irq");
3196 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3198 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3200 if (board->reg_type & ni_reg_6xxx_mask) {
3201 ao_win_out(CLEAR_WG, AO_Misc_611x);
3204 for (i = 0; i < cmd->chanlist_len; i++) {
3207 chan = CR_CHAN(cmd->chanlist[i]);
3209 ao_win_out(chan, AO_Waveform_Generation_611x);
3211 ao_win_out(bits, AO_Timed_611x);
3214 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3216 if (cmd->stop_src == TRIG_NONE) {
3217 devpriv->ao_mode1 |= AO_Continuous;
3218 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3220 devpriv->ao_mode1 &= ~AO_Continuous;
3221 devpriv->ao_mode1 |= AO_Trigger_Once;
3223 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3224 switch (cmd->start_src) {
3227 devpriv->ao_trigger_select &=
3228 ~(AO_START1_Polarity | AO_START1_Select(-1));
3229 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3230 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3231 AO_Trigger_Select_Register);
3234 devpriv->ao_trigger_select =
3235 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3236 if (cmd->start_arg & CR_INVERT)
3237 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3238 if (cmd->start_arg & CR_EDGE)
3239 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3240 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3241 AO_Trigger_Select_Register);
3247 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3248 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3250 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3251 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3252 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3253 if (cmd->stop_src == TRIG_NONE) {
3254 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3256 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3258 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3259 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3260 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3261 switch (cmd->stop_src) {
3263 if (board->reg_type & ni_reg_m_series_mask) {
3264 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3265 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3266 AO_UC_Load_A_Register);
3267 devpriv->stc_writew(dev, AO_UC_Load,
3268 AO_Command_1_Register);
3270 devpriv->stc_writel(dev, cmd->stop_arg,
3271 AO_UC_Load_A_Register);
3272 devpriv->stc_writew(dev, AO_UC_Load,
3273 AO_Command_1_Register);
3274 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3275 AO_UC_Load_A_Register);
3279 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3280 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3281 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3284 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3285 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3286 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3289 devpriv->ao_mode1 &=
3290 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3291 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3292 switch (cmd->scan_begin_src) {
3294 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3296 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3297 TRIG_ROUND_NEAREST);
3298 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3299 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3300 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3303 devpriv->ao_mode1 |=
3304 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3305 if (cmd->scan_begin_arg & CR_INVERT)
3306 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3307 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3313 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3314 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3315 devpriv->ao_mode2 &=
3316 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3317 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3319 if (cmd->scan_end_arg > 1) {
3320 devpriv->ao_mode1 |= AO_Multiple_Channels;
3321 devpriv->stc_writew(dev,
3322 AO_Number_Of_Channels(cmd->scan_end_arg -
3324 AO_UPDATE_Output_Select
3325 (AO_Update_Output_High_Z),
3326 AO_Output_Control_Register);
3329 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3330 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3331 if (board->reg_type &
3332 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3333 bits |= AO_Number_Of_Channels(0);
3336 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3338 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3340 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3342 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3343 AO_Command_1_Register);
3345 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3346 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3348 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3350 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3352 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3354 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3355 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3357 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3358 AO_TMRDACWR_Pulse_Width;
3359 if (board->ao_fifo_depth)
3360 bits |= AO_FIFO_Enable;
3362 bits |= AO_DMA_PIO_Control;
3364 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3365 verified with bus analyzer. */
3366 if (board->reg_type & ni_reg_m_series_mask)
3367 bits |= AO_Number_Of_DAC_Packages;
3369 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3370 /* enable sending of ao dma requests */
3371 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3373 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3375 if (cmd->stop_src == TRIG_COUNT) {
3376 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3377 Interrupt_B_Ack_Register);
3378 ni_set_bits(dev, Interrupt_B_Enable_Register,
3379 AO_BC_TC_Interrupt_Enable, 1);
3382 s->async->inttrig = &ni_ao_inttrig;
3387 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3388 struct comedi_cmd *cmd)
3390 const struct ni_board_struct *board = comedi_board(dev);
3391 struct ni_private *devpriv = dev->private;
3395 /* Step 1 : check if triggers are trivially valid */
3397 if ((cmd->flags & CMDF_WRITE) == 0)
3398 cmd->flags |= CMDF_WRITE;
3400 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3401 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3402 TRIG_TIMER | TRIG_EXT);
3403 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3404 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3405 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3410 /* Step 2a : make sure trigger sources are unique */
3412 err |= cfc_check_trigger_is_unique(cmd->start_src);
3413 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3414 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3416 /* Step 2b : and mutually compatible */
3421 /* Step 3: check if arguments are trivially valid */
3423 if (cmd->start_src == TRIG_EXT) {
3424 /* external trigger */
3425 unsigned int tmp = CR_CHAN(cmd->start_arg);
3429 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3430 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3432 /* true for both TRIG_NOW and TRIG_INT */
3433 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3436 if (cmd->scan_begin_src == TRIG_TIMER) {
3437 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3439 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3440 devpriv->clock_ns * 0xffffff);
3443 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3444 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3446 if (cmd->stop_src == TRIG_COUNT)
3447 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3448 else /* TRIG_NONE */
3449 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3454 /* step 4: fix up any arguments */
3455 if (cmd->scan_begin_src == TRIG_TIMER) {
3456 tmp = cmd->scan_begin_arg;
3457 cmd->scan_begin_arg =
3458 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3459 cmd->scan_begin_arg,
3463 if (tmp != cmd->scan_begin_arg)
3469 /* step 5: fix up chanlist */
3477 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3479 const struct ni_board_struct *board = comedi_board(dev);
3480 struct ni_private *devpriv = dev->private;
3482 /* devpriv->ao0p=0x0000; */
3483 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3485 /* devpriv->ao1p=AO_Channel(1); */
3486 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3488 ni_release_ao_mite_channel(dev);
3490 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3491 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3492 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3493 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3494 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3495 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3496 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3497 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3498 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3499 devpriv->ao_cmd1 = 0;
3500 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3501 devpriv->ao_cmd2 = 0;
3502 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3503 devpriv->ao_mode1 = 0;
3504 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3505 devpriv->ao_mode2 = 0;
3506 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3507 if (board->reg_type & ni_reg_m_series_mask)
3508 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3510 devpriv->ao_mode3 = 0;
3511 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3512 devpriv->ao_trigger_select = 0;
3513 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3514 AO_Trigger_Select_Register);
3515 if (board->reg_type & ni_reg_6xxx_mask) {
3516 unsigned immediate_bits = 0;
3518 for (i = 0; i < s->n_chan; ++i) {
3519 immediate_bits |= 1 << i;
3521 ao_win_out(immediate_bits, AO_Immediate_671x);
3522 ao_win_out(CLEAR_WG, AO_Misc_611x);
3524 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3531 static int ni_dio_insn_config(struct comedi_device *dev,
3532 struct comedi_subdevice *s,
3533 struct comedi_insn *insn, unsigned int *data)
3535 struct ni_private *devpriv = dev->private;
3538 printk("ni_dio_insn_config() chan=%d io=%d\n",
3539 CR_CHAN(insn->chanspec), data[0]);
3542 case INSN_CONFIG_DIO_OUTPUT:
3543 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3545 case INSN_CONFIG_DIO_INPUT:
3546 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3548 case INSN_CONFIG_DIO_QUERY:
3551 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3559 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3560 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3561 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3566 static int ni_dio_insn_bits(struct comedi_device *dev,
3567 struct comedi_subdevice *s,
3568 struct comedi_insn *insn, unsigned int *data)
3570 struct ni_private *devpriv = dev->private;
3573 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3577 /* Perform check to make sure we're not using the
3578 serial part of the dio */
3579 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3580 && devpriv->serial_interval_ns)
3583 s->state &= ~data[0];
3584 s->state |= (data[0] & data[1]);
3585 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3586 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3587 devpriv->stc_writew(dev, devpriv->dio_output,
3588 DIO_Output_Register);
3590 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3595 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3596 struct comedi_subdevice *s,
3597 struct comedi_insn *insn,
3600 struct ni_private *devpriv __maybe_unused = dev->private;
3603 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3604 CR_CHAN(insn->chanspec), data[0]);
3607 case INSN_CONFIG_DIO_OUTPUT:
3608 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3610 case INSN_CONFIG_DIO_INPUT:
3611 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3613 case INSN_CONFIG_DIO_QUERY:
3616 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3624 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3629 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3630 struct comedi_subdevice *s,
3631 struct comedi_insn *insn,
3634 struct ni_private *devpriv __maybe_unused = dev->private;
3637 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3642 s->state &= ~data[0];
3643 s->state |= (data[0] & data[1]);
3644 ni_writel(s->state, M_Offset_Static_Digital_Output);
3646 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3651 static int ni_cdio_cmdtest(struct comedi_device *dev,
3652 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3658 /* Step 1 : check if triggers are trivially valid */
3660 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3661 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3662 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3663 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3664 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3669 /* Step 2a : make sure trigger sources are unique */
3670 /* Step 2b : and mutually compatible */
3675 /* Step 3: check if arguments are trivially valid */
3677 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3679 tmp = cmd->scan_begin_arg;
3680 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3681 if (tmp != cmd->scan_begin_arg)
3684 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3685 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3686 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3691 /* step 4: fix up any arguments */
3696 /* step 5: check chanlist */
3698 for (i = 0; i < cmd->chanlist_len; ++i) {
3699 if (cmd->chanlist[i] != i)
3709 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3711 struct ni_private *devpriv __maybe_unused = dev->private;
3712 const struct comedi_cmd *cmd = &s->async->cmd;
3713 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3716 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3717 switch (cmd->scan_begin_src) {
3720 CR_CHAN(cmd->scan_begin_arg) &
3721 CDO_Sample_Source_Select_Mask;
3727 if (cmd->scan_begin_arg & CR_INVERT)
3728 cdo_mode_bits |= CDO_Polarity_Bit;
3729 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3731 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3732 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3733 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3736 "attempted to run digital output command with no lines configured as outputs");
3739 retval = ni_request_cdo_mite_channel(dev);
3743 s->async->inttrig = &ni_cdo_inttrig;
3747 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3748 unsigned int trignum)
3751 struct ni_private *devpriv = dev->private;
3752 unsigned long flags;
3756 const unsigned timeout = 1000;
3758 s->async->inttrig = NULL;
3760 /* read alloc the entire buffer */
3761 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3764 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3765 if (devpriv->cdo_mite_chan) {
3766 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3767 mite_dma_arm(devpriv->cdo_mite_chan);
3769 comedi_error(dev, "BUG: no cdo mite channel?");
3772 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3777 * XXX not sure what interrupt C group does
3778 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3779 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3781 for (i = 0; i < timeout; ++i) {
3782 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3787 comedi_error(dev, "dma failed to fill cdo fifo!");
3788 ni_cdio_cancel(dev, s);
3791 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3792 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3793 M_Offset_CDIO_Command);
3797 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3799 struct ni_private *devpriv __maybe_unused = dev->private;
3801 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3802 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3803 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3804 M_Offset_CDIO_Command);
3806 * XXX not sure what interrupt C group does ni_writeb(0,
3807 * M_Offset_Interrupt_C_Enable);
3809 ni_writel(0, M_Offset_CDO_Mask_Enable);
3810 ni_release_cdo_mite_channel(dev);
3814 static void handle_cdio_interrupt(struct comedi_device *dev)
3816 const struct ni_board_struct *board = comedi_board(dev);
3817 struct ni_private *devpriv __maybe_unused = dev->private;
3818 unsigned cdio_status;
3819 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3821 unsigned long flags;
3824 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3828 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3829 if (devpriv->cdo_mite_chan) {
3830 unsigned cdo_mite_status =
3831 mite_get_status(devpriv->cdo_mite_chan);
3832 if (cdo_mite_status & CHSR_LINKC) {
3834 devpriv->mite->mite_io_addr +
3835 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3837 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3839 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3842 cdio_status = ni_readl(M_Offset_CDIO_Status);
3843 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3844 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3845 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3846 s->async->events |= COMEDI_CB_OVERFLOW;
3848 if (cdio_status & CDO_FIFO_Empty_Bit) {
3849 /* printk("cdio fifo empty\n"); */
3850 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3851 M_Offset_CDIO_Command);
3852 /* s->async->events |= COMEDI_CB_EOA; */
3857 static int ni_serial_insn_config(struct comedi_device *dev,
3858 struct comedi_subdevice *s,
3859 struct comedi_insn *insn, unsigned int *data)
3861 struct ni_private *devpriv = dev->private;
3863 unsigned char byte_out, byte_in = 0;
3869 case INSN_CONFIG_SERIAL_CLOCK:
3872 printk("SPI serial clock Config cd\n", data[1]);
3874 devpriv->serial_hw_mode = 1;
3875 devpriv->dio_control |= DIO_HW_Serial_Enable;
3877 if (data[1] == SERIAL_DISABLED) {
3878 devpriv->serial_hw_mode = 0;
3879 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3880 DIO_Software_Serial_Control);
3881 data[1] = SERIAL_DISABLED;
3882 devpriv->serial_interval_ns = data[1];
3883 } else if (data[1] <= SERIAL_600NS) {
3884 /* Warning: this clock speed is too fast to reliably
3886 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3887 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3888 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3889 data[1] = SERIAL_600NS;
3890 devpriv->serial_interval_ns = data[1];
3891 } else if (data[1] <= SERIAL_1_2US) {
3892 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3893 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3894 DIO_Serial_Out_Divide_By_2;
3895 data[1] = SERIAL_1_2US;
3896 devpriv->serial_interval_ns = data[1];
3897 } else if (data[1] <= SERIAL_10US) {
3898 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3899 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3900 DIO_Serial_Out_Divide_By_2;
3901 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3902 600ns/1.2us. If you turn divide_by_2 off with the
3903 slow clock, you will still get 10us, except then
3904 all your delays are wrong. */
3905 data[1] = SERIAL_10US;
3906 devpriv->serial_interval_ns = data[1];
3908 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3909 DIO_Software_Serial_Control);
3910 devpriv->serial_hw_mode = 0;
3911 data[1] = (data[1] / 1000) * 1000;
3912 devpriv->serial_interval_ns = data[1];
3915 devpriv->stc_writew(dev, devpriv->dio_control,
3916 DIO_Control_Register);
3917 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3918 Clock_and_FOUT_Register);
3923 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3925 if (devpriv->serial_interval_ns == 0) {
3929 byte_out = data[1] & 0xFF;
3931 if (devpriv->serial_hw_mode) {
3932 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3934 } else if (devpriv->serial_interval_ns > 0) {
3935 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3938 printk("ni_serial_insn_config: serial disabled!\n");
3943 data[1] = byte_in & 0xFF;
3953 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3954 struct comedi_subdevice *s,
3955 unsigned char data_out,
3956 unsigned char *data_in)
3958 struct ni_private *devpriv = dev->private;
3959 unsigned int status1;
3960 int err = 0, count = 20;
3963 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3966 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3967 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3968 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3970 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3971 if (status1 & DIO_Serial_IO_In_Progress_St) {
3976 devpriv->dio_control |= DIO_HW_Serial_Start;
3977 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3978 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3980 /* Wait until STC says we're done, but don't loop infinitely. */
3982 devpriv->stc_readw(dev,
3983 Joint_Status_1_Register)) &
3984 DIO_Serial_IO_In_Progress_St) {
3985 /* Delay one bit per loop */
3986 udelay((devpriv->serial_interval_ns + 999) / 1000);
3989 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3995 /* Delay for last bit. This delay is absolutely necessary, because
3996 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3997 udelay((devpriv->serial_interval_ns + 999) / 1000);
3999 if (data_in != NULL) {
4000 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4002 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4007 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4012 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4013 struct comedi_subdevice *s,
4014 unsigned char data_out,
4015 unsigned char *data_in)
4017 struct ni_private *devpriv = dev->private;
4018 unsigned char mask, input = 0;
4021 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4024 /* Wait for one bit before transfer */
4025 udelay((devpriv->serial_interval_ns + 999) / 1000);
4027 for (mask = 0x80; mask; mask >>= 1) {
4028 /* Output current bit; note that we cannot touch s->state
4029 because it is a per-subdevice field, and serial is
4030 a separate subdevice from DIO. */
4031 devpriv->dio_output &= ~DIO_SDOUT;
4032 if (data_out & mask) {
4033 devpriv->dio_output |= DIO_SDOUT;
4035 devpriv->stc_writew(dev, devpriv->dio_output,
4036 DIO_Output_Register);
4038 /* Assert SDCLK (active low, inverted), wait for half of
4039 the delay, deassert SDCLK, and wait for the other half. */
4040 devpriv->dio_control |= DIO_Software_Serial_Control;
4041 devpriv->stc_writew(dev, devpriv->dio_control,
4042 DIO_Control_Register);
4044 udelay((devpriv->serial_interval_ns + 999) / 2000);
4046 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4047 devpriv->stc_writew(dev, devpriv->dio_control,
4048 DIO_Control_Register);
4050 udelay((devpriv->serial_interval_ns + 999) / 2000);
4052 /* Input current bit */
4053 if (devpriv->stc_readw(dev,
4054 DIO_Parallel_Input_Register) & DIO_SDIN)
4056 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4061 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4069 static void mio_common_detach(struct comedi_device *dev)
4071 struct ni_private *devpriv = dev->private;
4074 if (devpriv->counter_dev) {
4075 ni_gpct_device_destroy(devpriv->counter_dev);
4078 comedi_spriv_free(dev, NI_8255_DIO_SUBDEV);
4081 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4085 for (i = 0; i < s->n_chan; i++) {
4086 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4087 AO_Configuration_2_67xx);
4089 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4092 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4094 unsigned stc_register;
4096 case NITIO_G0_Autoincrement_Reg:
4097 stc_register = G_Autoincrement_Register(0);
4099 case NITIO_G1_Autoincrement_Reg:
4100 stc_register = G_Autoincrement_Register(1);
4102 case NITIO_G0_Command_Reg:
4103 stc_register = G_Command_Register(0);
4105 case NITIO_G1_Command_Reg:
4106 stc_register = G_Command_Register(1);
4108 case NITIO_G0_HW_Save_Reg:
4109 stc_register = G_HW_Save_Register(0);
4111 case NITIO_G1_HW_Save_Reg:
4112 stc_register = G_HW_Save_Register(1);
4114 case NITIO_G0_SW_Save_Reg:
4115 stc_register = G_Save_Register(0);
4117 case NITIO_G1_SW_Save_Reg:
4118 stc_register = G_Save_Register(1);
4120 case NITIO_G0_Mode_Reg:
4121 stc_register = G_Mode_Register(0);
4123 case NITIO_G1_Mode_Reg:
4124 stc_register = G_Mode_Register(1);
4126 case NITIO_G0_LoadA_Reg:
4127 stc_register = G_Load_A_Register(0);
4129 case NITIO_G1_LoadA_Reg:
4130 stc_register = G_Load_A_Register(1);
4132 case NITIO_G0_LoadB_Reg:
4133 stc_register = G_Load_B_Register(0);
4135 case NITIO_G1_LoadB_Reg:
4136 stc_register = G_Load_B_Register(1);
4138 case NITIO_G0_Input_Select_Reg:
4139 stc_register = G_Input_Select_Register(0);
4141 case NITIO_G1_Input_Select_Reg:
4142 stc_register = G_Input_Select_Register(1);
4144 case NITIO_G01_Status_Reg:
4145 stc_register = G_Status_Register;
4147 case NITIO_G01_Joint_Reset_Reg:
4148 stc_register = Joint_Reset_Register;
4150 case NITIO_G01_Joint_Status1_Reg:
4151 stc_register = Joint_Status_1_Register;
4153 case NITIO_G01_Joint_Status2_Reg:
4154 stc_register = Joint_Status_2_Register;
4156 case NITIO_G0_Interrupt_Acknowledge_Reg:
4157 stc_register = Interrupt_A_Ack_Register;
4159 case NITIO_G1_Interrupt_Acknowledge_Reg:
4160 stc_register = Interrupt_B_Ack_Register;
4162 case NITIO_G0_Status_Reg:
4163 stc_register = AI_Status_1_Register;
4165 case NITIO_G1_Status_Reg:
4166 stc_register = AO_Status_1_Register;
4168 case NITIO_G0_Interrupt_Enable_Reg:
4169 stc_register = Interrupt_A_Enable_Register;
4171 case NITIO_G1_Interrupt_Enable_Reg:
4172 stc_register = Interrupt_B_Enable_Register;
4175 printk("%s: unhandled register 0x%x in switch.\n",
4181 return stc_register;
4184 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4185 enum ni_gpct_register reg)
4187 struct comedi_device *dev = counter->counter_dev->dev;
4188 struct ni_private *devpriv = dev->private;
4189 unsigned stc_register;
4190 /* bits in the join reset register which are relevant to counters */
4191 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4192 static const unsigned gpct_interrupt_a_enable_mask =
4193 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4194 static const unsigned gpct_interrupt_b_enable_mask =
4195 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4198 /* m-series-only registers */
4199 case NITIO_G0_Counting_Mode_Reg:
4200 ni_writew(bits, M_Offset_G0_Counting_Mode);
4202 case NITIO_G1_Counting_Mode_Reg:
4203 ni_writew(bits, M_Offset_G1_Counting_Mode);
4205 case NITIO_G0_Second_Gate_Reg:
4206 ni_writew(bits, M_Offset_G0_Second_Gate);
4208 case NITIO_G1_Second_Gate_Reg:
4209 ni_writew(bits, M_Offset_G1_Second_Gate);
4211 case NITIO_G0_DMA_Config_Reg:
4212 ni_writew(bits, M_Offset_G0_DMA_Config);
4214 case NITIO_G1_DMA_Config_Reg:
4215 ni_writew(bits, M_Offset_G1_DMA_Config);
4217 case NITIO_G0_ABZ_Reg:
4218 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4220 case NITIO_G1_ABZ_Reg:
4221 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4224 /* 32 bit registers */
4225 case NITIO_G0_LoadA_Reg:
4226 case NITIO_G1_LoadA_Reg:
4227 case NITIO_G0_LoadB_Reg:
4228 case NITIO_G1_LoadB_Reg:
4229 stc_register = ni_gpct_to_stc_register(reg);
4230 devpriv->stc_writel(dev, bits, stc_register);
4233 /* 16 bit registers */
4234 case NITIO_G0_Interrupt_Enable_Reg:
4235 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4236 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4237 gpct_interrupt_a_enable_mask, bits);
4239 case NITIO_G1_Interrupt_Enable_Reg:
4240 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4241 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4242 gpct_interrupt_b_enable_mask, bits);
4244 case NITIO_G01_Joint_Reset_Reg:
4245 BUG_ON(bits & ~gpct_joint_reset_mask);
4248 stc_register = ni_gpct_to_stc_register(reg);
4249 devpriv->stc_writew(dev, bits, stc_register);
4253 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4254 enum ni_gpct_register reg)
4256 struct comedi_device *dev = counter->counter_dev->dev;
4257 struct ni_private *devpriv = dev->private;
4258 unsigned stc_register;
4261 /* m-series only registers */
4262 case NITIO_G0_DMA_Status_Reg:
4263 return ni_readw(M_Offset_G0_DMA_Status);
4265 case NITIO_G1_DMA_Status_Reg:
4266 return ni_readw(M_Offset_G1_DMA_Status);
4269 /* 32 bit registers */
4270 case NITIO_G0_HW_Save_Reg:
4271 case NITIO_G1_HW_Save_Reg:
4272 case NITIO_G0_SW_Save_Reg:
4273 case NITIO_G1_SW_Save_Reg:
4274 stc_register = ni_gpct_to_stc_register(reg);
4275 return devpriv->stc_readl(dev, stc_register);
4278 /* 16 bit registers */
4280 stc_register = ni_gpct_to_stc_register(reg);
4281 return devpriv->stc_readw(dev, stc_register);
4287 static int ni_freq_out_insn_read(struct comedi_device *dev,
4288 struct comedi_subdevice *s,
4289 struct comedi_insn *insn, unsigned int *data)
4291 struct ni_private *devpriv = dev->private;
4293 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4297 static int ni_freq_out_insn_write(struct comedi_device *dev,
4298 struct comedi_subdevice *s,
4299 struct comedi_insn *insn, unsigned int *data)
4301 struct ni_private *devpriv = dev->private;
4303 devpriv->clock_and_fout &= ~FOUT_Enable;
4304 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4305 Clock_and_FOUT_Register);
4306 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4307 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4308 devpriv->clock_and_fout |= FOUT_Enable;
4309 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4310 Clock_and_FOUT_Register);
4314 static int ni_set_freq_out_clock(struct comedi_device *dev,
4315 unsigned int clock_source)
4317 struct ni_private *devpriv = dev->private;
4319 switch (clock_source) {
4320 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4321 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4323 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4324 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4329 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4330 Clock_and_FOUT_Register);
4334 static void ni_get_freq_out_clock(struct comedi_device *dev,
4335 unsigned int *clock_source,
4336 unsigned int *clock_period_ns)
4338 struct ni_private *devpriv = dev->private;
4340 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4341 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4342 *clock_period_ns = TIMEBASE_2_NS;
4344 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4345 *clock_period_ns = TIMEBASE_1_NS * 2;
4349 static int ni_freq_out_insn_config(struct comedi_device *dev,
4350 struct comedi_subdevice *s,
4351 struct comedi_insn *insn, unsigned int *data)
4354 case INSN_CONFIG_SET_CLOCK_SRC:
4355 return ni_set_freq_out_clock(dev, data[1]);
4357 case INSN_CONFIG_GET_CLOCK_SRC:
4358 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4366 static int ni_alloc_private(struct comedi_device *dev)
4368 struct ni_private *devpriv;
4370 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4373 dev->private = devpriv;
4375 spin_lock_init(&devpriv->window_lock);
4376 spin_lock_init(&devpriv->soft_reg_copy_lock);
4377 spin_lock_init(&devpriv->mite_channel_lock);
4382 static int ni_E_init(struct comedi_device *dev)
4384 const struct ni_board_struct *board = comedi_board(dev);
4385 struct ni_private *devpriv = dev->private;
4386 struct comedi_subdevice *s;
4388 enum ni_gpct_variant counter_variant;
4391 if (board->n_aochan > MAX_N_AO_CHAN) {
4392 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4396 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4400 /* analog input subdevice */
4402 s = &dev->subdevices[NI_AI_SUBDEV];
4403 dev->read_subdev = s;
4404 if (board->n_adchan) {
4405 s->type = COMEDI_SUBD_AI;
4407 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4408 if (board->reg_type != ni_reg_611x)
4409 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4410 if (board->adbits > 16)
4411 s->subdev_flags |= SDF_LSAMPL;
4412 if (board->reg_type & ni_reg_m_series_mask)
4413 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4414 s->n_chan = board->n_adchan;
4415 s->len_chanlist = 512;
4416 s->maxdata = (1 << board->adbits) - 1;
4417 s->range_table = ni_range_lkup[board->gainlkup];
4418 s->insn_read = &ni_ai_insn_read;
4419 s->insn_config = &ni_ai_insn_config;
4420 s->do_cmdtest = &ni_ai_cmdtest;
4421 s->do_cmd = &ni_ai_cmd;
4422 s->cancel = &ni_ai_reset;
4423 s->poll = &ni_ai_poll;
4424 s->munge = &ni_ai_munge;
4426 s->async_dma_dir = DMA_FROM_DEVICE;
4429 s->type = COMEDI_SUBD_UNUSED;
4432 /* analog output subdevice */
4434 s = &dev->subdevices[NI_AO_SUBDEV];
4435 if (board->n_aochan) {
4436 s->type = COMEDI_SUBD_AO;
4437 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4438 if (board->reg_type & ni_reg_m_series_mask)
4439 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4440 s->n_chan = board->n_aochan;
4441 s->maxdata = (1 << board->aobits) - 1;
4442 s->range_table = board->ao_range_table;
4443 s->insn_read = &ni_ao_insn_read;
4444 if (board->reg_type & ni_reg_6xxx_mask) {
4445 s->insn_write = &ni_ao_insn_write_671x;
4447 s->insn_write = &ni_ao_insn_write;
4449 s->insn_config = &ni_ao_insn_config;
4451 if (board->n_aochan) {
4452 s->async_dma_dir = DMA_TO_DEVICE;
4454 if (board->ao_fifo_depth) {
4456 dev->write_subdev = s;
4457 s->subdev_flags |= SDF_CMD_WRITE;
4458 s->do_cmd = &ni_ao_cmd;
4459 s->do_cmdtest = &ni_ao_cmdtest;
4460 s->len_chanlist = board->n_aochan;
4461 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4462 s->munge = ni_ao_munge;
4464 s->cancel = &ni_ao_reset;
4466 s->type = COMEDI_SUBD_UNUSED;
4468 if ((board->reg_type & ni_reg_67xx_mask))
4469 init_ao_67xx(dev, s);
4471 /* digital i/o subdevice */
4473 s = &dev->subdevices[NI_DIO_SUBDEV];
4474 s->type = COMEDI_SUBD_DIO;
4475 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4477 s->io_bits = 0; /* all bits input */
4478 s->range_table = &range_digital;
4479 s->n_chan = board->num_p0_dio_channels;
4480 if (board->reg_type & ni_reg_m_series_mask) {
4482 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4483 s->insn_bits = &ni_m_series_dio_insn_bits;
4484 s->insn_config = &ni_m_series_dio_insn_config;
4485 s->do_cmd = &ni_cdio_cmd;
4486 s->do_cmdtest = &ni_cdio_cmdtest;
4487 s->cancel = &ni_cdio_cancel;
4488 s->async_dma_dir = DMA_BIDIRECTIONAL;
4489 s->len_chanlist = s->n_chan;
4491 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4492 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4494 s->insn_bits = &ni_dio_insn_bits;
4495 s->insn_config = &ni_dio_insn_config;
4496 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4497 ni_writew(devpriv->dio_control, DIO_Control_Register);
4501 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4502 if (board->has_8255) {
4503 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4505 s->type = COMEDI_SUBD_UNUSED;
4508 /* formerly general purpose counter/timer device, but no longer used */
4509 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4510 s->type = COMEDI_SUBD_UNUSED;
4512 /* calibration subdevice -- ai and ao */
4513 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4514 s->type = COMEDI_SUBD_CALIB;
4515 if (board->reg_type & ni_reg_m_series_mask) {
4516 /* internal PWM analog output used for AI nonlinearity calibration */
4517 s->subdev_flags = SDF_INTERNAL;
4518 s->insn_config = &ni_m_series_pwm_config;
4521 ni_writel(0x0, M_Offset_Cal_PWM);
4522 } else if (board->reg_type == ni_reg_6143) {
4523 /* internal PWM analog output used for AI nonlinearity calibration */
4524 s->subdev_flags = SDF_INTERNAL;
4525 s->insn_config = &ni_6143_pwm_config;
4529 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4530 s->insn_read = &ni_calib_insn_read;
4531 s->insn_write = &ni_calib_insn_write;
4532 caldac_setup(dev, s);
4536 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4537 s->type = COMEDI_SUBD_MEMORY;
4538 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4540 if (board->reg_type & ni_reg_m_series_mask) {
4541 s->n_chan = M_SERIES_EEPROM_SIZE;
4542 s->insn_read = &ni_m_series_eeprom_insn_read;
4545 s->insn_read = &ni_eeprom_insn_read;
4549 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4550 s->type = COMEDI_SUBD_DIO;
4551 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4552 if (board->reg_type & ni_reg_m_series_mask) {
4555 ni_writew(s->state, M_Offset_PFI_DO);
4556 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4557 ni_writew(devpriv->pfi_output_select_reg[i],
4558 M_Offset_PFI_Output_Select(i + 1));
4564 if (board->reg_type & ni_reg_m_series_mask) {
4565 s->insn_bits = &ni_pfi_insn_bits;
4567 s->insn_config = &ni_pfi_insn_config;
4568 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4570 /* cs5529 calibration adc */
4571 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4572 if (board->reg_type & ni_reg_67xx_mask) {
4573 s->type = COMEDI_SUBD_AI;
4574 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4575 /* one channel for each analog output channel */
4576 s->n_chan = board->n_aochan;
4577 s->maxdata = (1 << 16) - 1;
4578 s->range_table = &range_unknown; /* XXX */
4579 s->insn_read = cs5529_ai_insn_read;
4580 s->insn_config = NULL;
4583 s->type = COMEDI_SUBD_UNUSED;
4587 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4588 s->type = COMEDI_SUBD_SERIAL;
4589 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4592 s->insn_config = ni_serial_insn_config;
4593 devpriv->serial_interval_ns = 0;
4594 devpriv->serial_hw_mode = 0;
4597 s = &dev->subdevices[NI_RTSI_SUBDEV];
4598 s->type = COMEDI_SUBD_DIO;
4599 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4602 s->insn_bits = ni_rtsi_insn_bits;
4603 s->insn_config = ni_rtsi_insn_config;
4606 if (board->reg_type & ni_reg_m_series_mask) {
4607 counter_variant = ni_gpct_variant_m_series;
4609 counter_variant = ni_gpct_variant_e_series;
4611 devpriv->counter_dev = ni_gpct_device_construct(dev,
4612 &ni_gpct_write_register,
4613 &ni_gpct_read_register,
4616 /* General purpose counters */
4617 for (j = 0; j < NUM_GPCT; ++j) {
4618 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4619 s->type = COMEDI_SUBD_COUNTER;
4621 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4622 /* | SDF_CMD_WRITE */ ;
4624 if (board->reg_type & ni_reg_m_series_mask)
4625 s->maxdata = 0xffffffff;
4627 s->maxdata = 0xffffff;
4628 s->insn_read = &ni_gpct_insn_read;
4629 s->insn_write = &ni_gpct_insn_write;
4630 s->insn_config = &ni_gpct_insn_config;
4631 s->do_cmd = &ni_gpct_cmd;
4632 s->len_chanlist = 1;
4633 s->do_cmdtest = &ni_gpct_cmdtest;
4634 s->cancel = &ni_gpct_cancel;
4635 s->async_dma_dir = DMA_BIDIRECTIONAL;
4636 s->private = &devpriv->counter_dev->counters[j];
4638 devpriv->counter_dev->counters[j].chip_index = 0;
4639 devpriv->counter_dev->counters[j].counter_index = j;
4640 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4643 /* Frequency output */
4644 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4645 s->type = COMEDI_SUBD_COUNTER;
4646 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4649 s->insn_read = &ni_freq_out_insn_read;
4650 s->insn_write = &ni_freq_out_insn_write;
4651 s->insn_config = &ni_freq_out_insn_config;
4653 /* ai configuration */
4654 s = &dev->subdevices[NI_AI_SUBDEV];
4655 ni_ai_reset(dev, s);
4656 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4657 /* BEAM is this needed for PCI-6143 ?? */
4658 devpriv->clock_and_fout =
4659 Slow_Internal_Time_Divide_By_2 |
4660 Slow_Internal_Timebase |
4661 Clock_To_Board_Divide_By_2 |
4663 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4665 devpriv->clock_and_fout =
4666 Slow_Internal_Time_Divide_By_2 |
4667 Slow_Internal_Timebase |
4668 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4670 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4671 Clock_and_FOUT_Register);
4673 /* analog output configuration */
4674 s = &dev->subdevices[NI_AO_SUBDEV];
4675 ni_ao_reset(dev, s);
4678 devpriv->stc_writew(dev,
4679 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4680 0) | (Interrupt_Output_On_3_Pins & 0) |
4681 Interrupt_A_Enable | Interrupt_B_Enable |
4682 Interrupt_A_Output_Select(interrupt_pin
4684 Interrupt_B_Output_Select(interrupt_pin
4686 Interrupt_Control_Register);
4690 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4691 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4693 if (board->reg_type & ni_reg_6xxx_mask) {
4694 ni_writeb(0, Magic_611x);
4695 } else if (board->reg_type & ni_reg_m_series_mask) {
4697 for (channel = 0; channel < board->n_aochan; ++channel) {
4698 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4700 M_Offset_AO_Reference_Attenuation(channel));
4702 ni_writeb(0x0, M_Offset_AO_Calibration);
4709 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4711 struct comedi_device *dev = (struct comedi_device *)arg;
4712 struct ni_private *devpriv __maybe_unused = dev->private;
4715 ni_writeb(data, Port_A + 2 * port);
4718 return ni_readb(Port_A + 2 * port);
4723 presents the EEPROM as a subdevice
4726 static int ni_eeprom_insn_read(struct comedi_device *dev,
4727 struct comedi_subdevice *s,
4728 struct comedi_insn *insn, unsigned int *data)
4730 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4736 reads bytes out of eeprom
4739 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4741 struct ni_private *devpriv __maybe_unused = dev->private;
4745 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4746 ni_writeb(0x04, Serial_Command);
4747 for (bit = 0x8000; bit; bit >>= 1) {
4748 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4750 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4754 for (bit = 0x80; bit; bit >>= 1) {
4755 ni_writeb(0x04, Serial_Command);
4756 ni_writeb(0x05, Serial_Command);
4757 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4759 ni_writeb(0x00, Serial_Command);
4764 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4765 struct comedi_subdevice *s,
4766 struct comedi_insn *insn,
4769 struct ni_private *devpriv = dev->private;
4771 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4776 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4778 struct ni_private *devpriv = dev->private;
4780 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4781 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4785 static int ni_m_series_pwm_config(struct comedi_device *dev,
4786 struct comedi_subdevice *s,
4787 struct comedi_insn *insn, unsigned int *data)
4789 struct ni_private *devpriv = dev->private;
4790 unsigned up_count, down_count;
4793 case INSN_CONFIG_PWM_OUTPUT:
4795 case TRIG_ROUND_NEAREST:
4798 devpriv->clock_ns / 2) / devpriv->clock_ns;
4800 case TRIG_ROUND_DOWN:
4801 up_count = data[2] / devpriv->clock_ns;
4805 (data[2] + devpriv->clock_ns -
4806 1) / devpriv->clock_ns;
4813 case TRIG_ROUND_NEAREST:
4816 devpriv->clock_ns / 2) / devpriv->clock_ns;
4818 case TRIG_ROUND_DOWN:
4819 down_count = data[4] / devpriv->clock_ns;
4823 (data[4] + devpriv->clock_ns -
4824 1) / devpriv->clock_ns;
4830 if (up_count * devpriv->clock_ns != data[2] ||
4831 down_count * devpriv->clock_ns != data[4]) {
4832 data[2] = up_count * devpriv->clock_ns;
4833 data[4] = down_count * devpriv->clock_ns;
4836 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4837 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4839 devpriv->pwm_up_count = up_count;
4840 devpriv->pwm_down_count = down_count;
4843 case INSN_CONFIG_GET_PWM_OUTPUT:
4844 return ni_get_pwm_config(dev, data);
4853 static int ni_6143_pwm_config(struct comedi_device *dev,
4854 struct comedi_subdevice *s,
4855 struct comedi_insn *insn, unsigned int *data)
4857 struct ni_private *devpriv = dev->private;
4858 unsigned up_count, down_count;
4861 case INSN_CONFIG_PWM_OUTPUT:
4863 case TRIG_ROUND_NEAREST:
4866 devpriv->clock_ns / 2) / devpriv->clock_ns;
4868 case TRIG_ROUND_DOWN:
4869 up_count = data[2] / devpriv->clock_ns;
4873 (data[2] + devpriv->clock_ns -
4874 1) / devpriv->clock_ns;
4881 case TRIG_ROUND_NEAREST:
4884 devpriv->clock_ns / 2) / devpriv->clock_ns;
4886 case TRIG_ROUND_DOWN:
4887 down_count = data[4] / devpriv->clock_ns;
4891 (data[4] + devpriv->clock_ns -
4892 1) / devpriv->clock_ns;
4898 if (up_count * devpriv->clock_ns != data[2] ||
4899 down_count * devpriv->clock_ns != data[4]) {
4900 data[2] = up_count * devpriv->clock_ns;
4901 data[4] = down_count * devpriv->clock_ns;
4904 ni_writel(up_count, Calibration_HighTime_6143);
4905 devpriv->pwm_up_count = up_count;
4906 ni_writel(down_count, Calibration_LowTime_6143);
4907 devpriv->pwm_down_count = down_count;
4910 case INSN_CONFIG_GET_PWM_OUTPUT:
4911 return ni_get_pwm_config(dev, data);
4919 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4921 calibration subdevice
4923 static int ni_calib_insn_write(struct comedi_device *dev,
4924 struct comedi_subdevice *s,
4925 struct comedi_insn *insn, unsigned int *data)
4927 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4932 static int ni_calib_insn_read(struct comedi_device *dev,
4933 struct comedi_subdevice *s,
4934 struct comedi_insn *insn, unsigned int *data)
4936 struct ni_private *devpriv = dev->private;
4938 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4943 static int pack_mb88341(int addr, int val, int *bitstring);
4944 static int pack_dac8800(int addr, int val, int *bitstring);
4945 static int pack_dac8043(int addr, int val, int *bitstring);
4946 static int pack_ad8522(int addr, int val, int *bitstring);
4947 static int pack_ad8804(int addr, int val, int *bitstring);
4948 static int pack_ad8842(int addr, int val, int *bitstring);
4950 struct caldac_struct {
4953 int (*packbits) (int, int, int *);
4956 static struct caldac_struct caldacs[] = {
4957 [mb88341] = {12, 8, pack_mb88341},
4958 [dac8800] = {8, 8, pack_dac8800},
4959 [dac8043] = {1, 12, pack_dac8043},
4960 [ad8522] = {2, 12, pack_ad8522},
4961 [ad8804] = {12, 8, pack_ad8804},
4962 [ad8842] = {8, 8, pack_ad8842},
4963 [ad8804_debug] = {16, 8, pack_ad8804},
4966 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4968 const struct ni_board_struct *board = comedi_board(dev);
4969 struct ni_private *devpriv = dev->private;
4978 type = board->caldac[0];
4979 if (type == caldac_none)
4981 n_bits = caldacs[type].n_bits;
4982 for (i = 0; i < 3; i++) {
4983 type = board->caldac[i];
4984 if (type == caldac_none)
4986 if (caldacs[type].n_bits != n_bits)
4988 n_chans += caldacs[type].n_chans;
4991 s->n_chan = n_chans;
4994 unsigned int *maxdata_list;
4996 if (n_chans > MAX_N_CALDACS) {
4997 printk("BUG! MAX_N_CALDACS too small\n");
4999 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5001 for (i = 0; i < n_dacs; i++) {
5002 type = board->caldac[i];
5003 for (j = 0; j < caldacs[type].n_chans; j++) {
5004 maxdata_list[chan] =
5005 (1 << caldacs[type].n_bits) - 1;
5010 for (chan = 0; chan < s->n_chan; chan++)
5011 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5013 type = board->caldac[0];
5014 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5016 for (chan = 0; chan < s->n_chan; chan++)
5017 ni_write_caldac(dev, i, s->maxdata / 2);
5021 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5023 const struct ni_board_struct *board = comedi_board(dev);
5024 struct ni_private *devpriv = dev->private;
5025 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5029 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5030 if (devpriv->caldacs[addr] == val)
5032 devpriv->caldacs[addr] = val;
5034 for (i = 0; i < 3; i++) {
5035 type = board->caldac[i];
5036 if (type == caldac_none)
5038 if (addr < caldacs[type].n_chans) {
5039 bits = caldacs[type].packbits(addr, val, &bitstring);
5040 loadbit = SerDacLd(i);
5041 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5044 addr -= caldacs[type].n_chans;
5047 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5048 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5050 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5053 ni_writeb(loadbit, Serial_Command);
5055 ni_writeb(0, Serial_Command);
5058 static int pack_mb88341(int addr, int val, int *bitstring)
5062 Note that address bits are reversed. Thanks to
5063 Ingo Keen for noticing this.
5065 Note also that the 88341 expects address values from
5066 1-12, whereas we use channel numbers 0-11. The NI
5067 docs use 1-12, also, so be careful here.
5070 *bitstring = ((addr & 0x1) << 11) |
5071 ((addr & 0x2) << 9) |
5072 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5076 static int pack_dac8800(int addr, int val, int *bitstring)
5078 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5082 static int pack_dac8043(int addr, int val, int *bitstring)
5084 *bitstring = val & 0xfff;
5088 static int pack_ad8522(int addr, int val, int *bitstring)
5090 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5094 static int pack_ad8804(int addr, int val, int *bitstring)
5096 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5100 static int pack_ad8842(int addr, int val, int *bitstring)
5102 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5108 * Read the GPCTs current value.
5110 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5112 unsigned int hi1, hi2, lo;
5114 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5115 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5116 G_Command_Register(chan));
5118 devpriv->gpct_command[chan] |= G_Save_Trace;
5119 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5120 G_Command_Register(chan));
5122 /* This procedure is used because the two registers cannot
5123 * be read atomically. */
5125 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5126 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5127 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5128 } while (hi1 != hi2);
5130 return (hi1 << 16) | lo;
5133 static void GPCT_Reset(struct comedi_device *dev, int chan)
5135 int temp_ack_reg = 0;
5137 /* printk("GPCT_Reset..."); */
5138 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5142 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5143 ni_set_bits(dev, Interrupt_A_Enable_Register,
5144 G0_TC_Interrupt_Enable, 0);
5145 ni_set_bits(dev, Interrupt_A_Enable_Register,
5146 G0_Gate_Interrupt_Enable, 0);
5147 temp_ack_reg |= G0_Gate_Error_Confirm;
5148 temp_ack_reg |= G0_TC_Error_Confirm;
5149 temp_ack_reg |= G0_TC_Interrupt_Ack;
5150 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5151 devpriv->stc_writew(dev, temp_ack_reg,
5152 Interrupt_A_Ack_Register);
5154 /* problem...this interferes with the other ctr... */
5155 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5156 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5157 Analog_Trigger_Etc_Register);
5160 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5161 ni_set_bits(dev, Interrupt_B_Enable_Register,
5162 G1_TC_Interrupt_Enable, 0);
5163 ni_set_bits(dev, Interrupt_B_Enable_Register,
5164 G0_Gate_Interrupt_Enable, 0);
5165 temp_ack_reg |= G1_Gate_Error_Confirm;
5166 temp_ack_reg |= G1_TC_Error_Confirm;
5167 temp_ack_reg |= G1_TC_Interrupt_Ack;
5168 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5169 devpriv->stc_writew(dev, temp_ack_reg,
5170 Interrupt_B_Ack_Register);
5172 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5173 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5174 Analog_Trigger_Etc_Register);
5178 devpriv->gpct_mode[chan] = 0;
5179 devpriv->gpct_input_select[chan] = 0;
5180 devpriv->gpct_command[chan] = 0;
5182 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5184 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5185 G_Mode_Register(chan));
5186 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5187 G_Input_Select_Register(chan));
5188 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5190 /* printk("exit GPCT_Reset\n"); */
5195 static int ni_gpct_insn_config(struct comedi_device *dev,
5196 struct comedi_subdevice *s,
5197 struct comedi_insn *insn, unsigned int *data)
5199 struct ni_gpct *counter = s->private;
5200 return ni_tio_insn_config(counter, insn, data);
5203 static int ni_gpct_insn_read(struct comedi_device *dev,
5204 struct comedi_subdevice *s,
5205 struct comedi_insn *insn, unsigned int *data)
5207 struct ni_gpct *counter = s->private;
5208 return ni_tio_rinsn(counter, insn, data);
5211 static int ni_gpct_insn_write(struct comedi_device *dev,
5212 struct comedi_subdevice *s,
5213 struct comedi_insn *insn, unsigned int *data)
5215 struct ni_gpct *counter = s->private;
5216 return ni_tio_winsn(counter, insn, data);
5219 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5223 struct ni_gpct *counter = s->private;
5224 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5226 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5230 "no dma channel available for use by counter");
5233 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5234 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5235 retval = ni_tio_cmd(counter, s->async);
5242 static int ni_gpct_cmdtest(struct comedi_device *dev,
5243 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5246 struct ni_gpct *counter = s->private;
5248 return ni_tio_cmdtest(counter, cmd);
5254 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5257 struct ni_gpct *counter = s->private;
5260 retval = ni_tio_cancel(counter);
5261 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5262 ni_release_gpct_mite_channel(dev, counter->counter_index);
5271 * Programmable Function Inputs
5275 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5278 struct ni_private *devpriv = dev->private;
5279 unsigned pfi_reg_index;
5280 unsigned array_offset;
5282 if ((source & 0x1f) != source)
5284 pfi_reg_index = 1 + chan / 3;
5285 array_offset = pfi_reg_index - 1;
5286 devpriv->pfi_output_select_reg[array_offset] &=
5287 ~MSeries_PFI_Output_Select_Mask(chan);
5288 devpriv->pfi_output_select_reg[array_offset] |=
5289 MSeries_PFI_Output_Select_Bits(chan, source);
5290 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5291 M_Offset_PFI_Output_Select(pfi_reg_index));
5295 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5298 /* pre-m-series boards have fixed signals on pfi pins */
5299 if (source != ni_old_get_pfi_routing(dev, chan))
5304 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5307 const struct ni_board_struct *board = comedi_board(dev);
5309 if (board->reg_type & ni_reg_m_series_mask)
5310 return ni_m_series_set_pfi_routing(dev, chan, source);
5312 return ni_old_set_pfi_routing(dev, chan, source);
5315 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5318 struct ni_private *devpriv = dev->private;
5319 const unsigned array_offset = chan / 3;
5321 return MSeries_PFI_Output_Select_Source(chan,
5323 pfi_output_select_reg
5327 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5329 /* pre-m-series boards have fixed signals on pfi pins */
5332 return NI_PFI_OUTPUT_AI_START1;
5335 return NI_PFI_OUTPUT_AI_START2;
5338 return NI_PFI_OUTPUT_AI_CONVERT;
5341 return NI_PFI_OUTPUT_G_SRC1;
5344 return NI_PFI_OUTPUT_G_GATE1;
5347 return NI_PFI_OUTPUT_AO_UPDATE_N;
5350 return NI_PFI_OUTPUT_AO_START1;
5353 return NI_PFI_OUTPUT_AI_START_PULSE;
5356 return NI_PFI_OUTPUT_G_SRC0;
5359 return NI_PFI_OUTPUT_G_GATE0;
5362 printk("%s: bug, unhandled case in switch.\n", __func__);
5368 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5370 const struct ni_board_struct *board = comedi_board(dev);
5372 if (board->reg_type & ni_reg_m_series_mask)
5373 return ni_m_series_get_pfi_routing(dev, chan);
5375 return ni_old_get_pfi_routing(dev, chan);
5378 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5379 enum ni_pfi_filter_select filter)
5381 const struct ni_board_struct *board = comedi_board(dev);
5382 struct ni_private *devpriv __maybe_unused = dev->private;
5385 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5388 bits = ni_readl(M_Offset_PFI_Filter);
5389 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5390 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5391 ni_writel(bits, M_Offset_PFI_Filter);
5395 static int ni_pfi_insn_bits(struct comedi_device *dev,
5396 struct comedi_subdevice *s,
5397 struct comedi_insn *insn, unsigned int *data)
5399 const struct ni_board_struct *board = comedi_board(dev);
5400 struct ni_private *devpriv __maybe_unused = dev->private;
5402 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5406 s->state &= ~data[0];
5407 s->state |= (data[0] & data[1]);
5408 ni_writew(s->state, M_Offset_PFI_DO);
5410 data[1] = ni_readw(M_Offset_PFI_DI);
5414 static int ni_pfi_insn_config(struct comedi_device *dev,
5415 struct comedi_subdevice *s,
5416 struct comedi_insn *insn, unsigned int *data)
5418 struct ni_private *devpriv = dev->private;
5424 chan = CR_CHAN(insn->chanspec);
5428 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5431 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5433 case INSN_CONFIG_DIO_QUERY:
5435 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5436 COMEDI_OUTPUT : COMEDI_INPUT;
5439 case INSN_CONFIG_SET_ROUTING:
5440 return ni_set_pfi_routing(dev, chan, data[1]);
5442 case INSN_CONFIG_GET_ROUTING:
5443 data[1] = ni_get_pfi_routing(dev, chan);
5445 case INSN_CONFIG_FILTER:
5446 return ni_config_filter(dev, chan, data[1]);
5456 * NI RTSI Bus Functions
5459 static void ni_rtsi_init(struct comedi_device *dev)
5461 const struct ni_board_struct *board = comedi_board(dev);
5462 struct ni_private *devpriv = dev->private;
5464 /* Initialises the RTSI bus signal switch to a default state */
5466 /* Set clock mode to internal */
5467 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5468 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5469 printk("ni_set_master_clock failed, bug?");
5471 /* default internal lines routing to RTSI bus lines */
5472 devpriv->rtsi_trig_a_output_reg =
5473 RTSI_Trig_Output_Bits(0,
5474 NI_RTSI_OUTPUT_ADR_START1) |
5475 RTSI_Trig_Output_Bits(1,
5476 NI_RTSI_OUTPUT_ADR_START2) |
5477 RTSI_Trig_Output_Bits(2,
5478 NI_RTSI_OUTPUT_SCLKG) |
5479 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5480 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5481 RTSI_Trig_A_Output_Register);
5482 devpriv->rtsi_trig_b_output_reg =
5483 RTSI_Trig_Output_Bits(4,
5484 NI_RTSI_OUTPUT_DA_START1) |
5485 RTSI_Trig_Output_Bits(5,
5486 NI_RTSI_OUTPUT_G_SRC0) |
5487 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5488 if (board->reg_type & ni_reg_m_series_mask)
5489 devpriv->rtsi_trig_b_output_reg |=
5490 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5491 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5492 RTSI_Trig_B_Output_Register);
5495 * Sets the source and direction of the 4 on board lines
5496 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5500 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5501 struct comedi_subdevice *s,
5502 struct comedi_insn *insn, unsigned int *data)
5509 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5510 * given an arbitrary frequency input clock */
5511 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5512 unsigned *freq_divider,
5513 unsigned *freq_multiplier,
5514 unsigned *actual_period_ns)
5517 unsigned best_div = 1;
5518 static const unsigned max_div = 0x10;
5520 unsigned best_mult = 1;
5521 static const unsigned max_mult = 0x100;
5522 static const unsigned pico_per_nano = 1000;
5524 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5525 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5526 * 20 MHz for most timing clocks */
5527 static const unsigned target_picosec = 12500;
5528 static const unsigned fudge_factor_80_to_20Mhz = 4;
5529 int best_period_picosec = 0;
5530 for (div = 1; div <= max_div; ++div) {
5531 for (mult = 1; mult <= max_mult; ++mult) {
5532 unsigned new_period_ps =
5533 (reference_picosec * div) / mult;
5534 if (abs(new_period_ps - target_picosec) <
5535 abs(best_period_picosec - target_picosec)) {
5536 best_period_picosec = new_period_ps;
5542 if (best_period_picosec == 0) {
5543 printk("%s: bug, failed to find pll parameters\n", __func__);
5546 *freq_divider = best_div;
5547 *freq_multiplier = best_mult;
5549 (best_period_picosec * fudge_factor_80_to_20Mhz +
5550 (pico_per_nano / 2)) / pico_per_nano;
5554 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5556 const struct ni_board_struct *board = comedi_board(dev);
5558 if (board->reg_type & ni_reg_m_series_mask)
5564 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5565 unsigned source, unsigned period_ns)
5567 struct ni_private *devpriv = dev->private;
5568 static const unsigned min_period_ns = 50;
5569 static const unsigned max_period_ns = 1000;
5570 static const unsigned timeout = 1000;
5571 unsigned pll_control_bits;
5572 unsigned freq_divider;
5573 unsigned freq_multiplier;
5577 if (source == NI_MIO_PLL_PXI10_CLOCK)
5579 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5580 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5582 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5583 "for the phased-lock loop.\n", __func__,
5584 min_period_ns, max_period_ns);
5587 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5588 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5589 RTSI_Trig_Direction_Register);
5591 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5592 devpriv->clock_and_fout2 |=
5593 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5594 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5596 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5597 devpriv->clock_and_fout2 |=
5598 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5599 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5601 &devpriv->clock_ns);
5605 case NI_MIO_PLL_PXI10_CLOCK:
5606 /* pxi clock is 10MHz */
5607 devpriv->clock_and_fout2 |=
5608 MSeries_PLL_In_Source_Select_PXI_Clock10;
5609 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5611 &devpriv->clock_ns);
5617 unsigned rtsi_channel;
5618 static const unsigned max_rtsi_channel = 7;
5619 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5622 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5623 devpriv->clock_and_fout2 |=
5624 MSeries_PLL_In_Source_Select_RTSI_Bits
5629 if (rtsi_channel > max_rtsi_channel)
5631 retval = ni_mseries_get_pll_parameters(period_ns,
5641 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5643 MSeries_PLL_Divisor_Bits(freq_divider) |
5644 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5646 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5647 * freq_divider, freq_multiplier, pll_control_bits); */
5648 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5649 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5650 devpriv->clock_source = source;
5651 /* it seems to typically take a few hundred microseconds for PLL to lock */
5652 for (i = 0; i < timeout; ++i) {
5653 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5660 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5661 __func__, source, period_ns);
5667 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5670 const struct ni_board_struct *board = comedi_board(dev);
5671 struct ni_private *devpriv = dev->private;
5673 if (source == NI_MIO_INTERNAL_CLOCK) {
5674 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5675 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5676 RTSI_Trig_Direction_Register);
5677 devpriv->clock_ns = TIMEBASE_1_NS;
5678 if (board->reg_type & ni_reg_m_series_mask) {
5679 devpriv->clock_and_fout2 &=
5680 ~(MSeries_Timebase1_Select_Bit |
5681 MSeries_Timebase3_Select_Bit);
5682 ni_writew(devpriv->clock_and_fout2,
5683 M_Offset_Clock_and_Fout2);
5684 ni_writew(0, M_Offset_PLL_Control);
5686 devpriv->clock_source = source;
5688 if (board->reg_type & ni_reg_m_series_mask) {
5689 return ni_mseries_set_pll_master_clock(dev, source,
5692 if (source == NI_MIO_RTSI_CLOCK) {
5693 devpriv->rtsi_trig_direction_reg |=
5695 devpriv->stc_writew(dev,
5697 rtsi_trig_direction_reg,
5698 RTSI_Trig_Direction_Register);
5699 if (period_ns == 0) {
5701 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5705 devpriv->clock_ns = period_ns;
5707 devpriv->clock_source = source;
5715 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5718 const struct ni_board_struct *board = comedi_board(dev);
5720 if (chan >= num_configurable_rtsi_channels(dev)) {
5721 if (chan == old_RTSI_clock_channel) {
5722 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5726 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5727 __func__, chan, old_RTSI_clock_channel);
5734 case NI_RTSI_OUTPUT_ADR_START1:
5735 case NI_RTSI_OUTPUT_ADR_START2:
5736 case NI_RTSI_OUTPUT_SCLKG:
5737 case NI_RTSI_OUTPUT_DACUPDN:
5738 case NI_RTSI_OUTPUT_DA_START1:
5739 case NI_RTSI_OUTPUT_G_SRC0:
5740 case NI_RTSI_OUTPUT_G_GATE0:
5741 case NI_RTSI_OUTPUT_RGOUT0:
5742 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5745 case NI_RTSI_OUTPUT_RTSI_OSC:
5746 if (board->reg_type & ni_reg_m_series_mask)
5757 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5760 struct ni_private *devpriv = dev->private;
5762 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5765 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5766 devpriv->rtsi_trig_a_output_reg |=
5767 RTSI_Trig_Output_Bits(chan, source);
5768 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5769 RTSI_Trig_A_Output_Register);
5770 } else if (chan < 8) {
5771 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5772 devpriv->rtsi_trig_b_output_reg |=
5773 RTSI_Trig_Output_Bits(chan, source);
5774 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5775 RTSI_Trig_B_Output_Register);
5780 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5782 struct ni_private *devpriv = dev->private;
5785 return RTSI_Trig_Output_Source(chan,
5786 devpriv->rtsi_trig_a_output_reg);
5787 } else if (chan < num_configurable_rtsi_channels(dev)) {
5788 return RTSI_Trig_Output_Source(chan,
5789 devpriv->rtsi_trig_b_output_reg);
5791 if (chan == old_RTSI_clock_channel)
5792 return NI_RTSI_OUTPUT_RTSI_OSC;
5793 printk("%s: bug! should never get here?\n", __func__);
5798 static int ni_rtsi_insn_config(struct comedi_device *dev,
5799 struct comedi_subdevice *s,
5800 struct comedi_insn *insn, unsigned int *data)
5802 const struct ni_board_struct *board = comedi_board(dev);
5803 struct ni_private *devpriv = dev->private;
5804 unsigned int chan = CR_CHAN(insn->chanspec);
5807 case INSN_CONFIG_DIO_OUTPUT:
5808 if (chan < num_configurable_rtsi_channels(dev)) {
5809 devpriv->rtsi_trig_direction_reg |=
5810 RTSI_Output_Bit(chan,
5811 (board->reg_type & ni_reg_m_series_mask) != 0);
5812 } else if (chan == old_RTSI_clock_channel) {
5813 devpriv->rtsi_trig_direction_reg |=
5814 Drive_RTSI_Clock_Bit;
5816 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5817 RTSI_Trig_Direction_Register);
5819 case INSN_CONFIG_DIO_INPUT:
5820 if (chan < num_configurable_rtsi_channels(dev)) {
5821 devpriv->rtsi_trig_direction_reg &=
5822 ~RTSI_Output_Bit(chan,
5823 (board->reg_type & ni_reg_m_series_mask) != 0);
5824 } else if (chan == old_RTSI_clock_channel) {
5825 devpriv->rtsi_trig_direction_reg &=
5826 ~Drive_RTSI_Clock_Bit;
5828 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5829 RTSI_Trig_Direction_Register);
5831 case INSN_CONFIG_DIO_QUERY:
5832 if (chan < num_configurable_rtsi_channels(dev)) {
5834 (devpriv->rtsi_trig_direction_reg &
5835 RTSI_Output_Bit(chan,
5836 (board->reg_type & ni_reg_m_series_mask) != 0))
5837 ? INSN_CONFIG_DIO_OUTPUT
5838 : INSN_CONFIG_DIO_INPUT;
5839 } else if (chan == old_RTSI_clock_channel) {
5841 (devpriv->rtsi_trig_direction_reg &
5842 Drive_RTSI_Clock_Bit)
5843 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5847 case INSN_CONFIG_SET_CLOCK_SRC:
5848 return ni_set_master_clock(dev, data[1], data[2]);
5850 case INSN_CONFIG_GET_CLOCK_SRC:
5851 data[1] = devpriv->clock_source;
5852 data[2] = devpriv->clock_ns;
5855 case INSN_CONFIG_SET_ROUTING:
5856 return ni_set_rtsi_routing(dev, chan, data[1]);
5858 case INSN_CONFIG_GET_ROUTING:
5859 data[1] = ni_get_rtsi_routing(dev, chan);
5869 static int cs5529_wait_for_idle(struct comedi_device *dev)
5871 unsigned short status;
5872 const int timeout = HZ;
5875 for (i = 0; i < timeout; i++) {
5876 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5877 if ((status & CSS_ADC_BUSY) == 0) {
5880 set_current_state(TASK_INTERRUPTIBLE);
5881 if (schedule_timeout(1)) {
5885 /* printk("looped %i times waiting for idle\n", i); */
5887 printk("%s: %s: timeout\n", __FILE__, __func__);
5893 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5895 static const int timeout = 100;
5898 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5899 /* give time for command to start being serially clocked into cs5529.
5900 * this insures that the CSS_ADC_BUSY bit will get properly
5901 * set before we exit this function.
5903 for (i = 0; i < timeout; i++) {
5904 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5908 /* printk("looped %i times writing command to cs5529\n", i); */
5910 comedi_error(dev, "possible problem - never saw adc go busy?");
5914 /* write to cs5529 register */
5915 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5916 unsigned int reg_select_bits)
5918 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5919 CAL_ADC_Config_Data_High_Word_67xx);
5920 ni_ao_win_outw(dev, (value & 0xffff),
5921 CAL_ADC_Config_Data_Low_Word_67xx);
5922 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5923 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5924 if (cs5529_wait_for_idle(dev))
5925 comedi_error(dev, "time or signal in cs5529_config_write()");
5928 #ifdef NI_CS5529_DEBUG
5929 /* read from cs5529 register */
5930 static unsigned int cs5529_config_read(struct comedi_device *dev,
5931 unsigned int reg_select_bits)
5935 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5936 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5937 if (cs5529_wait_for_idle(dev))
5938 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5939 value = (ni_ao_win_inw(dev,
5940 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5942 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5947 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5950 unsigned short status;
5952 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5953 retval = cs5529_wait_for_idle(dev);
5956 "timeout or signal in cs5529_do_conversion()");
5959 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5960 if (status & CSS_OSC_DETECT) {
5962 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5965 if (status & CSS_OVERRANGE) {
5967 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5970 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5971 /* cs5529 returns 16 bit signed data in bipolar mode */
5977 static int cs5529_ai_insn_read(struct comedi_device *dev,
5978 struct comedi_subdevice *s,
5979 struct comedi_insn *insn, unsigned int *data)
5982 unsigned short sample;
5983 unsigned int channel_select;
5984 const unsigned int INTERNAL_REF = 0x1000;
5986 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5987 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5988 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5989 if (insn->chanspec & CR_ALT_SOURCE)
5990 channel_select = INTERNAL_REF;
5992 channel_select = CR_CHAN(insn->chanspec);
5993 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5995 for (n = 0; n < insn->n; n++) {
5996 retval = cs5529_do_conversion(dev, &sample);
6004 static int init_cs5529(struct comedi_device *dev)
6006 unsigned int config_bits =
6007 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6010 /* do self-calibration */
6011 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6012 CSCMD_CONFIG_REGISTER);
6013 /* need to force a conversion for calibration to run */
6014 cs5529_do_conversion(dev, NULL);
6016 /* force gain calibration to 1 */
6017 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6018 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6019 CSCMD_CONFIG_REGISTER);
6020 if (cs5529_wait_for_idle(dev))
6021 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6023 #ifdef NI_CS5529_DEBUG
6024 printk("config: 0x%x\n", cs5529_config_read(dev,
6025 CSCMD_CONFIG_REGISTER));
6026 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6027 printk("offset: 0x%x\n", cs5529_config_read(dev,
6028 CSCMD_OFFSET_REGISTER));