2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
29 Interrupt support originally added by Truxton Fulton
32 References (from ftp://ftp.natinst.com/support/manuals):
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
40 Other possibly relevant info:
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
45 320906c.pdf maximum signal ratings
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
54 - the interrupt routine needs to be cleaned up
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
68 #include "comedi_fc.h"
71 #define MDPRINTK(format, args...)
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
192 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
200 static const struct comedi_lrange *const ni_range_lkup[] = {
201 [ai_gain_16] = &range_ni_E_ai,
202 [ai_gain_8] = &range_ni_E_ai_limited,
203 [ai_gain_14] = &range_ni_E_ai_limited14,
204 [ai_gain_4] = &range_ni_E_ai_bipolar4,
205 [ai_gain_611x] = &range_ni_E_ai_611x,
206 [ai_gain_622x] = &range_ni_M_ai_622x,
207 [ai_gain_628x] = &range_ni_M_ai_628x,
208 [ai_gain_6143] = &range_bipolar5
211 static int ni_dio_insn_config(struct comedi_device *dev,
212 struct comedi_subdevice *s,
213 struct comedi_insn *insn, unsigned int *data);
214 static int ni_dio_insn_bits(struct comedi_device *dev,
215 struct comedi_subdevice *s,
216 struct comedi_insn *insn, unsigned int *data);
217 static int ni_cdio_cmdtest(struct comedi_device *dev,
218 struct comedi_subdevice *s, struct comedi_cmd *cmd);
219 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
220 static int ni_cdio_cancel(struct comedi_device *dev,
221 struct comedi_subdevice *s);
222 static void handle_cdio_interrupt(struct comedi_device *dev);
223 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
224 unsigned int trignum);
226 static int ni_serial_insn_config(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_insn *insn, unsigned int *data);
229 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 unsigned char data_out,
232 unsigned char *data_in);
233 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 unsigned char data_out,
236 unsigned char *data_in);
238 static int ni_calib_insn_read(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 struct comedi_insn *insn, unsigned int *data);
241 static int ni_calib_insn_write(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_insn *insn, unsigned int *data);
245 static int ni_eeprom_insn_read(struct comedi_device *dev,
246 struct comedi_subdevice *s,
247 struct comedi_insn *insn, unsigned int *data);
248 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
249 struct comedi_subdevice *s,
250 struct comedi_insn *insn,
253 static int ni_pfi_insn_bits(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn, unsigned int *data);
256 static int ni_pfi_insn_config(struct comedi_device *dev,
257 struct comedi_subdevice *s,
258 struct comedi_insn *insn, unsigned int *data);
259 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
262 static void ni_rtsi_init(struct comedi_device *dev);
263 static int ni_rtsi_insn_bits(struct comedi_device *dev,
264 struct comedi_subdevice *s,
265 struct comedi_insn *insn, unsigned int *data);
266 static int ni_rtsi_insn_config(struct comedi_device *dev,
267 struct comedi_subdevice *s,
268 struct comedi_insn *insn, unsigned int *data);
270 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
271 static int ni_read_eeprom(struct comedi_device *dev, int addr);
273 #ifdef DEBUG_STATUS_A
274 static void ni_mio_print_status_a(int status);
276 #define ni_mio_print_status_a(a)
278 #ifdef DEBUG_STATUS_B
279 static void ni_mio_print_status_b(int status);
281 #define ni_mio_print_status_b(a)
284 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
286 static void ni_handle_fifo_half_full(struct comedi_device *dev);
287 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
288 struct comedi_subdevice *s);
290 static void ni_handle_fifo_dregs(struct comedi_device *dev);
291 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
292 unsigned int trignum);
293 static void ni_load_channelgain_list(struct comedi_device *dev,
294 unsigned int n_chan, unsigned int *list);
295 static void shutdown_ai_command(struct comedi_device *dev);
297 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
298 unsigned int trignum);
300 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
302 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
304 static int ni_gpct_insn_write(struct comedi_device *dev,
305 struct comedi_subdevice *s,
306 struct comedi_insn *insn, unsigned int *data);
307 static int ni_gpct_insn_read(struct comedi_device *dev,
308 struct comedi_subdevice *s,
309 struct comedi_insn *insn, unsigned int *data);
310 static int ni_gpct_insn_config(struct comedi_device *dev,
311 struct comedi_subdevice *s,
312 struct comedi_insn *insn, unsigned int *data);
314 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
315 static int ni_gpct_cmdtest(struct comedi_device *dev,
316 struct comedi_subdevice *s, struct comedi_cmd *cmd);
318 static int ni_gpct_cancel(struct comedi_device *dev,
319 struct comedi_subdevice *s);
320 static void handle_gpct_interrupt(struct comedi_device *dev,
321 unsigned short counter_index);
323 static int init_cs5529(struct comedi_device *dev);
324 static int cs5529_do_conversion(struct comedi_device *dev,
325 unsigned short *data);
326 static int cs5529_ai_insn_read(struct comedi_device *dev,
327 struct comedi_subdevice *s,
328 struct comedi_insn *insn, unsigned int *data);
329 #ifdef NI_CS5529_DEBUG
330 static unsigned int cs5529_config_read(struct comedi_device *dev,
331 unsigned int reg_select_bits);
333 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
334 unsigned int reg_select_bits);
336 static int ni_m_series_pwm_config(struct comedi_device *dev,
337 struct comedi_subdevice *s,
338 struct comedi_insn *insn, unsigned int *data);
339 static int ni_6143_pwm_config(struct comedi_device *dev,
340 struct comedi_subdevice *s,
341 struct comedi_insn *insn, unsigned int *data);
343 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
345 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
346 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
350 AIMODE_HALF_FULL = 1,
355 enum ni_common_subdevices {
361 NI_CALIBRATION_SUBDEV,
364 NI_CS5529_CALIBRATION_SUBDEV,
372 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
374 switch (counter_index) {
376 return NI_GPCT0_SUBDEV;
379 return NI_GPCT1_SUBDEV;
385 return NI_GPCT0_SUBDEV;
388 enum timebase_nanoseconds {
390 TIMEBASE_2_NS = 10000
393 #define SERIAL_DISABLED 0
394 #define SERIAL_600NS 600
395 #define SERIAL_1_2US 1200
396 #define SERIAL_10US 10000
398 static const int num_adc_stages_611x = 3;
400 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
401 unsigned ai_mite_status);
402 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
403 unsigned ao_mite_status);
404 static void get_last_sample_611x(struct comedi_device *dev);
405 static void get_last_sample_6143(struct comedi_device *dev);
407 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
408 unsigned bit_mask, unsigned bit_values)
410 struct ni_private *devpriv = dev->private;
413 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
415 case Interrupt_A_Enable_Register:
416 devpriv->int_a_enable_reg &= ~bit_mask;
417 devpriv->int_a_enable_reg |= bit_values & bit_mask;
418 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
419 Interrupt_A_Enable_Register);
421 case Interrupt_B_Enable_Register:
422 devpriv->int_b_enable_reg &= ~bit_mask;
423 devpriv->int_b_enable_reg |= bit_values & bit_mask;
424 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
425 Interrupt_B_Enable_Register);
427 case IO_Bidirection_Pin_Register:
428 devpriv->io_bidirection_pin_reg &= ~bit_mask;
429 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
430 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
431 IO_Bidirection_Pin_Register);
434 devpriv->ai_ao_select_reg &= ~bit_mask;
435 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
436 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
439 devpriv->g0_g1_select_reg &= ~bit_mask;
440 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
441 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
444 printk("Warning %s() called with invalid register\n", __func__);
445 printk("reg is %d\n", reg);
449 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
453 static int ni_ai_drain_dma(struct comedi_device *dev);
455 /* DMA channel setup */
457 /* negative channel means no channel */
458 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
464 (ni_stc_dma_channel_select_bitfield(channel) <<
465 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
469 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
472 /* negative channel means no channel */
473 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
479 (ni_stc_dma_channel_select_bitfield(channel) <<
480 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
484 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
487 /* negative mite_channel means no channel */
488 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
494 if (mite_channel >= 0) {
495 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
499 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
503 /* negative mite_channel means no channel */
504 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
507 struct ni_private *devpriv = dev->private;
510 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
511 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
512 if (mite_channel >= 0) {
513 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
514 under the assumption the cdio dma selection works just like ai/ao/gpct.
515 Definitely works for dma channels 0 and 1. */
516 devpriv->cdio_dma_select_reg |=
517 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
518 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
520 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
522 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
525 static int ni_request_ai_mite_channel(struct comedi_device *dev)
527 struct ni_private *devpriv = dev->private;
530 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
531 BUG_ON(devpriv->ai_mite_chan);
532 devpriv->ai_mite_chan =
533 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
534 if (devpriv->ai_mite_chan == NULL) {
535 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
537 "failed to reserve mite dma channel for analog input.");
540 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
541 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
542 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
546 static int ni_request_ao_mite_channel(struct comedi_device *dev)
548 struct ni_private *devpriv = dev->private;
551 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
552 BUG_ON(devpriv->ao_mite_chan);
553 devpriv->ao_mite_chan =
554 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
555 if (devpriv->ao_mite_chan == NULL) {
556 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
558 "failed to reserve mite dma channel for analog outut.");
561 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
562 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
563 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
567 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
569 enum comedi_io_direction direction)
571 struct ni_private *devpriv = dev->private;
573 struct mite_channel *mite_chan;
575 BUG_ON(gpct_index >= NUM_GPCT);
576 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
577 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
579 mite_request_channel(devpriv->mite,
580 devpriv->gpct_mite_ring[gpct_index]);
581 if (mite_chan == NULL) {
582 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
584 "failed to reserve mite dma channel for counter.");
587 mite_chan->dir = direction;
588 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
590 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
591 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
597 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
600 struct ni_private *devpriv = dev->private;
603 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
604 BUG_ON(devpriv->cdo_mite_chan);
605 devpriv->cdo_mite_chan =
606 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
607 if (devpriv->cdo_mite_chan == NULL) {
608 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
610 "failed to reserve mite dma channel for correlated digital outut.");
613 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
614 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
615 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
620 static void ni_release_ai_mite_channel(struct comedi_device *dev)
623 struct ni_private *devpriv = dev->private;
626 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
627 if (devpriv->ai_mite_chan) {
628 ni_set_ai_dma_channel(dev, -1);
629 mite_release_channel(devpriv->ai_mite_chan);
630 devpriv->ai_mite_chan = NULL;
632 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
636 static void ni_release_ao_mite_channel(struct comedi_device *dev)
639 struct ni_private *devpriv = dev->private;
642 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
643 if (devpriv->ao_mite_chan) {
644 ni_set_ao_dma_channel(dev, -1);
645 mite_release_channel(devpriv->ao_mite_chan);
646 devpriv->ao_mite_chan = NULL;
648 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
653 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
656 struct ni_private *devpriv = dev->private;
659 BUG_ON(gpct_index >= NUM_GPCT);
660 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
661 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
662 struct mite_channel *mite_chan =
663 devpriv->counter_dev->counters[gpct_index].mite_chan;
665 ni_set_gpct_dma_channel(dev, gpct_index, -1);
666 ni_tio_set_mite_channel(&devpriv->
667 counter_dev->counters[gpct_index],
669 mite_release_channel(mite_chan);
671 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
675 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
678 struct ni_private *devpriv = dev->private;
681 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
682 if (devpriv->cdo_mite_chan) {
683 ni_set_cdo_dma_channel(dev, -1);
684 mite_release_channel(devpriv->cdo_mite_chan);
685 devpriv->cdo_mite_chan = NULL;
687 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
691 /* e-series boards use the second irq signals to generate dma requests for their counters */
693 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
694 unsigned gpct_index, short enable)
696 const struct ni_board_struct *board = comedi_board(dev);
697 struct ni_private *devpriv = dev->private;
699 if (board->reg_type & ni_reg_m_series_mask)
701 switch (gpct_index) {
704 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
705 Second_IRQ_A_Enable_Register);
707 devpriv->stc_writew(dev, 0,
708 Second_IRQ_A_Enable_Register);
713 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
714 Second_IRQ_B_Enable_Register);
716 devpriv->stc_writew(dev, 0,
717 Second_IRQ_B_Enable_Register);
727 static void ni_clear_ai_fifo(struct comedi_device *dev)
729 const struct ni_board_struct *board = comedi_board(dev);
730 struct ni_private *devpriv = dev->private;
732 if (board->reg_type == ni_reg_6143) {
733 /* Flush the 6143 data FIFO */
734 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
735 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
736 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
738 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
739 if (board->reg_type == ni_reg_625x) {
740 ni_writeb(0, M_Offset_Static_AI_Control(0));
741 ni_writeb(1, M_Offset_Static_AI_Control(0));
743 /* the NI example code does 3 convert pulses for 625x boards,
744 but that appears to be wrong in practice. */
745 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
746 AI_Command_1_Register);
747 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
748 AI_Command_1_Register);
749 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
750 AI_Command_1_Register);
756 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
758 struct ni_private *devpriv = dev->private;
760 devpriv->stc_writew(dev, data >> 16, reg);
761 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
764 static uint32_t win_in2(struct comedi_device *dev, int reg)
766 struct ni_private *devpriv = dev->private;
769 bits = devpriv->stc_readw(dev, reg) << 16;
770 bits |= devpriv->stc_readw(dev, reg + 1);
774 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
775 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
778 struct ni_private *devpriv = dev->private;
781 spin_lock_irqsave(&devpriv->window_lock, flags);
782 ni_writew(addr, AO_Window_Address_611x);
783 ni_writew(data, AO_Window_Data_611x);
784 spin_unlock_irqrestore(&devpriv->window_lock, flags);
787 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
790 struct ni_private *devpriv = dev->private;
793 spin_lock_irqsave(&devpriv->window_lock, flags);
794 ni_writew(addr, AO_Window_Address_611x);
795 ni_writel(data, AO_Window_Data_611x);
796 spin_unlock_irqrestore(&devpriv->window_lock, flags);
799 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
801 struct ni_private *devpriv = dev->private;
805 spin_lock_irqsave(&devpriv->window_lock, flags);
806 ni_writew(addr, AO_Window_Address_611x);
807 data = ni_readw(AO_Window_Data_611x);
808 spin_unlock_irqrestore(&devpriv->window_lock, flags);
812 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
813 * share registers (such as Interrupt_A_Register) without interfering with
816 * NOTE: the switch/case statements are optimized out for a constant argument
817 * so this is actually quite fast--- If you must wrap another function around this
818 * make it inline to avoid a large speed penalty.
820 * value should only be 1 or 0.
822 static inline void ni_set_bits(struct comedi_device *dev, int reg,
823 unsigned bits, unsigned value)
831 ni_set_bitfield(dev, reg, bits, bit_values);
834 static irqreturn_t ni_E_interrupt(int irq, void *d)
836 struct comedi_device *dev = d;
837 struct ni_private *devpriv = dev->private;
838 unsigned short a_status;
839 unsigned short b_status;
840 unsigned int ai_mite_status = 0;
841 unsigned int ao_mite_status = 0;
844 struct mite_struct *mite = devpriv->mite;
849 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
851 /* lock to avoid race with comedi_poll */
852 spin_lock_irqsave(&dev->spinlock, flags);
853 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
854 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
857 unsigned long flags_too;
859 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
860 if (devpriv->ai_mite_chan) {
861 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
862 if (ai_mite_status & CHSR_LINKC)
864 devpriv->mite->mite_io_addr +
866 ai_mite_chan->channel));
868 if (devpriv->ao_mite_chan) {
869 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
870 if (ao_mite_status & CHSR_LINKC)
874 ao_mite_chan->channel));
876 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
879 ack_a_interrupt(dev, a_status);
880 ack_b_interrupt(dev, b_status);
881 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
882 handle_a_interrupt(dev, a_status, ai_mite_status);
883 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
884 handle_b_interrupt(dev, b_status, ao_mite_status);
885 handle_gpct_interrupt(dev, 0);
886 handle_gpct_interrupt(dev, 1);
887 handle_cdio_interrupt(dev);
889 spin_unlock_irqrestore(&dev->spinlock, flags);
894 static void ni_sync_ai_dma(struct comedi_device *dev)
896 struct ni_private *devpriv = dev->private;
897 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
900 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
901 if (devpriv->ai_mite_chan)
902 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
903 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
906 static void mite_handle_b_linkc(struct mite_struct *mite,
907 struct comedi_device *dev)
909 struct ni_private *devpriv = dev->private;
910 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
913 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
914 if (devpriv->ao_mite_chan) {
915 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
917 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
920 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
922 struct ni_private *devpriv = dev->private;
923 static const int timeout = 10000;
925 for (i = 0; i < timeout; i++) {
926 unsigned short b_status;
928 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
929 if (b_status & AO_FIFO_Half_Full_St)
931 /* if we poll too often, the pci bus activity seems
932 to slow the dma transfer down */
936 comedi_error(dev, "timed out waiting for dma load");
943 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
945 struct ni_private *devpriv = dev->private;
947 if (devpriv->aimode == AIMODE_SCAN) {
949 static const int timeout = 10;
952 for (i = 0; i < timeout; i++) {
954 if ((s->async->events & COMEDI_CB_EOS))
959 ni_handle_fifo_dregs(dev);
960 s->async->events |= COMEDI_CB_EOS;
963 /* handle special case of single scan using AI_End_On_End_Of_Scan */
964 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
965 shutdown_ai_command(dev);
969 static void shutdown_ai_command(struct comedi_device *dev)
971 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
974 ni_ai_drain_dma(dev);
976 ni_handle_fifo_dregs(dev);
977 get_last_sample_611x(dev);
978 get_last_sample_6143(dev);
980 s->async->events |= COMEDI_CB_EOA;
983 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
986 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
995 case NI_GPCT0_SUBDEV:
996 case NI_GPCT1_SUBDEV:
997 ni_gpct_cancel(dev, s);
1000 ni_cdio_cancel(dev, s);
1006 comedi_event(dev, s);
1009 static void handle_gpct_interrupt(struct comedi_device *dev,
1010 unsigned short counter_index)
1013 struct ni_private *devpriv = dev->private;
1014 struct comedi_subdevice *s;
1016 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1018 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1020 if (s->async->events)
1025 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1027 struct ni_private *devpriv = dev->private;
1028 unsigned short ack = 0;
1030 if (a_status & AI_SC_TC_St) {
1031 ack |= AI_SC_TC_Interrupt_Ack;
1033 if (a_status & AI_START1_St) {
1034 ack |= AI_START1_Interrupt_Ack;
1036 if (a_status & AI_START_St) {
1037 ack |= AI_START_Interrupt_Ack;
1039 if (a_status & AI_STOP_St) {
1040 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1041 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1044 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1047 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1048 unsigned ai_mite_status)
1050 struct ni_private *devpriv = dev->private;
1051 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1053 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1054 if (s->type == COMEDI_SUBD_UNUSED)
1057 #ifdef DEBUG_INTERRUPT
1059 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1060 status, ai_mite_status);
1061 ni_mio_print_status_a(status);
1064 if (ai_mite_status & CHSR_LINKC) {
1065 ni_sync_ai_dma(dev);
1068 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1069 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1070 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1072 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1074 /* mite_print_chsr(ai_mite_status); */
1075 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1076 /* disable_irq(dev->irq); */
1080 /* test for all uncommon interrupt events at the same time */
1081 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1082 AI_SC_TC_St | AI_START1_St)) {
1083 if (status == 0xffff) {
1085 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1086 /* we probably aren't even running a command now,
1087 * so it's a good idea to be careful. */
1088 if (comedi_is_subdevice_running(s)) {
1090 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1095 if (status & (AI_Overrun_St | AI_Overflow_St |
1096 AI_SC_TC_Error_St)) {
1097 printk("ni_mio_common: ai error a_status=%04x\n",
1099 ni_mio_print_status_a(status);
1101 shutdown_ai_command(dev);
1103 s->async->events |= COMEDI_CB_ERROR;
1104 if (status & (AI_Overrun_St | AI_Overflow_St))
1105 s->async->events |= COMEDI_CB_OVERFLOW;
1111 if (status & AI_SC_TC_St) {
1112 #ifdef DEBUG_INTERRUPT
1113 printk("ni_mio_common: SC_TC interrupt\n");
1115 if (!devpriv->ai_continuous) {
1116 shutdown_ai_command(dev);
1121 if (status & AI_FIFO_Half_Full_St) {
1123 static const int timeout = 10;
1124 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1125 *fail to get the fifo less than half full, so loop to be sure.*/
1126 for (i = 0; i < timeout; ++i) {
1127 ni_handle_fifo_half_full(dev);
1128 if ((devpriv->stc_readw(dev,
1129 AI_Status_1_Register) &
1130 AI_FIFO_Half_Full_St) == 0)
1134 #endif /* !PCIDMA */
1136 if ((status & AI_STOP_St)) {
1137 ni_handle_eos(dev, s);
1142 #ifdef DEBUG_INTERRUPT
1143 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1144 if (status & Interrupt_A_St) {
1146 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1152 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1154 struct ni_private *devpriv = dev->private;
1155 unsigned short ack = 0;
1157 if (b_status & AO_BC_TC_St) {
1158 ack |= AO_BC_TC_Interrupt_Ack;
1160 if (b_status & AO_Overrun_St) {
1161 ack |= AO_Error_Interrupt_Ack;
1163 if (b_status & AO_START_St) {
1164 ack |= AO_START_Interrupt_Ack;
1166 if (b_status & AO_START1_St) {
1167 ack |= AO_START1_Interrupt_Ack;
1169 if (b_status & AO_UC_TC_St) {
1170 ack |= AO_UC_TC_Interrupt_Ack;
1172 if (b_status & AO_UI2_TC_St) {
1173 ack |= AO_UI2_TC_Interrupt_Ack;
1175 if (b_status & AO_UPDATE_St) {
1176 ack |= AO_UPDATE_Interrupt_Ack;
1179 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1182 static void handle_b_interrupt(struct comedi_device *dev,
1183 unsigned short b_status, unsigned ao_mite_status)
1185 struct ni_private *devpriv = dev->private;
1186 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1187 /* unsigned short ack=0; */
1189 #ifdef DEBUG_INTERRUPT
1190 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1191 b_status, ao_mite_status);
1192 ni_mio_print_status_b(b_status);
1196 /* Currently, mite.c requires us to handle LINKC */
1197 if (ao_mite_status & CHSR_LINKC) {
1198 mite_handle_b_linkc(devpriv->mite, dev);
1201 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1202 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1203 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1205 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1207 /* mite_print_chsr(ao_mite_status); */
1208 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1212 if (b_status == 0xffff)
1214 if (b_status & AO_Overrun_St) {
1216 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1217 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1218 s->async->events |= COMEDI_CB_OVERFLOW;
1221 if (b_status & AO_BC_TC_St) {
1223 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1224 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1225 s->async->events |= COMEDI_CB_EOA;
1228 if (b_status & AO_FIFO_Request_St) {
1231 ret = ni_ao_fifo_half_empty(dev, s);
1233 printk("ni_mio_common: AO buffer underrun\n");
1234 ni_set_bits(dev, Interrupt_B_Enable_Register,
1235 AO_FIFO_Interrupt_Enable |
1236 AO_Error_Interrupt_Enable, 0);
1237 s->async->events |= COMEDI_CB_OVERFLOW;
1245 #ifdef DEBUG_STATUS_A
1246 static const char *const status_a_strings[] = {
1247 "passthru0", "fifo", "G0_gate", "G0_TC",
1248 "stop", "start", "sc_tc", "start1",
1249 "start2", "sc_tc_error", "overflow", "overrun",
1250 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1253 static void ni_mio_print_status_a(int status)
1257 printk("A status:");
1258 for (i = 15; i >= 0; i--) {
1259 if (status & (1 << i)) {
1260 printk(" %s", status_a_strings[i]);
1267 #ifdef DEBUG_STATUS_B
1268 static const char *const status_b_strings[] = {
1269 "passthru1", "fifo", "G1_gate", "G1_TC",
1270 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1271 "start1", "overrun", "start", "bc_tc_error",
1272 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1275 static void ni_mio_print_status_b(int status)
1279 printk("B status:");
1280 for (i = 15; i >= 0; i--) {
1281 if (status & (1 << i)) {
1282 printk(" %s", status_b_strings[i]);
1291 static void ni_ao_fifo_load(struct comedi_device *dev,
1292 struct comedi_subdevice *s, int n)
1294 const struct ni_board_struct *board = comedi_board(dev);
1295 struct comedi_async *async = s->async;
1296 struct comedi_cmd *cmd = &async->cmd;
1304 chan = async->cur_chan;
1305 for (i = 0; i < n; i++) {
1306 err &= comedi_buf_get(async, &d);
1310 range = CR_RANGE(cmd->chanlist[chan]);
1312 if (board->reg_type & ni_reg_6xxx_mask) {
1313 packed_data = d & 0xffff;
1314 /* 6711 only has 16 bit wide ao fifo */
1315 if (board->reg_type != ni_reg_6711) {
1316 err &= comedi_buf_get(async, &d);
1321 packed_data |= (d << 16) & 0xffff0000;
1323 ni_writel(packed_data, DAC_FIFO_Data_611x);
1325 ni_writew(d, DAC_FIFO_Data);
1328 chan %= cmd->chanlist_len;
1330 async->cur_chan = chan;
1332 async->events |= COMEDI_CB_OVERFLOW;
1337 * There's a small problem if the FIFO gets really low and we
1338 * don't have the data to fill it. Basically, if after we fill
1339 * the FIFO with all the data available, the FIFO is _still_
1340 * less than half full, we never clear the interrupt. If the
1341 * IRQ is in edge mode, we never get another interrupt, because
1342 * this one wasn't cleared. If in level mode, we get flooded
1343 * with interrupts that we can't fulfill, because nothing ever
1344 * gets put into the buffer.
1346 * This kind of situation is recoverable, but it is easier to
1347 * just pretend we had a FIFO underrun, since there is a good
1348 * chance it will happen anyway. This is _not_ the case for
1349 * RT code, as RT code might purposely be running close to the
1350 * metal. Needs to be fixed eventually.
1352 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1353 struct comedi_subdevice *s)
1355 const struct ni_board_struct *board = comedi_board(dev);
1358 n = comedi_buf_read_n_available(s->async);
1360 s->async->events |= COMEDI_CB_OVERFLOW;
1365 if (n > board->ao_fifo_depth / 2)
1366 n = board->ao_fifo_depth / 2;
1368 ni_ao_fifo_load(dev, s, n);
1370 s->async->events |= COMEDI_CB_BLOCK;
1375 static int ni_ao_prep_fifo(struct comedi_device *dev,
1376 struct comedi_subdevice *s)
1378 const struct ni_board_struct *board = comedi_board(dev);
1379 struct ni_private *devpriv = dev->private;
1383 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1384 if (board->reg_type & ni_reg_6xxx_mask)
1385 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1387 /* load some data */
1388 n = comedi_buf_read_n_available(s->async);
1393 if (n > board->ao_fifo_depth)
1394 n = board->ao_fifo_depth;
1396 ni_ao_fifo_load(dev, s, n);
1401 static void ni_ai_fifo_read(struct comedi_device *dev,
1402 struct comedi_subdevice *s, int n)
1404 const struct ni_board_struct *board = comedi_board(dev);
1405 struct ni_private *devpriv = dev->private;
1406 struct comedi_async *async = s->async;
1409 if (board->reg_type == ni_reg_611x) {
1413 for (i = 0; i < n / 2; i++) {
1414 dl = ni_readl(ADC_FIFO_Data_611x);
1415 /* This may get the hi/lo data in the wrong order */
1416 data[0] = (dl >> 16) & 0xffff;
1417 data[1] = dl & 0xffff;
1418 cfc_write_array_to_buffer(s, data, sizeof(data));
1420 /* Check if there's a single sample stuck in the FIFO */
1422 dl = ni_readl(ADC_FIFO_Data_611x);
1423 data[0] = dl & 0xffff;
1424 cfc_write_to_buffer(s, data[0]);
1426 } else if (board->reg_type == ni_reg_6143) {
1430 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1431 for (i = 0; i < n / 2; i++) {
1432 dl = ni_readl(AIFIFO_Data_6143);
1434 data[0] = (dl >> 16) & 0xffff;
1435 data[1] = dl & 0xffff;
1436 cfc_write_array_to_buffer(s, data, sizeof(data));
1439 /* Assume there is a single sample stuck in the FIFO */
1440 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1441 dl = ni_readl(AIFIFO_Data_6143);
1442 data[0] = (dl >> 16) & 0xffff;
1443 cfc_write_to_buffer(s, data[0]);
1446 if (n > sizeof(devpriv->ai_fifo_buffer) /
1447 sizeof(devpriv->ai_fifo_buffer[0])) {
1448 comedi_error(dev, "bug! ai_fifo_buffer too small");
1449 async->events |= COMEDI_CB_ERROR;
1452 for (i = 0; i < n; i++) {
1453 devpriv->ai_fifo_buffer[i] =
1454 ni_readw(ADC_FIFO_Data_Register);
1456 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1458 sizeof(devpriv->ai_fifo_buffer[0]));
1462 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1464 const struct ni_board_struct *board = comedi_board(dev);
1465 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1468 n = board->ai_fifo_depth / 2;
1470 ni_ai_fifo_read(dev, s, n);
1475 static int ni_ai_drain_dma(struct comedi_device *dev)
1477 struct ni_private *devpriv = dev->private;
1479 static const int timeout = 10000;
1480 unsigned long flags;
1483 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1484 if (devpriv->ai_mite_chan) {
1485 for (i = 0; i < timeout; i++) {
1486 if ((devpriv->stc_readw(dev,
1487 AI_Status_1_Register) &
1489 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1495 printk("ni_mio_common: wait for dma drain timed out\n");
1497 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1498 mite_bytes_in_transit(devpriv->ai_mite_chan),
1499 devpriv->stc_readw(dev, AI_Status_1_Register));
1503 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1505 ni_sync_ai_dma(dev);
1513 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1515 const struct ni_board_struct *board = comedi_board(dev);
1516 struct ni_private *devpriv = dev->private;
1517 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1523 if (board->reg_type == ni_reg_611x) {
1524 while ((devpriv->stc_readw(dev,
1525 AI_Status_1_Register) &
1526 AI_FIFO_Empty_St) == 0) {
1527 dl = ni_readl(ADC_FIFO_Data_611x);
1529 /* This may get the hi/lo data in the wrong order */
1530 data[0] = (dl >> 16);
1531 data[1] = (dl & 0xffff);
1532 cfc_write_array_to_buffer(s, data, sizeof(data));
1534 } else if (board->reg_type == ni_reg_6143) {
1536 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1537 dl = ni_readl(AIFIFO_Data_6143);
1539 /* This may get the hi/lo data in the wrong order */
1540 data[0] = (dl >> 16);
1541 data[1] = (dl & 0xffff);
1542 cfc_write_array_to_buffer(s, data, sizeof(data));
1545 /* Check if stranded sample is present */
1546 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1547 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1548 dl = ni_readl(AIFIFO_Data_6143);
1549 data[0] = (dl >> 16) & 0xffff;
1550 cfc_write_to_buffer(s, data[0]);
1555 devpriv->stc_readw(dev,
1556 AI_Status_1_Register) & AI_FIFO_Empty_St;
1557 while (fifo_empty == 0) {
1560 sizeof(devpriv->ai_fifo_buffer) /
1561 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1563 devpriv->stc_readw(dev,
1564 AI_Status_1_Register) &
1568 devpriv->ai_fifo_buffer[i] =
1569 ni_readw(ADC_FIFO_Data_Register);
1571 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1574 ai_fifo_buffer[0]));
1579 static void get_last_sample_611x(struct comedi_device *dev)
1581 const struct ni_board_struct *board = comedi_board(dev);
1582 struct ni_private *devpriv __maybe_unused = dev->private;
1583 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1587 if (board->reg_type != ni_reg_611x)
1590 /* Check if there's a single sample stuck in the FIFO */
1591 if (ni_readb(XXX_Status) & 0x80) {
1592 dl = ni_readl(ADC_FIFO_Data_611x);
1593 data = (dl & 0xffff);
1594 cfc_write_to_buffer(s, data);
1598 static void get_last_sample_6143(struct comedi_device *dev)
1600 const struct ni_board_struct *board = comedi_board(dev);
1601 struct ni_private *devpriv __maybe_unused = dev->private;
1602 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1606 if (board->reg_type != ni_reg_6143)
1609 /* Check if there's a single sample stuck in the FIFO */
1610 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1611 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1612 dl = ni_readl(AIFIFO_Data_6143);
1614 /* This may get the hi/lo data in the wrong order */
1615 data = (dl >> 16) & 0xffff;
1616 cfc_write_to_buffer(s, data);
1620 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1621 void *data, unsigned int num_bytes,
1622 unsigned int chan_index)
1624 struct ni_private *devpriv = dev->private;
1625 struct comedi_async *async = s->async;
1627 unsigned int length = num_bytes / bytes_per_sample(s);
1628 short *array = data;
1629 unsigned int *larray = data;
1631 for (i = 0; i < length; i++) {
1633 if (s->subdev_flags & SDF_LSAMPL)
1634 larray[i] = le32_to_cpu(larray[i]);
1636 array[i] = le16_to_cpu(array[i]);
1638 if (s->subdev_flags & SDF_LSAMPL)
1639 larray[i] += devpriv->ai_offset[chan_index];
1641 array[i] += devpriv->ai_offset[chan_index];
1643 chan_index %= async->cmd.chanlist_len;
1649 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1651 const struct ni_board_struct *board = comedi_board(dev);
1652 struct ni_private *devpriv = dev->private;
1653 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1655 unsigned long flags;
1657 retval = ni_request_ai_mite_channel(dev);
1660 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1662 /* write alloc the entire buffer */
1663 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1665 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1666 if (devpriv->ai_mite_chan == NULL) {
1667 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1671 switch (board->reg_type) {
1674 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1677 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1680 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1684 mite_dma_arm(devpriv->ai_mite_chan);
1685 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1690 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1692 const struct ni_board_struct *board = comedi_board(dev);
1693 struct ni_private *devpriv = dev->private;
1694 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1696 unsigned long flags;
1698 retval = ni_request_ao_mite_channel(dev);
1702 /* read alloc the entire buffer */
1703 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1705 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1706 if (devpriv->ao_mite_chan) {
1707 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1708 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1710 /* doing 32 instead of 16 bit wide transfers from memory
1711 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1712 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1714 mite_dma_arm(devpriv->ao_mite_chan);
1717 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1725 used for both cancel ioctl and board initialization
1727 this is pretty harsh for a cancel, but it works...
1730 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1732 const struct ni_board_struct *board = comedi_board(dev);
1733 struct ni_private *devpriv = dev->private;
1735 ni_release_ai_mite_channel(dev);
1736 /* ai configuration */
1737 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1738 Joint_Reset_Register);
1740 ni_set_bits(dev, Interrupt_A_Enable_Register,
1741 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1742 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1743 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1744 AI_FIFO_Interrupt_Enable, 0);
1746 ni_clear_ai_fifo(dev);
1748 if (board->reg_type != ni_reg_6143)
1749 ni_writeb(0, Misc_Command);
1751 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1752 devpriv->stc_writew(dev,
1753 AI_Start_Stop | AI_Mode_1_Reserved
1754 /*| AI_Trigger_Once */ ,
1755 AI_Mode_1_Register);
1756 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1757 /* generate FIFO interrupts on non-empty */
1758 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1759 if (board->reg_type == ni_reg_611x) {
1760 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1762 AI_LOCALMUX_CLK_Pulse_Width,
1763 AI_Personal_Register);
1764 devpriv->stc_writew(dev,
1765 AI_SCAN_IN_PROG_Output_Select(3) |
1766 AI_EXTMUX_CLK_Output_Select(0) |
1767 AI_LOCALMUX_CLK_Output_Select(2) |
1768 AI_SC_TC_Output_Select(3) |
1769 AI_CONVERT_Output_Select
1770 (AI_CONVERT_Output_Enable_High),
1771 AI_Output_Control_Register);
1772 } else if (board->reg_type == ni_reg_6143) {
1773 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1775 AI_LOCALMUX_CLK_Pulse_Width,
1776 AI_Personal_Register);
1777 devpriv->stc_writew(dev,
1778 AI_SCAN_IN_PROG_Output_Select(3) |
1779 AI_EXTMUX_CLK_Output_Select(0) |
1780 AI_LOCALMUX_CLK_Output_Select(2) |
1781 AI_SC_TC_Output_Select(3) |
1782 AI_CONVERT_Output_Select
1783 (AI_CONVERT_Output_Enable_Low),
1784 AI_Output_Control_Register);
1786 unsigned ai_output_control_bits;
1787 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1789 AI_CONVERT_Pulse_Width |
1790 AI_LOCALMUX_CLK_Pulse_Width,
1791 AI_Personal_Register);
1792 ai_output_control_bits =
1793 AI_SCAN_IN_PROG_Output_Select(3) |
1794 AI_EXTMUX_CLK_Output_Select(0) |
1795 AI_LOCALMUX_CLK_Output_Select(2) |
1796 AI_SC_TC_Output_Select(3);
1797 if (board->reg_type == ni_reg_622x)
1798 ai_output_control_bits |=
1799 AI_CONVERT_Output_Select
1800 (AI_CONVERT_Output_Enable_High);
1802 ai_output_control_bits |=
1803 AI_CONVERT_Output_Select
1804 (AI_CONVERT_Output_Enable_Low);
1805 devpriv->stc_writew(dev, ai_output_control_bits,
1806 AI_Output_Control_Register);
1808 /* the following registers should not be changed, because there
1809 * are no backup registers in devpriv. If you want to change
1810 * any of these, add a backup register and other appropriate code:
1811 * AI_Mode_1_Register
1812 * AI_Mode_3_Register
1813 * AI_Personal_Register
1814 * AI_Output_Control_Register
1816 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1818 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1823 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1825 unsigned long flags;
1828 /* lock to avoid race with interrupt handler */
1829 spin_lock_irqsave(&dev->spinlock, flags);
1831 ni_handle_fifo_dregs(dev);
1833 ni_sync_ai_dma(dev);
1835 count = s->async->buf_write_count - s->async->buf_read_count;
1836 spin_unlock_irqrestore(&dev->spinlock, flags);
1841 static int ni_ai_insn_read(struct comedi_device *dev,
1842 struct comedi_subdevice *s, struct comedi_insn *insn,
1845 const struct ni_board_struct *board = comedi_board(dev);
1846 struct ni_private *devpriv = dev->private;
1848 const unsigned int mask = (1 << board->adbits) - 1;
1853 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1855 ni_clear_ai_fifo(dev);
1857 signbits = devpriv->ai_offset[0];
1858 if (board->reg_type == ni_reg_611x) {
1859 for (n = 0; n < num_adc_stages_611x; n++) {
1860 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1861 AI_Command_1_Register);
1864 for (n = 0; n < insn->n; n++) {
1865 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1866 AI_Command_1_Register);
1867 /* The 611x has screwy 32-bit FIFOs. */
1869 for (i = 0; i < NI_TIMEOUT; i++) {
1870 if (ni_readb(XXX_Status) & 0x80) {
1871 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1875 if (!(devpriv->stc_readw(dev,
1876 AI_Status_1_Register) &
1877 AI_FIFO_Empty_St)) {
1878 d = ni_readl(ADC_FIFO_Data_611x) &
1883 if (i == NI_TIMEOUT) {
1885 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1891 } else if (board->reg_type == ni_reg_6143) {
1892 for (n = 0; n < insn->n; n++) {
1893 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1894 AI_Command_1_Register);
1896 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1898 for (i = 0; i < NI_TIMEOUT; i++) {
1899 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1900 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1901 dl = ni_readl(AIFIFO_Data_6143);
1905 if (i == NI_TIMEOUT) {
1907 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1910 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1913 for (n = 0; n < insn->n; n++) {
1914 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1915 AI_Command_1_Register);
1916 for (i = 0; i < NI_TIMEOUT; i++) {
1917 if (!(devpriv->stc_readw(dev,
1918 AI_Status_1_Register) &
1922 if (i == NI_TIMEOUT) {
1924 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1927 if (board->reg_type & ni_reg_m_series_mask) {
1929 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1931 d = ni_readw(ADC_FIFO_Data_Register);
1932 d += signbits; /* subtle: needs to be short addition */
1940 static void ni_prime_channelgain_list(struct comedi_device *dev)
1942 struct ni_private *devpriv = dev->private;
1945 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1946 for (i = 0; i < NI_TIMEOUT; ++i) {
1947 if (!(devpriv->stc_readw(dev,
1948 AI_Status_1_Register) &
1949 AI_FIFO_Empty_St)) {
1950 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1955 printk("ni_mio_common: timeout loading channel/gain list\n");
1958 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1959 unsigned int n_chan,
1962 const struct ni_board_struct *board = comedi_board(dev);
1963 struct ni_private *devpriv = dev->private;
1964 unsigned int chan, range, aref;
1967 unsigned int dither;
1968 unsigned range_code;
1970 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1972 /* offset = 1 << (board->adbits - 1); */
1973 if ((list[0] & CR_ALT_SOURCE)) {
1974 unsigned bypass_bits;
1975 chan = CR_CHAN(list[0]);
1976 range = CR_RANGE(list[0]);
1977 range_code = ni_gainlkup[board->gainlkup][range];
1978 dither = ((list[0] & CR_ALT_FILTER) != 0);
1979 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1980 bypass_bits |= chan;
1982 (devpriv->ai_calib_source) &
1983 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1984 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1985 MSeries_AI_Bypass_Mode_Mux_Mask |
1986 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1987 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1989 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1990 /* don't use 2's complement encoding */
1991 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1992 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1994 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1997 for (i = 0; i < n_chan; i++) {
1998 unsigned config_bits = 0;
1999 chan = CR_CHAN(list[i]);
2000 aref = CR_AREF(list[i]);
2001 range = CR_RANGE(list[i]);
2002 dither = ((list[i] & CR_ALT_FILTER) != 0);
2004 range_code = ni_gainlkup[board->gainlkup][range];
2005 devpriv->ai_offset[i] = offset;
2009 MSeries_AI_Config_Channel_Type_Differential_Bits;
2013 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2017 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2022 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2024 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2025 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2026 if (i == n_chan - 1)
2027 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2029 config_bits |= MSeries_AI_Config_Dither_Bit;
2030 /* don't use 2's complement encoding */
2031 config_bits |= MSeries_AI_Config_Polarity_Bit;
2032 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2034 ni_prime_channelgain_list(dev);
2038 * Notes on the 6110 and 6111:
2039 * These boards a slightly different than the rest of the series, since
2040 * they have multiple A/D converters.
2041 * From the driver side, the configuration memory is a
2043 * Configuration Memory Low:
2045 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2046 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2047 * 1001 gain=0.1 (+/- 50)
2056 * Configuration Memory High:
2057 * bits 12-14: Channel Type
2058 * 001 for differential
2059 * 000 for calibration
2060 * bit 11: coupling (this is not currently handled)
2064 * valid channels are 0-3
2066 static void ni_load_channelgain_list(struct comedi_device *dev,
2067 unsigned int n_chan, unsigned int *list)
2069 const struct ni_board_struct *board = comedi_board(dev);
2070 struct ni_private *devpriv = dev->private;
2071 unsigned int chan, range, aref;
2073 unsigned int hi, lo;
2075 unsigned int dither;
2077 if (board->reg_type & ni_reg_m_series_mask) {
2078 ni_m_series_load_channelgain_list(dev, n_chan, list);
2081 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2082 && (board->reg_type != ni_reg_6143)) {
2083 if (devpriv->changain_state
2084 && devpriv->changain_spec == list[0]) {
2088 devpriv->changain_state = 1;
2089 devpriv->changain_spec = list[0];
2091 devpriv->changain_state = 0;
2094 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2096 /* Set up Calibration mode if required */
2097 if (board->reg_type == ni_reg_6143) {
2098 if ((list[0] & CR_ALT_SOURCE)
2099 && !devpriv->ai_calib_source_enabled) {
2100 /* Strobe Relay enable bit */
2101 ni_writew(devpriv->ai_calib_source |
2102 Calibration_Channel_6143_RelayOn,
2103 Calibration_Channel_6143);
2104 ni_writew(devpriv->ai_calib_source,
2105 Calibration_Channel_6143);
2106 devpriv->ai_calib_source_enabled = 1;
2107 msleep_interruptible(100); /* Allow relays to change */
2108 } else if (!(list[0] & CR_ALT_SOURCE)
2109 && devpriv->ai_calib_source_enabled) {
2110 /* Strobe Relay disable bit */
2111 ni_writew(devpriv->ai_calib_source |
2112 Calibration_Channel_6143_RelayOff,
2113 Calibration_Channel_6143);
2114 ni_writew(devpriv->ai_calib_source,
2115 Calibration_Channel_6143);
2116 devpriv->ai_calib_source_enabled = 0;
2117 msleep_interruptible(100); /* Allow relays to change */
2121 offset = 1 << (board->adbits - 1);
2122 for (i = 0; i < n_chan; i++) {
2123 if ((board->reg_type != ni_reg_6143)
2124 && (list[i] & CR_ALT_SOURCE)) {
2125 chan = devpriv->ai_calib_source;
2127 chan = CR_CHAN(list[i]);
2129 aref = CR_AREF(list[i]);
2130 range = CR_RANGE(list[i]);
2131 dither = ((list[i] & CR_ALT_FILTER) != 0);
2133 /* fix the external/internal range differences */
2134 range = ni_gainlkup[board->gainlkup][range];
2135 if (board->reg_type == ni_reg_611x)
2136 devpriv->ai_offset[i] = offset;
2138 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2141 if ((list[i] & CR_ALT_SOURCE)) {
2142 if (board->reg_type == ni_reg_611x)
2143 ni_writew(CR_CHAN(list[i]) & 0x0003,
2144 Calibration_Channel_Select_611x);
2146 if (board->reg_type == ni_reg_611x)
2148 else if (board->reg_type == ni_reg_6143)
2152 hi |= AI_DIFFERENTIAL;
2164 hi |= AI_CONFIG_CHANNEL(chan);
2166 ni_writew(hi, Configuration_Memory_High);
2168 if (board->reg_type != ni_reg_6143) {
2170 if (i == n_chan - 1)
2171 lo |= AI_LAST_CHANNEL;
2175 ni_writew(lo, Configuration_Memory_Low);
2179 /* prime the channel/gain list */
2180 if ((board->reg_type != ni_reg_611x)
2181 && (board->reg_type != ni_reg_6143)) {
2182 ni_prime_channelgain_list(dev);
2186 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2189 struct ni_private *devpriv = dev->private;
2192 switch (round_mode) {
2193 case TRIG_ROUND_NEAREST:
2195 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2197 case TRIG_ROUND_DOWN:
2198 divider = (nanosec) / devpriv->clock_ns;
2201 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2207 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2209 struct ni_private *devpriv = dev->private;
2211 return devpriv->clock_ns * (timer + 1);
2214 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2215 unsigned num_channels)
2217 const struct ni_board_struct *board = comedi_board(dev);
2219 switch (board->reg_type) {
2222 /* simultaneously-sampled inputs */
2223 return board->ai_speed;
2226 /* multiplexed inputs */
2229 return board->ai_speed * num_channels;
2232 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2233 struct comedi_cmd *cmd)
2235 const struct ni_board_struct *board = comedi_board(dev);
2236 struct ni_private *devpriv = dev->private;
2239 unsigned int sources;
2241 /* Step 1 : check if triggers are trivially valid */
2243 if ((cmd->flags & CMDF_WRITE))
2244 cmd->flags &= ~CMDF_WRITE;
2246 err |= cfc_check_trigger_src(&cmd->start_src,
2247 TRIG_NOW | TRIG_INT | TRIG_EXT);
2248 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2249 TRIG_TIMER | TRIG_EXT);
2251 sources = TRIG_TIMER | TRIG_EXT;
2252 if (board->reg_type == ni_reg_611x ||
2253 board->reg_type == ni_reg_6143)
2254 sources |= TRIG_NOW;
2255 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2257 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2258 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2263 /* Step 2a : make sure trigger sources are unique */
2265 err |= cfc_check_trigger_is_unique(cmd->start_src);
2266 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2267 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2268 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2270 /* Step 2b : and mutually compatible */
2275 /* Step 3: check if arguments are trivially valid */
2277 if (cmd->start_src == TRIG_EXT) {
2278 /* external trigger */
2279 unsigned int tmp = CR_CHAN(cmd->start_arg);
2283 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2284 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2286 /* true for both TRIG_NOW and TRIG_INT */
2287 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2290 if (cmd->scan_begin_src == TRIG_TIMER) {
2291 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2292 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2293 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2294 devpriv->clock_ns * 0xffffff);
2295 } else if (cmd->scan_begin_src == TRIG_EXT) {
2296 /* external trigger */
2297 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2301 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2302 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2303 } else { /* TRIG_OTHER */
2304 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2307 if (cmd->convert_src == TRIG_TIMER) {
2308 if ((board->reg_type == ni_reg_611x)
2309 || (board->reg_type == ni_reg_6143)) {
2310 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2312 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2314 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2315 devpriv->clock_ns * 0xffff);
2317 } else if (cmd->convert_src == TRIG_EXT) {
2318 /* external trigger */
2319 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2323 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2324 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2325 } else if (cmd->convert_src == TRIG_NOW) {
2326 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2329 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2331 if (cmd->stop_src == TRIG_COUNT) {
2332 unsigned int max_count = 0x01000000;
2334 if (board->reg_type == ni_reg_611x)
2335 max_count -= num_adc_stages_611x;
2336 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2337 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2340 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2346 /* step 4: fix up any arguments */
2348 if (cmd->scan_begin_src == TRIG_TIMER) {
2349 tmp = cmd->scan_begin_arg;
2350 cmd->scan_begin_arg =
2351 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2352 cmd->scan_begin_arg,
2356 if (tmp != cmd->scan_begin_arg)
2359 if (cmd->convert_src == TRIG_TIMER) {
2360 if ((board->reg_type != ni_reg_611x)
2361 && (board->reg_type != ni_reg_6143)) {
2362 tmp = cmd->convert_arg;
2364 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2369 if (tmp != cmd->convert_arg)
2371 if (cmd->scan_begin_src == TRIG_TIMER &&
2372 cmd->scan_begin_arg <
2373 cmd->convert_arg * cmd->scan_end_arg) {
2374 cmd->scan_begin_arg =
2375 cmd->convert_arg * cmd->scan_end_arg;
2387 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2389 const struct ni_board_struct *board = comedi_board(dev);
2390 struct ni_private *devpriv = dev->private;
2391 const struct comedi_cmd *cmd = &s->async->cmd;
2393 int mode1 = 0; /* mode1 is needed for both stop and convert */
2395 int start_stop_select = 0;
2396 unsigned int stop_count;
2397 int interrupt_a_enable = 0;
2399 MDPRINTK("ni_ai_cmd\n");
2400 if (dev->irq == 0) {
2401 comedi_error(dev, "cannot run command without an irq");
2404 ni_clear_ai_fifo(dev);
2406 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2408 /* start configuration */
2409 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2411 /* disable analog triggering for now, since it
2412 * interferes with the use of pfi0 */
2413 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2414 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2415 Analog_Trigger_Etc_Register);
2417 switch (cmd->start_src) {
2420 devpriv->stc_writew(dev, AI_START2_Select(0) |
2421 AI_START1_Sync | AI_START1_Edge |
2422 AI_START1_Select(0),
2423 AI_Trigger_Select_Register);
2427 int chan = CR_CHAN(cmd->start_arg);
2428 unsigned int bits = AI_START2_Select(0) |
2429 AI_START1_Sync | AI_START1_Select(chan + 1);
2431 if (cmd->start_arg & CR_INVERT)
2432 bits |= AI_START1_Polarity;
2433 if (cmd->start_arg & CR_EDGE)
2434 bits |= AI_START1_Edge;
2435 devpriv->stc_writew(dev, bits,
2436 AI_Trigger_Select_Register);
2441 mode2 &= ~AI_Pre_Trigger;
2442 mode2 &= ~AI_SC_Initial_Load_Source;
2443 mode2 &= ~AI_SC_Reload_Mode;
2444 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2446 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2447 || (board->reg_type == ni_reg_6143)) {
2448 start_stop_select |= AI_STOP_Polarity;
2449 start_stop_select |= AI_STOP_Select(31); /* logic low */
2450 start_stop_select |= AI_STOP_Sync;
2452 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2454 devpriv->stc_writew(dev, start_stop_select,
2455 AI_START_STOP_Select_Register);
2457 devpriv->ai_cmd2 = 0;
2458 switch (cmd->stop_src) {
2460 stop_count = cmd->stop_arg - 1;
2462 if (board->reg_type == ni_reg_611x) {
2463 /* have to take 3 stage adc pipeline into account */
2464 stop_count += num_adc_stages_611x;
2466 /* stage number of scans */
2467 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2469 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2470 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2471 /* load SC (Scan Count) */
2472 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2474 devpriv->ai_continuous = 0;
2475 if (stop_count == 0) {
2476 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2477 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2478 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2479 if (cmd->chanlist_len > 1)
2480 start_stop_select |=
2481 AI_STOP_Polarity | AI_STOP_Edge;
2485 /* stage number of scans */
2486 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2488 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2489 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2491 /* load SC (Scan Count) */
2492 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2494 devpriv->ai_continuous = 1;
2499 switch (cmd->scan_begin_src) {
2502 stop bits for non 611x boards
2503 AI_SI_Special_Trigger_Delay=0
2505 AI_START_STOP_Select_Register:
2506 AI_START_Polarity=0 (?) rising edge
2507 AI_START_Edge=1 edge triggered
2509 AI_START_Select=0 SI_TC
2510 AI_STOP_Polarity=0 rising edge
2511 AI_STOP_Edge=0 level
2513 AI_STOP_Select=19 external pin (configuration mem)
2515 start_stop_select |= AI_START_Edge | AI_START_Sync;
2516 devpriv->stc_writew(dev, start_stop_select,
2517 AI_START_STOP_Select_Register);
2519 mode2 |= AI_SI_Reload_Mode(0);
2520 /* AI_SI_Initial_Load_Source=A */
2521 mode2 &= ~AI_SI_Initial_Load_Source;
2522 /* mode2 |= AI_SC_Reload_Mode; */
2523 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2526 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2527 TRIG_ROUND_NEAREST);
2528 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2529 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2532 if (cmd->scan_begin_arg & CR_EDGE)
2533 start_stop_select |= AI_START_Edge;
2534 /* AI_START_Polarity==1 is falling edge */
2535 if (cmd->scan_begin_arg & CR_INVERT)
2536 start_stop_select |= AI_START_Polarity;
2537 if (cmd->scan_begin_src != cmd->convert_src ||
2538 (cmd->scan_begin_arg & ~CR_EDGE) !=
2539 (cmd->convert_arg & ~CR_EDGE))
2540 start_stop_select |= AI_START_Sync;
2541 start_stop_select |=
2542 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2543 devpriv->stc_writew(dev, start_stop_select,
2544 AI_START_STOP_Select_Register);
2548 switch (cmd->convert_src) {
2551 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2554 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2555 TRIG_ROUND_NEAREST);
2556 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2557 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2559 /* AI_SI2_Reload_Mode = alternate */
2560 /* AI_SI2_Initial_Load_Source = A */
2561 mode2 &= ~AI_SI2_Initial_Load_Source;
2562 mode2 |= AI_SI2_Reload_Mode;
2563 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2566 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2568 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2569 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2571 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2574 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2575 if ((cmd->convert_arg & CR_INVERT) == 0)
2576 mode1 |= AI_CONVERT_Source_Polarity;
2577 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2579 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2580 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2587 /* interrupt on FIFO, errors, SC_TC */
2588 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2589 AI_SC_TC_Interrupt_Enable;
2592 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2595 if (cmd->flags & TRIG_WAKE_EOS
2596 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2597 /* wake on end-of-scan */
2598 devpriv->aimode = AIMODE_SCAN;
2600 devpriv->aimode = AIMODE_HALF_FULL;
2603 switch (devpriv->aimode) {
2604 case AIMODE_HALF_FULL:
2605 /*generate FIFO interrupts and DMA requests on half-full */
2607 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2608 AI_Mode_3_Register);
2610 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2611 AI_Mode_3_Register);
2615 /*generate FIFO interrupts on non-empty */
2616 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2617 AI_Mode_3_Register);
2621 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2622 AI_Mode_3_Register);
2624 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2625 AI_Mode_3_Register);
2627 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2633 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2635 ni_set_bits(dev, Interrupt_A_Enable_Register,
2636 interrupt_a_enable, 1);
2638 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2639 devpriv->int_a_enable_reg);
2641 /* interrupt on nothing */
2642 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2644 /* XXX start polling if necessary */
2645 MDPRINTK("interrupting on nothing\n");
2648 /* end configuration */
2649 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2651 switch (cmd->scan_begin_src) {
2653 devpriv->stc_writew(dev,
2654 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2655 AI_SC_Arm, AI_Command_1_Register);
2658 /* XXX AI_SI_Arm? */
2659 devpriv->stc_writew(dev,
2660 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2661 AI_SC_Arm, AI_Command_1_Register);
2667 int retval = ni_ai_setup_MITE_dma(dev);
2671 /* mite_dump_regs(devpriv->mite); */
2674 switch (cmd->start_src) {
2676 /* AI_START1_Pulse */
2677 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2678 AI_Command_2_Register);
2679 s->async->inttrig = NULL;
2682 s->async->inttrig = NULL;
2685 s->async->inttrig = &ni_ai_inttrig;
2689 MDPRINTK("exit ni_ai_cmd\n");
2694 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2695 unsigned int trignum)
2697 struct ni_private *devpriv = dev->private;
2702 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2703 AI_Command_2_Register);
2704 s->async->inttrig = NULL;
2709 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2710 struct comedi_subdevice *s,
2711 struct comedi_insn *insn,
2712 unsigned int *data);
2714 static int ni_ai_insn_config(struct comedi_device *dev,
2715 struct comedi_subdevice *s,
2716 struct comedi_insn *insn, unsigned int *data)
2718 const struct ni_board_struct *board = comedi_board(dev);
2719 struct ni_private *devpriv = dev->private;
2725 case INSN_CONFIG_ANALOG_TRIG:
2726 return ni_ai_config_analog_trig(dev, s, insn, data);
2727 case INSN_CONFIG_ALT_SOURCE:
2728 if (board->reg_type & ni_reg_m_series_mask) {
2729 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2730 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2731 MSeries_AI_Bypass_Mode_Mux_Mask |
2732 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2735 devpriv->ai_calib_source = data[1];
2736 } else if (board->reg_type == ni_reg_6143) {
2737 unsigned int calib_source;
2739 calib_source = data[1] & 0xf;
2741 if (calib_source > 0xF)
2744 devpriv->ai_calib_source = calib_source;
2745 ni_writew(calib_source, Calibration_Channel_6143);
2747 unsigned int calib_source;
2748 unsigned int calib_source_adjust;
2750 calib_source = data[1] & 0xf;
2751 calib_source_adjust = (data[1] >> 4) & 0xff;
2753 if (calib_source >= 8)
2755 devpriv->ai_calib_source = calib_source;
2756 if (board->reg_type == ni_reg_611x) {
2757 ni_writeb(calib_source_adjust,
2758 Cal_Gain_Select_611x);
2769 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2770 struct comedi_subdevice *s,
2771 struct comedi_insn *insn,
2774 const struct ni_board_struct *board = comedi_board(dev);
2775 struct ni_private *devpriv = dev->private;
2776 unsigned int a, b, modebits;
2780 * data[2] is analog line
2781 * data[3] is set level
2782 * data[4] is reset level */
2783 if (!board->has_analog_trig)
2785 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2786 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2789 if (data[2] >= board->n_adchan) {
2790 data[2] = board->n_adchan - 1;
2793 if (data[3] > 255) { /* a */
2797 if (data[4] > 255) { /* b */
2808 * high mode 00 00 01 10
2809 * low mode 00 00 10 01
2811 * hysteresis low mode 10 00 00 01
2812 * hysteresis high mode 01 00 00 10
2813 * middle mode 10 01 01 10
2818 modebits = data[1] & 0xff;
2819 if (modebits & 0xf0) {
2820 /* two level mode */
2826 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2828 devpriv->atrig_low = a;
2829 devpriv->atrig_high = b;
2831 case 0x81: /* low hysteresis mode */
2832 devpriv->atrig_mode = 6;
2834 case 0x42: /* high hysteresis mode */
2835 devpriv->atrig_mode = 3;
2837 case 0x96: /* middle window mode */
2838 devpriv->atrig_mode = 2;
2845 /* one level mode */
2851 case 0x06: /* high window mode */
2852 devpriv->atrig_high = a;
2853 devpriv->atrig_mode = 0;
2855 case 0x09: /* low window mode */
2856 devpriv->atrig_low = a;
2857 devpriv->atrig_mode = 1;
2869 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2870 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2871 void *data, unsigned int num_bytes,
2872 unsigned int chan_index)
2874 const struct ni_board_struct *board = comedi_board(dev);
2875 struct comedi_async *async = s->async;
2878 unsigned int offset;
2879 unsigned int length = num_bytes / sizeof(short);
2880 short *array = data;
2882 offset = 1 << (board->aobits - 1);
2883 for (i = 0; i < length; i++) {
2884 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2885 if (board->ao_unipolar == 0 || (range & 1) == 0)
2888 array[i] = cpu_to_le16(array[i]);
2891 chan_index %= async->cmd.chanlist_len;
2895 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2896 struct comedi_subdevice *s,
2897 unsigned int chanspec[],
2898 unsigned int n_chans, int timed)
2900 const struct ni_board_struct *board = comedi_board(dev);
2901 struct ni_private *devpriv = dev->private;
2909 for (i = 0; i < board->n_aochan; ++i) {
2910 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2911 ni_writeb(devpriv->ao_conf[i],
2912 M_Offset_AO_Config_Bank(i));
2913 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2916 for (i = 0; i < n_chans; i++) {
2917 const struct comedi_krange *krange;
2918 chan = CR_CHAN(chanspec[i]);
2919 range = CR_RANGE(chanspec[i]);
2920 krange = s->range_table->range + range;
2923 switch (krange->max - krange->min) {
2925 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2926 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2929 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2930 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2933 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2934 ni_writeb(MSeries_Attenuate_x5_Bit,
2935 M_Offset_AO_Reference_Attenuation(chan));
2938 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2939 ni_writeb(MSeries_Attenuate_x5_Bit,
2940 M_Offset_AO_Reference_Attenuation(chan));
2943 printk("%s: bug! unhandled ao reference voltage\n",
2947 switch (krange->max + krange->min) {
2949 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2952 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2955 printk("%s: bug! unhandled ao offset voltage\n",
2960 conf |= MSeries_AO_Update_Timed_Bit;
2961 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2962 devpriv->ao_conf[chan] = conf;
2963 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2968 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2969 struct comedi_subdevice *s,
2970 unsigned int chanspec[],
2971 unsigned int n_chans)
2973 const struct ni_board_struct *board = comedi_board(dev);
2974 struct ni_private *devpriv = dev->private;
2981 for (i = 0; i < n_chans; i++) {
2982 chan = CR_CHAN(chanspec[i]);
2983 range = CR_RANGE(chanspec[i]);
2984 conf = AO_Channel(chan);
2986 if (board->ao_unipolar) {
2987 if ((range & 1) == 0) {
2989 invert = (1 << (board->aobits - 1));
2997 invert = (1 << (board->aobits - 1));
3000 /* not all boards can deglitch, but this shouldn't hurt */
3001 if (chanspec[i] & CR_DEGLITCH)
3002 conf |= AO_Deglitch;
3004 /* analog reference */
3005 /* AREF_OTHER connects AO ground to AI ground, i think */
3006 conf |= (CR_AREF(chanspec[i]) ==
3007 AREF_OTHER) ? AO_Ground_Ref : 0;
3009 ni_writew(conf, AO_Configuration);
3010 devpriv->ao_conf[chan] = conf;
3015 static int ni_ao_config_chanlist(struct comedi_device *dev,
3016 struct comedi_subdevice *s,
3017 unsigned int chanspec[], unsigned int n_chans,
3020 const struct ni_board_struct *board = comedi_board(dev);
3022 if (board->reg_type & ni_reg_m_series_mask)
3023 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3026 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3029 static int ni_ao_insn_read(struct comedi_device *dev,
3030 struct comedi_subdevice *s, struct comedi_insn *insn,
3033 struct ni_private *devpriv = dev->private;
3035 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3040 static int ni_ao_insn_write(struct comedi_device *dev,
3041 struct comedi_subdevice *s,
3042 struct comedi_insn *insn, unsigned int *data)
3044 const struct ni_board_struct *board = comedi_board(dev);
3045 struct ni_private *devpriv = dev->private;
3046 unsigned int chan = CR_CHAN(insn->chanspec);
3047 unsigned int invert;
3049 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3051 devpriv->ao[chan] = data[0];
3053 if (board->reg_type & ni_reg_m_series_mask) {
3054 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3056 ni_writew(data[0] ^ invert,
3057 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3062 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3063 struct comedi_subdevice *s,
3064 struct comedi_insn *insn, unsigned int *data)
3066 const struct ni_board_struct *board = comedi_board(dev);
3067 struct ni_private *devpriv = dev->private;
3068 unsigned int chan = CR_CHAN(insn->chanspec);
3069 unsigned int invert;
3071 ao_win_out(1 << chan, AO_Immediate_671x);
3072 invert = 1 << (board->aobits - 1);
3074 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3076 devpriv->ao[chan] = data[0];
3077 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3082 static int ni_ao_insn_config(struct comedi_device *dev,
3083 struct comedi_subdevice *s,
3084 struct comedi_insn *insn, unsigned int *data)
3086 const struct ni_board_struct *board = comedi_board(dev);
3087 struct ni_private *devpriv = dev->private;
3090 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3093 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3095 data[2] += devpriv->mite->fifo_size;
3112 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3113 unsigned int trignum)
3115 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3116 struct ni_private *devpriv = dev->private;
3118 int interrupt_b_bits;
3120 static const int timeout = 1000;
3125 /* Null trig at beginning prevent ao start trigger from executing more than
3126 once per command (and doing things like trying to allocate the ao dma channel
3128 s->async->inttrig = NULL;
3130 ni_set_bits(dev, Interrupt_B_Enable_Register,
3131 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3132 interrupt_b_bits = AO_Error_Interrupt_Enable;
3134 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3135 if (board->reg_type & ni_reg_6xxx_mask)
3136 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3137 ret = ni_ao_setup_MITE_dma(dev);
3140 ret = ni_ao_wait_for_dma_load(dev);
3144 ret = ni_ao_prep_fifo(dev, s);
3148 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3151 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3152 AO_Mode_3_Register);
3153 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3154 /* wait for DACs to be loaded */
3155 for (i = 0; i < timeout; i++) {
3157 if ((devpriv->stc_readw(dev,
3158 Joint_Status_2_Register) &
3159 AO_TMRDACWRs_In_Progress_St) == 0)
3164 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3167 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3168 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3169 Interrupt_B_Ack_Register);
3171 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3173 devpriv->stc_writew(dev,
3174 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3175 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3176 AO_Command_1_Register);
3178 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3179 AO_Command_2_Register);
3184 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3186 const struct ni_board_struct *board = comedi_board(dev);
3187 struct ni_private *devpriv = dev->private;
3188 const struct comedi_cmd *cmd = &s->async->cmd;
3193 if (dev->irq == 0) {
3194 comedi_error(dev, "cannot run command without an irq");
3198 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3200 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3202 if (board->reg_type & ni_reg_6xxx_mask) {
3203 ao_win_out(CLEAR_WG, AO_Misc_611x);
3206 for (i = 0; i < cmd->chanlist_len; i++) {
3209 chan = CR_CHAN(cmd->chanlist[i]);
3211 ao_win_out(chan, AO_Waveform_Generation_611x);
3213 ao_win_out(bits, AO_Timed_611x);
3216 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3218 if (cmd->stop_src == TRIG_NONE) {
3219 devpriv->ao_mode1 |= AO_Continuous;
3220 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3222 devpriv->ao_mode1 &= ~AO_Continuous;
3223 devpriv->ao_mode1 |= AO_Trigger_Once;
3225 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3226 switch (cmd->start_src) {
3229 devpriv->ao_trigger_select &=
3230 ~(AO_START1_Polarity | AO_START1_Select(-1));
3231 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3232 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3233 AO_Trigger_Select_Register);
3236 devpriv->ao_trigger_select =
3237 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3238 if (cmd->start_arg & CR_INVERT)
3239 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3240 if (cmd->start_arg & CR_EDGE)
3241 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3242 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3243 AO_Trigger_Select_Register);
3249 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3250 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3252 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3253 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3254 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3255 if (cmd->stop_src == TRIG_NONE) {
3256 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3258 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3260 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3261 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3262 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3263 switch (cmd->stop_src) {
3265 if (board->reg_type & ni_reg_m_series_mask) {
3266 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3267 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3268 AO_UC_Load_A_Register);
3269 devpriv->stc_writew(dev, AO_UC_Load,
3270 AO_Command_1_Register);
3272 devpriv->stc_writel(dev, cmd->stop_arg,
3273 AO_UC_Load_A_Register);
3274 devpriv->stc_writew(dev, AO_UC_Load,
3275 AO_Command_1_Register);
3276 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3277 AO_UC_Load_A_Register);
3281 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3282 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3283 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3286 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3287 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3288 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3291 devpriv->ao_mode1 &=
3292 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3293 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3294 switch (cmd->scan_begin_src) {
3296 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3298 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3299 TRIG_ROUND_NEAREST);
3300 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3301 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3302 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3305 devpriv->ao_mode1 |=
3306 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3307 if (cmd->scan_begin_arg & CR_INVERT)
3308 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3309 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3315 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3316 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3317 devpriv->ao_mode2 &=
3318 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3319 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3321 if (cmd->scan_end_arg > 1) {
3322 devpriv->ao_mode1 |= AO_Multiple_Channels;
3323 devpriv->stc_writew(dev,
3324 AO_Number_Of_Channels(cmd->scan_end_arg -
3326 AO_UPDATE_Output_Select
3327 (AO_Update_Output_High_Z),
3328 AO_Output_Control_Register);
3331 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3332 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3333 if (board->reg_type &
3334 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3335 bits |= AO_Number_Of_Channels(0);
3338 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3340 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3342 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3344 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3345 AO_Command_1_Register);
3347 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3348 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3350 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3352 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3354 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3356 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3357 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3359 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3360 AO_TMRDACWR_Pulse_Width;
3361 if (board->ao_fifo_depth)
3362 bits |= AO_FIFO_Enable;
3364 bits |= AO_DMA_PIO_Control;
3366 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3367 verified with bus analyzer. */
3368 if (board->reg_type & ni_reg_m_series_mask)
3369 bits |= AO_Number_Of_DAC_Packages;
3371 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3372 /* enable sending of ao dma requests */
3373 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3375 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3377 if (cmd->stop_src == TRIG_COUNT) {
3378 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3379 Interrupt_B_Ack_Register);
3380 ni_set_bits(dev, Interrupt_B_Enable_Register,
3381 AO_BC_TC_Interrupt_Enable, 1);
3384 s->async->inttrig = &ni_ao_inttrig;
3389 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3390 struct comedi_cmd *cmd)
3392 const struct ni_board_struct *board = comedi_board(dev);
3393 struct ni_private *devpriv = dev->private;
3397 /* Step 1 : check if triggers are trivially valid */
3399 if ((cmd->flags & CMDF_WRITE) == 0)
3400 cmd->flags |= CMDF_WRITE;
3402 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3403 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3404 TRIG_TIMER | TRIG_EXT);
3405 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3406 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3407 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3412 /* Step 2a : make sure trigger sources are unique */
3414 err |= cfc_check_trigger_is_unique(cmd->start_src);
3415 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3416 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3418 /* Step 2b : and mutually compatible */
3423 /* Step 3: check if arguments are trivially valid */
3425 if (cmd->start_src == TRIG_EXT) {
3426 /* external trigger */
3427 unsigned int tmp = CR_CHAN(cmd->start_arg);
3431 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3432 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3434 /* true for both TRIG_NOW and TRIG_INT */
3435 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3438 if (cmd->scan_begin_src == TRIG_TIMER) {
3439 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3441 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3442 devpriv->clock_ns * 0xffffff);
3445 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3446 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3448 if (cmd->stop_src == TRIG_COUNT)
3449 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3450 else /* TRIG_NONE */
3451 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3456 /* step 4: fix up any arguments */
3457 if (cmd->scan_begin_src == TRIG_TIMER) {
3458 tmp = cmd->scan_begin_arg;
3459 cmd->scan_begin_arg =
3460 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3461 cmd->scan_begin_arg,
3465 if (tmp != cmd->scan_begin_arg)
3471 /* step 5: fix up chanlist */
3479 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3481 const struct ni_board_struct *board = comedi_board(dev);
3482 struct ni_private *devpriv = dev->private;
3484 /* devpriv->ao0p=0x0000; */
3485 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3487 /* devpriv->ao1p=AO_Channel(1); */
3488 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3490 ni_release_ao_mite_channel(dev);
3492 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3493 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3494 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3495 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3496 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3497 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3498 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3499 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3500 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3501 devpriv->ao_cmd1 = 0;
3502 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3503 devpriv->ao_cmd2 = 0;
3504 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3505 devpriv->ao_mode1 = 0;
3506 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3507 devpriv->ao_mode2 = 0;
3508 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3509 if (board->reg_type & ni_reg_m_series_mask)
3510 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3512 devpriv->ao_mode3 = 0;
3513 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3514 devpriv->ao_trigger_select = 0;
3515 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3516 AO_Trigger_Select_Register);
3517 if (board->reg_type & ni_reg_6xxx_mask) {
3518 unsigned immediate_bits = 0;
3520 for (i = 0; i < s->n_chan; ++i) {
3521 immediate_bits |= 1 << i;
3523 ao_win_out(immediate_bits, AO_Immediate_671x);
3524 ao_win_out(CLEAR_WG, AO_Misc_611x);
3526 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3533 static int ni_dio_insn_config(struct comedi_device *dev,
3534 struct comedi_subdevice *s,
3535 struct comedi_insn *insn, unsigned int *data)
3537 struct ni_private *devpriv = dev->private;
3540 printk("ni_dio_insn_config() chan=%d io=%d\n",
3541 CR_CHAN(insn->chanspec), data[0]);
3544 case INSN_CONFIG_DIO_OUTPUT:
3545 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3547 case INSN_CONFIG_DIO_INPUT:
3548 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3550 case INSN_CONFIG_DIO_QUERY:
3553 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3561 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3562 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3563 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3568 static int ni_dio_insn_bits(struct comedi_device *dev,
3569 struct comedi_subdevice *s,
3570 struct comedi_insn *insn, unsigned int *data)
3572 struct ni_private *devpriv = dev->private;
3575 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3579 /* Perform check to make sure we're not using the
3580 serial part of the dio */
3581 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3582 && devpriv->serial_interval_ns)
3585 s->state &= ~data[0];
3586 s->state |= (data[0] & data[1]);
3587 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3588 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3589 devpriv->stc_writew(dev, devpriv->dio_output,
3590 DIO_Output_Register);
3592 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3597 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3598 struct comedi_subdevice *s,
3599 struct comedi_insn *insn,
3602 struct ni_private *devpriv __maybe_unused = dev->private;
3605 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3606 CR_CHAN(insn->chanspec), data[0]);
3609 case INSN_CONFIG_DIO_OUTPUT:
3610 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3612 case INSN_CONFIG_DIO_INPUT:
3613 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3615 case INSN_CONFIG_DIO_QUERY:
3618 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3626 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3631 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3632 struct comedi_subdevice *s,
3633 struct comedi_insn *insn,
3636 struct ni_private *devpriv __maybe_unused = dev->private;
3639 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3644 s->state &= ~data[0];
3645 s->state |= (data[0] & data[1]);
3646 ni_writel(s->state, M_Offset_Static_Digital_Output);
3648 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3653 static int ni_cdio_cmdtest(struct comedi_device *dev,
3654 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3660 /* Step 1 : check if triggers are trivially valid */
3662 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3663 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3664 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3665 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3666 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3671 /* Step 2a : make sure trigger sources are unique */
3672 /* Step 2b : and mutually compatible */
3677 /* Step 3: check if arguments are trivially valid */
3679 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3681 tmp = cmd->scan_begin_arg;
3682 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3683 if (tmp != cmd->scan_begin_arg)
3686 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3687 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3688 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3693 /* step 4: fix up any arguments */
3698 /* step 5: check chanlist */
3700 for (i = 0; i < cmd->chanlist_len; ++i) {
3701 if (cmd->chanlist[i] != i)
3711 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3713 struct ni_private *devpriv __maybe_unused = dev->private;
3714 const struct comedi_cmd *cmd = &s->async->cmd;
3715 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3718 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3719 switch (cmd->scan_begin_src) {
3722 CR_CHAN(cmd->scan_begin_arg) &
3723 CDO_Sample_Source_Select_Mask;
3729 if (cmd->scan_begin_arg & CR_INVERT)
3730 cdo_mode_bits |= CDO_Polarity_Bit;
3731 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3733 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3734 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3735 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3738 "attempted to run digital output command with no lines configured as outputs");
3741 retval = ni_request_cdo_mite_channel(dev);
3745 s->async->inttrig = &ni_cdo_inttrig;
3749 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3750 unsigned int trignum)
3753 struct ni_private *devpriv = dev->private;
3754 unsigned long flags;
3758 const unsigned timeout = 1000;
3760 s->async->inttrig = NULL;
3762 /* read alloc the entire buffer */
3763 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3766 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3767 if (devpriv->cdo_mite_chan) {
3768 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3769 mite_dma_arm(devpriv->cdo_mite_chan);
3771 comedi_error(dev, "BUG: no cdo mite channel?");
3774 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3779 * XXX not sure what interrupt C group does
3780 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3781 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3783 for (i = 0; i < timeout; ++i) {
3784 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3789 comedi_error(dev, "dma failed to fill cdo fifo!");
3790 ni_cdio_cancel(dev, s);
3793 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3794 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3795 M_Offset_CDIO_Command);
3799 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3801 struct ni_private *devpriv __maybe_unused = dev->private;
3803 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3804 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3805 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3806 M_Offset_CDIO_Command);
3808 * XXX not sure what interrupt C group does ni_writeb(0,
3809 * M_Offset_Interrupt_C_Enable);
3811 ni_writel(0, M_Offset_CDO_Mask_Enable);
3812 ni_release_cdo_mite_channel(dev);
3816 static void handle_cdio_interrupt(struct comedi_device *dev)
3818 const struct ni_board_struct *board = comedi_board(dev);
3819 struct ni_private *devpriv __maybe_unused = dev->private;
3820 unsigned cdio_status;
3821 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3823 unsigned long flags;
3826 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3830 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3831 if (devpriv->cdo_mite_chan) {
3832 unsigned cdo_mite_status =
3833 mite_get_status(devpriv->cdo_mite_chan);
3834 if (cdo_mite_status & CHSR_LINKC) {
3836 devpriv->mite->mite_io_addr +
3837 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3839 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3841 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3844 cdio_status = ni_readl(M_Offset_CDIO_Status);
3845 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3846 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3847 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3848 s->async->events |= COMEDI_CB_OVERFLOW;
3850 if (cdio_status & CDO_FIFO_Empty_Bit) {
3851 /* printk("cdio fifo empty\n"); */
3852 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3853 M_Offset_CDIO_Command);
3854 /* s->async->events |= COMEDI_CB_EOA; */
3859 static int ni_serial_insn_config(struct comedi_device *dev,
3860 struct comedi_subdevice *s,
3861 struct comedi_insn *insn, unsigned int *data)
3863 struct ni_private *devpriv = dev->private;
3865 unsigned char byte_out, byte_in = 0;
3871 case INSN_CONFIG_SERIAL_CLOCK:
3874 printk("SPI serial clock Config cd\n", data[1]);
3876 devpriv->serial_hw_mode = 1;
3877 devpriv->dio_control |= DIO_HW_Serial_Enable;
3879 if (data[1] == SERIAL_DISABLED) {
3880 devpriv->serial_hw_mode = 0;
3881 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3882 DIO_Software_Serial_Control);
3883 data[1] = SERIAL_DISABLED;
3884 devpriv->serial_interval_ns = data[1];
3885 } else if (data[1] <= SERIAL_600NS) {
3886 /* Warning: this clock speed is too fast to reliably
3888 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3889 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3890 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3891 data[1] = SERIAL_600NS;
3892 devpriv->serial_interval_ns = data[1];
3893 } else if (data[1] <= SERIAL_1_2US) {
3894 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3895 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3896 DIO_Serial_Out_Divide_By_2;
3897 data[1] = SERIAL_1_2US;
3898 devpriv->serial_interval_ns = data[1];
3899 } else if (data[1] <= SERIAL_10US) {
3900 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3901 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3902 DIO_Serial_Out_Divide_By_2;
3903 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3904 600ns/1.2us. If you turn divide_by_2 off with the
3905 slow clock, you will still get 10us, except then
3906 all your delays are wrong. */
3907 data[1] = SERIAL_10US;
3908 devpriv->serial_interval_ns = data[1];
3910 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3911 DIO_Software_Serial_Control);
3912 devpriv->serial_hw_mode = 0;
3913 data[1] = (data[1] / 1000) * 1000;
3914 devpriv->serial_interval_ns = data[1];
3917 devpriv->stc_writew(dev, devpriv->dio_control,
3918 DIO_Control_Register);
3919 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3920 Clock_and_FOUT_Register);
3925 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3927 if (devpriv->serial_interval_ns == 0) {
3931 byte_out = data[1] & 0xFF;
3933 if (devpriv->serial_hw_mode) {
3934 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3936 } else if (devpriv->serial_interval_ns > 0) {
3937 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3940 printk("ni_serial_insn_config: serial disabled!\n");
3945 data[1] = byte_in & 0xFF;
3955 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3956 struct comedi_subdevice *s,
3957 unsigned char data_out,
3958 unsigned char *data_in)
3960 struct ni_private *devpriv = dev->private;
3961 unsigned int status1;
3962 int err = 0, count = 20;
3965 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3968 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3969 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3970 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3972 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3973 if (status1 & DIO_Serial_IO_In_Progress_St) {
3978 devpriv->dio_control |= DIO_HW_Serial_Start;
3979 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3980 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3982 /* Wait until STC says we're done, but don't loop infinitely. */
3984 devpriv->stc_readw(dev,
3985 Joint_Status_1_Register)) &
3986 DIO_Serial_IO_In_Progress_St) {
3987 /* Delay one bit per loop */
3988 udelay((devpriv->serial_interval_ns + 999) / 1000);
3991 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3997 /* Delay for last bit. This delay is absolutely necessary, because
3998 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3999 udelay((devpriv->serial_interval_ns + 999) / 1000);
4001 if (data_in != NULL) {
4002 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4004 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4009 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4014 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4015 struct comedi_subdevice *s,
4016 unsigned char data_out,
4017 unsigned char *data_in)
4019 struct ni_private *devpriv = dev->private;
4020 unsigned char mask, input = 0;
4023 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4026 /* Wait for one bit before transfer */
4027 udelay((devpriv->serial_interval_ns + 999) / 1000);
4029 for (mask = 0x80; mask; mask >>= 1) {
4030 /* Output current bit; note that we cannot touch s->state
4031 because it is a per-subdevice field, and serial is
4032 a separate subdevice from DIO. */
4033 devpriv->dio_output &= ~DIO_SDOUT;
4034 if (data_out & mask) {
4035 devpriv->dio_output |= DIO_SDOUT;
4037 devpriv->stc_writew(dev, devpriv->dio_output,
4038 DIO_Output_Register);
4040 /* Assert SDCLK (active low, inverted), wait for half of
4041 the delay, deassert SDCLK, and wait for the other half. */
4042 devpriv->dio_control |= DIO_Software_Serial_Control;
4043 devpriv->stc_writew(dev, devpriv->dio_control,
4044 DIO_Control_Register);
4046 udelay((devpriv->serial_interval_ns + 999) / 2000);
4048 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4049 devpriv->stc_writew(dev, devpriv->dio_control,
4050 DIO_Control_Register);
4052 udelay((devpriv->serial_interval_ns + 999) / 2000);
4054 /* Input current bit */
4055 if (devpriv->stc_readw(dev,
4056 DIO_Parallel_Input_Register) & DIO_SDIN)
4058 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4063 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4071 static void mio_common_detach(struct comedi_device *dev)
4073 struct ni_private *devpriv = dev->private;
4076 if (devpriv->counter_dev) {
4077 ni_gpct_device_destroy(devpriv->counter_dev);
4080 comedi_spriv_free(dev, NI_8255_DIO_SUBDEV);
4083 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4087 for (i = 0; i < s->n_chan; i++) {
4088 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4089 AO_Configuration_2_67xx);
4091 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4094 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4096 unsigned stc_register;
4098 case NITIO_G0_Autoincrement_Reg:
4099 stc_register = G_Autoincrement_Register(0);
4101 case NITIO_G1_Autoincrement_Reg:
4102 stc_register = G_Autoincrement_Register(1);
4104 case NITIO_G0_Command_Reg:
4105 stc_register = G_Command_Register(0);
4107 case NITIO_G1_Command_Reg:
4108 stc_register = G_Command_Register(1);
4110 case NITIO_G0_HW_Save_Reg:
4111 stc_register = G_HW_Save_Register(0);
4113 case NITIO_G1_HW_Save_Reg:
4114 stc_register = G_HW_Save_Register(1);
4116 case NITIO_G0_SW_Save_Reg:
4117 stc_register = G_Save_Register(0);
4119 case NITIO_G1_SW_Save_Reg:
4120 stc_register = G_Save_Register(1);
4122 case NITIO_G0_Mode_Reg:
4123 stc_register = G_Mode_Register(0);
4125 case NITIO_G1_Mode_Reg:
4126 stc_register = G_Mode_Register(1);
4128 case NITIO_G0_LoadA_Reg:
4129 stc_register = G_Load_A_Register(0);
4131 case NITIO_G1_LoadA_Reg:
4132 stc_register = G_Load_A_Register(1);
4134 case NITIO_G0_LoadB_Reg:
4135 stc_register = G_Load_B_Register(0);
4137 case NITIO_G1_LoadB_Reg:
4138 stc_register = G_Load_B_Register(1);
4140 case NITIO_G0_Input_Select_Reg:
4141 stc_register = G_Input_Select_Register(0);
4143 case NITIO_G1_Input_Select_Reg:
4144 stc_register = G_Input_Select_Register(1);
4146 case NITIO_G01_Status_Reg:
4147 stc_register = G_Status_Register;
4149 case NITIO_G01_Joint_Reset_Reg:
4150 stc_register = Joint_Reset_Register;
4152 case NITIO_G01_Joint_Status1_Reg:
4153 stc_register = Joint_Status_1_Register;
4155 case NITIO_G01_Joint_Status2_Reg:
4156 stc_register = Joint_Status_2_Register;
4158 case NITIO_G0_Interrupt_Acknowledge_Reg:
4159 stc_register = Interrupt_A_Ack_Register;
4161 case NITIO_G1_Interrupt_Acknowledge_Reg:
4162 stc_register = Interrupt_B_Ack_Register;
4164 case NITIO_G0_Status_Reg:
4165 stc_register = AI_Status_1_Register;
4167 case NITIO_G1_Status_Reg:
4168 stc_register = AO_Status_1_Register;
4170 case NITIO_G0_Interrupt_Enable_Reg:
4171 stc_register = Interrupt_A_Enable_Register;
4173 case NITIO_G1_Interrupt_Enable_Reg:
4174 stc_register = Interrupt_B_Enable_Register;
4177 printk("%s: unhandled register 0x%x in switch.\n",
4183 return stc_register;
4186 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4187 enum ni_gpct_register reg)
4189 struct comedi_device *dev = counter->counter_dev->dev;
4190 struct ni_private *devpriv = dev->private;
4191 unsigned stc_register;
4192 /* bits in the join reset register which are relevant to counters */
4193 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4194 static const unsigned gpct_interrupt_a_enable_mask =
4195 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4196 static const unsigned gpct_interrupt_b_enable_mask =
4197 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4200 /* m-series-only registers */
4201 case NITIO_G0_Counting_Mode_Reg:
4202 ni_writew(bits, M_Offset_G0_Counting_Mode);
4204 case NITIO_G1_Counting_Mode_Reg:
4205 ni_writew(bits, M_Offset_G1_Counting_Mode);
4207 case NITIO_G0_Second_Gate_Reg:
4208 ni_writew(bits, M_Offset_G0_Second_Gate);
4210 case NITIO_G1_Second_Gate_Reg:
4211 ni_writew(bits, M_Offset_G1_Second_Gate);
4213 case NITIO_G0_DMA_Config_Reg:
4214 ni_writew(bits, M_Offset_G0_DMA_Config);
4216 case NITIO_G1_DMA_Config_Reg:
4217 ni_writew(bits, M_Offset_G1_DMA_Config);
4219 case NITIO_G0_ABZ_Reg:
4220 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4222 case NITIO_G1_ABZ_Reg:
4223 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4226 /* 32 bit registers */
4227 case NITIO_G0_LoadA_Reg:
4228 case NITIO_G1_LoadA_Reg:
4229 case NITIO_G0_LoadB_Reg:
4230 case NITIO_G1_LoadB_Reg:
4231 stc_register = ni_gpct_to_stc_register(reg);
4232 devpriv->stc_writel(dev, bits, stc_register);
4235 /* 16 bit registers */
4236 case NITIO_G0_Interrupt_Enable_Reg:
4237 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4238 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4239 gpct_interrupt_a_enable_mask, bits);
4241 case NITIO_G1_Interrupt_Enable_Reg:
4242 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4243 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4244 gpct_interrupt_b_enable_mask, bits);
4246 case NITIO_G01_Joint_Reset_Reg:
4247 BUG_ON(bits & ~gpct_joint_reset_mask);
4250 stc_register = ni_gpct_to_stc_register(reg);
4251 devpriv->stc_writew(dev, bits, stc_register);
4255 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4256 enum ni_gpct_register reg)
4258 struct comedi_device *dev = counter->counter_dev->dev;
4259 struct ni_private *devpriv = dev->private;
4260 unsigned stc_register;
4263 /* m-series only registers */
4264 case NITIO_G0_DMA_Status_Reg:
4265 return ni_readw(M_Offset_G0_DMA_Status);
4267 case NITIO_G1_DMA_Status_Reg:
4268 return ni_readw(M_Offset_G1_DMA_Status);
4271 /* 32 bit registers */
4272 case NITIO_G0_HW_Save_Reg:
4273 case NITIO_G1_HW_Save_Reg:
4274 case NITIO_G0_SW_Save_Reg:
4275 case NITIO_G1_SW_Save_Reg:
4276 stc_register = ni_gpct_to_stc_register(reg);
4277 return devpriv->stc_readl(dev, stc_register);
4280 /* 16 bit registers */
4282 stc_register = ni_gpct_to_stc_register(reg);
4283 return devpriv->stc_readw(dev, stc_register);
4289 static int ni_freq_out_insn_read(struct comedi_device *dev,
4290 struct comedi_subdevice *s,
4291 struct comedi_insn *insn, unsigned int *data)
4293 struct ni_private *devpriv = dev->private;
4295 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4299 static int ni_freq_out_insn_write(struct comedi_device *dev,
4300 struct comedi_subdevice *s,
4301 struct comedi_insn *insn, unsigned int *data)
4303 struct ni_private *devpriv = dev->private;
4305 devpriv->clock_and_fout &= ~FOUT_Enable;
4306 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4307 Clock_and_FOUT_Register);
4308 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4309 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4310 devpriv->clock_and_fout |= FOUT_Enable;
4311 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4312 Clock_and_FOUT_Register);
4316 static int ni_set_freq_out_clock(struct comedi_device *dev,
4317 unsigned int clock_source)
4319 struct ni_private *devpriv = dev->private;
4321 switch (clock_source) {
4322 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4323 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4325 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4326 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4331 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4332 Clock_and_FOUT_Register);
4336 static void ni_get_freq_out_clock(struct comedi_device *dev,
4337 unsigned int *clock_source,
4338 unsigned int *clock_period_ns)
4340 struct ni_private *devpriv = dev->private;
4342 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4343 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4344 *clock_period_ns = TIMEBASE_2_NS;
4346 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4347 *clock_period_ns = TIMEBASE_1_NS * 2;
4351 static int ni_freq_out_insn_config(struct comedi_device *dev,
4352 struct comedi_subdevice *s,
4353 struct comedi_insn *insn, unsigned int *data)
4356 case INSN_CONFIG_SET_CLOCK_SRC:
4357 return ni_set_freq_out_clock(dev, data[1]);
4359 case INSN_CONFIG_GET_CLOCK_SRC:
4360 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4368 static int ni_alloc_private(struct comedi_device *dev)
4370 struct ni_private *devpriv;
4372 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4375 dev->private = devpriv;
4377 spin_lock_init(&devpriv->window_lock);
4378 spin_lock_init(&devpriv->soft_reg_copy_lock);
4379 spin_lock_init(&devpriv->mite_channel_lock);
4384 static int ni_E_init(struct comedi_device *dev)
4386 const struct ni_board_struct *board = comedi_board(dev);
4387 struct ni_private *devpriv = dev->private;
4388 struct comedi_subdevice *s;
4390 enum ni_gpct_variant counter_variant;
4393 if (board->n_aochan > MAX_N_AO_CHAN) {
4394 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4398 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4402 /* analog input subdevice */
4404 s = &dev->subdevices[NI_AI_SUBDEV];
4405 dev->read_subdev = s;
4406 if (board->n_adchan) {
4407 s->type = COMEDI_SUBD_AI;
4409 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4410 if (board->reg_type != ni_reg_611x)
4411 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4412 if (board->adbits > 16)
4413 s->subdev_flags |= SDF_LSAMPL;
4414 if (board->reg_type & ni_reg_m_series_mask)
4415 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4416 s->n_chan = board->n_adchan;
4417 s->len_chanlist = 512;
4418 s->maxdata = (1 << board->adbits) - 1;
4419 s->range_table = ni_range_lkup[board->gainlkup];
4420 s->insn_read = &ni_ai_insn_read;
4421 s->insn_config = &ni_ai_insn_config;
4422 s->do_cmdtest = &ni_ai_cmdtest;
4423 s->do_cmd = &ni_ai_cmd;
4424 s->cancel = &ni_ai_reset;
4425 s->poll = &ni_ai_poll;
4426 s->munge = &ni_ai_munge;
4428 s->async_dma_dir = DMA_FROM_DEVICE;
4431 s->type = COMEDI_SUBD_UNUSED;
4434 /* analog output subdevice */
4436 s = &dev->subdevices[NI_AO_SUBDEV];
4437 if (board->n_aochan) {
4438 s->type = COMEDI_SUBD_AO;
4439 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4440 if (board->reg_type & ni_reg_m_series_mask)
4441 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4442 s->n_chan = board->n_aochan;
4443 s->maxdata = (1 << board->aobits) - 1;
4444 s->range_table = board->ao_range_table;
4445 s->insn_read = &ni_ao_insn_read;
4446 if (board->reg_type & ni_reg_6xxx_mask) {
4447 s->insn_write = &ni_ao_insn_write_671x;
4449 s->insn_write = &ni_ao_insn_write;
4451 s->insn_config = &ni_ao_insn_config;
4453 if (board->n_aochan) {
4454 s->async_dma_dir = DMA_TO_DEVICE;
4456 if (board->ao_fifo_depth) {
4458 dev->write_subdev = s;
4459 s->subdev_flags |= SDF_CMD_WRITE;
4460 s->do_cmd = &ni_ao_cmd;
4461 s->do_cmdtest = &ni_ao_cmdtest;
4462 s->len_chanlist = board->n_aochan;
4463 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4464 s->munge = ni_ao_munge;
4466 s->cancel = &ni_ao_reset;
4468 s->type = COMEDI_SUBD_UNUSED;
4470 if ((board->reg_type & ni_reg_67xx_mask))
4471 init_ao_67xx(dev, s);
4473 /* digital i/o subdevice */
4475 s = &dev->subdevices[NI_DIO_SUBDEV];
4476 s->type = COMEDI_SUBD_DIO;
4477 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4479 s->io_bits = 0; /* all bits input */
4480 s->range_table = &range_digital;
4481 s->n_chan = board->num_p0_dio_channels;
4482 if (board->reg_type & ni_reg_m_series_mask) {
4484 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4485 s->insn_bits = &ni_m_series_dio_insn_bits;
4486 s->insn_config = &ni_m_series_dio_insn_config;
4487 s->do_cmd = &ni_cdio_cmd;
4488 s->do_cmdtest = &ni_cdio_cmdtest;
4489 s->cancel = &ni_cdio_cancel;
4490 s->async_dma_dir = DMA_BIDIRECTIONAL;
4491 s->len_chanlist = s->n_chan;
4493 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4494 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4496 s->insn_bits = &ni_dio_insn_bits;
4497 s->insn_config = &ni_dio_insn_config;
4498 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4499 ni_writew(devpriv->dio_control, DIO_Control_Register);
4503 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4504 if (board->has_8255) {
4505 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4507 s->type = COMEDI_SUBD_UNUSED;
4510 /* formerly general purpose counter/timer device, but no longer used */
4511 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4512 s->type = COMEDI_SUBD_UNUSED;
4514 /* calibration subdevice -- ai and ao */
4515 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4516 s->type = COMEDI_SUBD_CALIB;
4517 if (board->reg_type & ni_reg_m_series_mask) {
4518 /* internal PWM analog output used for AI nonlinearity calibration */
4519 s->subdev_flags = SDF_INTERNAL;
4520 s->insn_config = &ni_m_series_pwm_config;
4523 ni_writel(0x0, M_Offset_Cal_PWM);
4524 } else if (board->reg_type == ni_reg_6143) {
4525 /* internal PWM analog output used for AI nonlinearity calibration */
4526 s->subdev_flags = SDF_INTERNAL;
4527 s->insn_config = &ni_6143_pwm_config;
4531 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4532 s->insn_read = &ni_calib_insn_read;
4533 s->insn_write = &ni_calib_insn_write;
4534 caldac_setup(dev, s);
4538 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4539 s->type = COMEDI_SUBD_MEMORY;
4540 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4542 if (board->reg_type & ni_reg_m_series_mask) {
4543 s->n_chan = M_SERIES_EEPROM_SIZE;
4544 s->insn_read = &ni_m_series_eeprom_insn_read;
4547 s->insn_read = &ni_eeprom_insn_read;
4551 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4552 s->type = COMEDI_SUBD_DIO;
4553 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4554 if (board->reg_type & ni_reg_m_series_mask) {
4557 ni_writew(s->state, M_Offset_PFI_DO);
4558 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4559 ni_writew(devpriv->pfi_output_select_reg[i],
4560 M_Offset_PFI_Output_Select(i + 1));
4566 if (board->reg_type & ni_reg_m_series_mask) {
4567 s->insn_bits = &ni_pfi_insn_bits;
4569 s->insn_config = &ni_pfi_insn_config;
4570 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4572 /* cs5529 calibration adc */
4573 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4574 if (board->reg_type & ni_reg_67xx_mask) {
4575 s->type = COMEDI_SUBD_AI;
4576 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4577 /* one channel for each analog output channel */
4578 s->n_chan = board->n_aochan;
4579 s->maxdata = (1 << 16) - 1;
4580 s->range_table = &range_unknown; /* XXX */
4581 s->insn_read = cs5529_ai_insn_read;
4582 s->insn_config = NULL;
4585 s->type = COMEDI_SUBD_UNUSED;
4589 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4590 s->type = COMEDI_SUBD_SERIAL;
4591 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4594 s->insn_config = ni_serial_insn_config;
4595 devpriv->serial_interval_ns = 0;
4596 devpriv->serial_hw_mode = 0;
4599 s = &dev->subdevices[NI_RTSI_SUBDEV];
4600 s->type = COMEDI_SUBD_DIO;
4601 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4604 s->insn_bits = ni_rtsi_insn_bits;
4605 s->insn_config = ni_rtsi_insn_config;
4608 if (board->reg_type & ni_reg_m_series_mask) {
4609 counter_variant = ni_gpct_variant_m_series;
4611 counter_variant = ni_gpct_variant_e_series;
4613 devpriv->counter_dev = ni_gpct_device_construct(dev,
4614 &ni_gpct_write_register,
4615 &ni_gpct_read_register,
4618 /* General purpose counters */
4619 for (j = 0; j < NUM_GPCT; ++j) {
4620 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4621 s->type = COMEDI_SUBD_COUNTER;
4622 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4624 if (board->reg_type & ni_reg_m_series_mask)
4625 s->maxdata = 0xffffffff;
4627 s->maxdata = 0xffffff;
4628 s->insn_read = &ni_gpct_insn_read;
4629 s->insn_write = &ni_gpct_insn_write;
4630 s->insn_config = &ni_gpct_insn_config;
4632 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4633 s->do_cmd = &ni_gpct_cmd;
4634 s->len_chanlist = 1;
4635 s->do_cmdtest = &ni_gpct_cmdtest;
4636 s->cancel = &ni_gpct_cancel;
4637 s->async_dma_dir = DMA_BIDIRECTIONAL;
4639 s->private = &devpriv->counter_dev->counters[j];
4641 devpriv->counter_dev->counters[j].chip_index = 0;
4642 devpriv->counter_dev->counters[j].counter_index = j;
4643 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4646 /* Frequency output */
4647 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4648 s->type = COMEDI_SUBD_COUNTER;
4649 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4652 s->insn_read = &ni_freq_out_insn_read;
4653 s->insn_write = &ni_freq_out_insn_write;
4654 s->insn_config = &ni_freq_out_insn_config;
4656 /* ai configuration */
4657 s = &dev->subdevices[NI_AI_SUBDEV];
4658 ni_ai_reset(dev, s);
4659 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4660 /* BEAM is this needed for PCI-6143 ?? */
4661 devpriv->clock_and_fout =
4662 Slow_Internal_Time_Divide_By_2 |
4663 Slow_Internal_Timebase |
4664 Clock_To_Board_Divide_By_2 |
4666 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4668 devpriv->clock_and_fout =
4669 Slow_Internal_Time_Divide_By_2 |
4670 Slow_Internal_Timebase |
4671 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4673 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4674 Clock_and_FOUT_Register);
4676 /* analog output configuration */
4677 s = &dev->subdevices[NI_AO_SUBDEV];
4678 ni_ao_reset(dev, s);
4681 devpriv->stc_writew(dev,
4682 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4683 0) | (Interrupt_Output_On_3_Pins & 0) |
4684 Interrupt_A_Enable | Interrupt_B_Enable |
4685 Interrupt_A_Output_Select(interrupt_pin
4687 Interrupt_B_Output_Select(interrupt_pin
4689 Interrupt_Control_Register);
4693 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4694 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4696 if (board->reg_type & ni_reg_6xxx_mask) {
4697 ni_writeb(0, Magic_611x);
4698 } else if (board->reg_type & ni_reg_m_series_mask) {
4700 for (channel = 0; channel < board->n_aochan; ++channel) {
4701 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4703 M_Offset_AO_Reference_Attenuation(channel));
4705 ni_writeb(0x0, M_Offset_AO_Calibration);
4712 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4714 struct comedi_device *dev = (struct comedi_device *)arg;
4715 struct ni_private *devpriv __maybe_unused = dev->private;
4718 ni_writeb(data, Port_A + 2 * port);
4721 return ni_readb(Port_A + 2 * port);
4726 presents the EEPROM as a subdevice
4729 static int ni_eeprom_insn_read(struct comedi_device *dev,
4730 struct comedi_subdevice *s,
4731 struct comedi_insn *insn, unsigned int *data)
4733 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4739 reads bytes out of eeprom
4742 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4744 struct ni_private *devpriv __maybe_unused = dev->private;
4748 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4749 ni_writeb(0x04, Serial_Command);
4750 for (bit = 0x8000; bit; bit >>= 1) {
4751 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4753 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4757 for (bit = 0x80; bit; bit >>= 1) {
4758 ni_writeb(0x04, Serial_Command);
4759 ni_writeb(0x05, Serial_Command);
4760 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4762 ni_writeb(0x00, Serial_Command);
4767 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4768 struct comedi_subdevice *s,
4769 struct comedi_insn *insn,
4772 struct ni_private *devpriv = dev->private;
4774 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4779 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4781 struct ni_private *devpriv = dev->private;
4783 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4784 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4788 static int ni_m_series_pwm_config(struct comedi_device *dev,
4789 struct comedi_subdevice *s,
4790 struct comedi_insn *insn, unsigned int *data)
4792 struct ni_private *devpriv = dev->private;
4793 unsigned up_count, down_count;
4796 case INSN_CONFIG_PWM_OUTPUT:
4798 case TRIG_ROUND_NEAREST:
4801 devpriv->clock_ns / 2) / devpriv->clock_ns;
4803 case TRIG_ROUND_DOWN:
4804 up_count = data[2] / devpriv->clock_ns;
4808 (data[2] + devpriv->clock_ns -
4809 1) / devpriv->clock_ns;
4816 case TRIG_ROUND_NEAREST:
4819 devpriv->clock_ns / 2) / devpriv->clock_ns;
4821 case TRIG_ROUND_DOWN:
4822 down_count = data[4] / devpriv->clock_ns;
4826 (data[4] + devpriv->clock_ns -
4827 1) / devpriv->clock_ns;
4833 if (up_count * devpriv->clock_ns != data[2] ||
4834 down_count * devpriv->clock_ns != data[4]) {
4835 data[2] = up_count * devpriv->clock_ns;
4836 data[4] = down_count * devpriv->clock_ns;
4839 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4840 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4842 devpriv->pwm_up_count = up_count;
4843 devpriv->pwm_down_count = down_count;
4846 case INSN_CONFIG_GET_PWM_OUTPUT:
4847 return ni_get_pwm_config(dev, data);
4856 static int ni_6143_pwm_config(struct comedi_device *dev,
4857 struct comedi_subdevice *s,
4858 struct comedi_insn *insn, unsigned int *data)
4860 struct ni_private *devpriv = dev->private;
4861 unsigned up_count, down_count;
4864 case INSN_CONFIG_PWM_OUTPUT:
4866 case TRIG_ROUND_NEAREST:
4869 devpriv->clock_ns / 2) / devpriv->clock_ns;
4871 case TRIG_ROUND_DOWN:
4872 up_count = data[2] / devpriv->clock_ns;
4876 (data[2] + devpriv->clock_ns -
4877 1) / devpriv->clock_ns;
4884 case TRIG_ROUND_NEAREST:
4887 devpriv->clock_ns / 2) / devpriv->clock_ns;
4889 case TRIG_ROUND_DOWN:
4890 down_count = data[4] / devpriv->clock_ns;
4894 (data[4] + devpriv->clock_ns -
4895 1) / devpriv->clock_ns;
4901 if (up_count * devpriv->clock_ns != data[2] ||
4902 down_count * devpriv->clock_ns != data[4]) {
4903 data[2] = up_count * devpriv->clock_ns;
4904 data[4] = down_count * devpriv->clock_ns;
4907 ni_writel(up_count, Calibration_HighTime_6143);
4908 devpriv->pwm_up_count = up_count;
4909 ni_writel(down_count, Calibration_LowTime_6143);
4910 devpriv->pwm_down_count = down_count;
4913 case INSN_CONFIG_GET_PWM_OUTPUT:
4914 return ni_get_pwm_config(dev, data);
4922 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4924 calibration subdevice
4926 static int ni_calib_insn_write(struct comedi_device *dev,
4927 struct comedi_subdevice *s,
4928 struct comedi_insn *insn, unsigned int *data)
4930 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4935 static int ni_calib_insn_read(struct comedi_device *dev,
4936 struct comedi_subdevice *s,
4937 struct comedi_insn *insn, unsigned int *data)
4939 struct ni_private *devpriv = dev->private;
4941 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4946 static int pack_mb88341(int addr, int val, int *bitstring);
4947 static int pack_dac8800(int addr, int val, int *bitstring);
4948 static int pack_dac8043(int addr, int val, int *bitstring);
4949 static int pack_ad8522(int addr, int val, int *bitstring);
4950 static int pack_ad8804(int addr, int val, int *bitstring);
4951 static int pack_ad8842(int addr, int val, int *bitstring);
4953 struct caldac_struct {
4956 int (*packbits) (int, int, int *);
4959 static struct caldac_struct caldacs[] = {
4960 [mb88341] = {12, 8, pack_mb88341},
4961 [dac8800] = {8, 8, pack_dac8800},
4962 [dac8043] = {1, 12, pack_dac8043},
4963 [ad8522] = {2, 12, pack_ad8522},
4964 [ad8804] = {12, 8, pack_ad8804},
4965 [ad8842] = {8, 8, pack_ad8842},
4966 [ad8804_debug] = {16, 8, pack_ad8804},
4969 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4971 const struct ni_board_struct *board = comedi_board(dev);
4972 struct ni_private *devpriv = dev->private;
4981 type = board->caldac[0];
4982 if (type == caldac_none)
4984 n_bits = caldacs[type].n_bits;
4985 for (i = 0; i < 3; i++) {
4986 type = board->caldac[i];
4987 if (type == caldac_none)
4989 if (caldacs[type].n_bits != n_bits)
4991 n_chans += caldacs[type].n_chans;
4994 s->n_chan = n_chans;
4997 unsigned int *maxdata_list;
4999 if (n_chans > MAX_N_CALDACS) {
5000 printk("BUG! MAX_N_CALDACS too small\n");
5002 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5004 for (i = 0; i < n_dacs; i++) {
5005 type = board->caldac[i];
5006 for (j = 0; j < caldacs[type].n_chans; j++) {
5007 maxdata_list[chan] =
5008 (1 << caldacs[type].n_bits) - 1;
5013 for (chan = 0; chan < s->n_chan; chan++)
5014 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5016 type = board->caldac[0];
5017 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5019 for (chan = 0; chan < s->n_chan; chan++)
5020 ni_write_caldac(dev, i, s->maxdata / 2);
5024 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5026 const struct ni_board_struct *board = comedi_board(dev);
5027 struct ni_private *devpriv = dev->private;
5028 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5032 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5033 if (devpriv->caldacs[addr] == val)
5035 devpriv->caldacs[addr] = val;
5037 for (i = 0; i < 3; i++) {
5038 type = board->caldac[i];
5039 if (type == caldac_none)
5041 if (addr < caldacs[type].n_chans) {
5042 bits = caldacs[type].packbits(addr, val, &bitstring);
5043 loadbit = SerDacLd(i);
5044 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5047 addr -= caldacs[type].n_chans;
5050 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5051 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5053 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5056 ni_writeb(loadbit, Serial_Command);
5058 ni_writeb(0, Serial_Command);
5061 static int pack_mb88341(int addr, int val, int *bitstring)
5065 Note that address bits are reversed. Thanks to
5066 Ingo Keen for noticing this.
5068 Note also that the 88341 expects address values from
5069 1-12, whereas we use channel numbers 0-11. The NI
5070 docs use 1-12, also, so be careful here.
5073 *bitstring = ((addr & 0x1) << 11) |
5074 ((addr & 0x2) << 9) |
5075 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5079 static int pack_dac8800(int addr, int val, int *bitstring)
5081 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5085 static int pack_dac8043(int addr, int val, int *bitstring)
5087 *bitstring = val & 0xfff;
5091 static int pack_ad8522(int addr, int val, int *bitstring)
5093 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5097 static int pack_ad8804(int addr, int val, int *bitstring)
5099 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5103 static int pack_ad8842(int addr, int val, int *bitstring)
5105 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5111 * Read the GPCTs current value.
5113 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5115 unsigned int hi1, hi2, lo;
5117 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5118 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5119 G_Command_Register(chan));
5121 devpriv->gpct_command[chan] |= G_Save_Trace;
5122 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5123 G_Command_Register(chan));
5125 /* This procedure is used because the two registers cannot
5126 * be read atomically. */
5128 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5129 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5130 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5131 } while (hi1 != hi2);
5133 return (hi1 << 16) | lo;
5136 static void GPCT_Reset(struct comedi_device *dev, int chan)
5138 int temp_ack_reg = 0;
5140 /* printk("GPCT_Reset..."); */
5141 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5145 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5146 ni_set_bits(dev, Interrupt_A_Enable_Register,
5147 G0_TC_Interrupt_Enable, 0);
5148 ni_set_bits(dev, Interrupt_A_Enable_Register,
5149 G0_Gate_Interrupt_Enable, 0);
5150 temp_ack_reg |= G0_Gate_Error_Confirm;
5151 temp_ack_reg |= G0_TC_Error_Confirm;
5152 temp_ack_reg |= G0_TC_Interrupt_Ack;
5153 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5154 devpriv->stc_writew(dev, temp_ack_reg,
5155 Interrupt_A_Ack_Register);
5157 /* problem...this interferes with the other ctr... */
5158 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5159 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5160 Analog_Trigger_Etc_Register);
5163 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5164 ni_set_bits(dev, Interrupt_B_Enable_Register,
5165 G1_TC_Interrupt_Enable, 0);
5166 ni_set_bits(dev, Interrupt_B_Enable_Register,
5167 G0_Gate_Interrupt_Enable, 0);
5168 temp_ack_reg |= G1_Gate_Error_Confirm;
5169 temp_ack_reg |= G1_TC_Error_Confirm;
5170 temp_ack_reg |= G1_TC_Interrupt_Ack;
5171 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5172 devpriv->stc_writew(dev, temp_ack_reg,
5173 Interrupt_B_Ack_Register);
5175 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5176 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5177 Analog_Trigger_Etc_Register);
5181 devpriv->gpct_mode[chan] = 0;
5182 devpriv->gpct_input_select[chan] = 0;
5183 devpriv->gpct_command[chan] = 0;
5185 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5187 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5188 G_Mode_Register(chan));
5189 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5190 G_Input_Select_Register(chan));
5191 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5193 /* printk("exit GPCT_Reset\n"); */
5198 static int ni_gpct_insn_config(struct comedi_device *dev,
5199 struct comedi_subdevice *s,
5200 struct comedi_insn *insn, unsigned int *data)
5202 struct ni_gpct *counter = s->private;
5203 return ni_tio_insn_config(counter, insn, data);
5206 static int ni_gpct_insn_read(struct comedi_device *dev,
5207 struct comedi_subdevice *s,
5208 struct comedi_insn *insn, unsigned int *data)
5210 struct ni_gpct *counter = s->private;
5211 return ni_tio_rinsn(counter, insn, data);
5214 static int ni_gpct_insn_write(struct comedi_device *dev,
5215 struct comedi_subdevice *s,
5216 struct comedi_insn *insn, unsigned int *data)
5218 struct ni_gpct *counter = s->private;
5219 return ni_tio_winsn(counter, insn, data);
5223 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5226 struct ni_gpct *counter = s->private;
5227 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5229 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5233 "no dma channel available for use by counter");
5236 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5237 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5238 retval = ni_tio_cmd(counter, s->async);
5244 static int ni_gpct_cmdtest(struct comedi_device *dev,
5245 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5247 struct ni_gpct *counter = s->private;
5249 return ni_tio_cmdtest(counter, cmd);
5254 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5257 struct ni_gpct *counter = s->private;
5260 retval = ni_tio_cancel(counter);
5261 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5262 ni_release_gpct_mite_channel(dev, counter->counter_index);
5271 * Programmable Function Inputs
5275 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5278 struct ni_private *devpriv = dev->private;
5279 unsigned pfi_reg_index;
5280 unsigned array_offset;
5282 if ((source & 0x1f) != source)
5284 pfi_reg_index = 1 + chan / 3;
5285 array_offset = pfi_reg_index - 1;
5286 devpriv->pfi_output_select_reg[array_offset] &=
5287 ~MSeries_PFI_Output_Select_Mask(chan);
5288 devpriv->pfi_output_select_reg[array_offset] |=
5289 MSeries_PFI_Output_Select_Bits(chan, source);
5290 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5291 M_Offset_PFI_Output_Select(pfi_reg_index));
5295 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5298 /* pre-m-series boards have fixed signals on pfi pins */
5299 if (source != ni_old_get_pfi_routing(dev, chan))
5304 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5307 const struct ni_board_struct *board = comedi_board(dev);
5309 if (board->reg_type & ni_reg_m_series_mask)
5310 return ni_m_series_set_pfi_routing(dev, chan, source);
5312 return ni_old_set_pfi_routing(dev, chan, source);
5315 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5318 struct ni_private *devpriv = dev->private;
5319 const unsigned array_offset = chan / 3;
5321 return MSeries_PFI_Output_Select_Source(chan,
5323 pfi_output_select_reg
5327 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5329 /* pre-m-series boards have fixed signals on pfi pins */
5332 return NI_PFI_OUTPUT_AI_START1;
5335 return NI_PFI_OUTPUT_AI_START2;
5338 return NI_PFI_OUTPUT_AI_CONVERT;
5341 return NI_PFI_OUTPUT_G_SRC1;
5344 return NI_PFI_OUTPUT_G_GATE1;
5347 return NI_PFI_OUTPUT_AO_UPDATE_N;
5350 return NI_PFI_OUTPUT_AO_START1;
5353 return NI_PFI_OUTPUT_AI_START_PULSE;
5356 return NI_PFI_OUTPUT_G_SRC0;
5359 return NI_PFI_OUTPUT_G_GATE0;
5362 printk("%s: bug, unhandled case in switch.\n", __func__);
5368 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5370 const struct ni_board_struct *board = comedi_board(dev);
5372 if (board->reg_type & ni_reg_m_series_mask)
5373 return ni_m_series_get_pfi_routing(dev, chan);
5375 return ni_old_get_pfi_routing(dev, chan);
5378 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5379 enum ni_pfi_filter_select filter)
5381 const struct ni_board_struct *board = comedi_board(dev);
5382 struct ni_private *devpriv __maybe_unused = dev->private;
5385 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5388 bits = ni_readl(M_Offset_PFI_Filter);
5389 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5390 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5391 ni_writel(bits, M_Offset_PFI_Filter);
5395 static int ni_pfi_insn_bits(struct comedi_device *dev,
5396 struct comedi_subdevice *s,
5397 struct comedi_insn *insn, unsigned int *data)
5399 const struct ni_board_struct *board = comedi_board(dev);
5400 struct ni_private *devpriv __maybe_unused = dev->private;
5402 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5406 s->state &= ~data[0];
5407 s->state |= (data[0] & data[1]);
5408 ni_writew(s->state, M_Offset_PFI_DO);
5410 data[1] = ni_readw(M_Offset_PFI_DI);
5414 static int ni_pfi_insn_config(struct comedi_device *dev,
5415 struct comedi_subdevice *s,
5416 struct comedi_insn *insn, unsigned int *data)
5418 struct ni_private *devpriv = dev->private;
5424 chan = CR_CHAN(insn->chanspec);
5428 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5431 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5433 case INSN_CONFIG_DIO_QUERY:
5435 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5436 COMEDI_OUTPUT : COMEDI_INPUT;
5439 case INSN_CONFIG_SET_ROUTING:
5440 return ni_set_pfi_routing(dev, chan, data[1]);
5442 case INSN_CONFIG_GET_ROUTING:
5443 data[1] = ni_get_pfi_routing(dev, chan);
5445 case INSN_CONFIG_FILTER:
5446 return ni_config_filter(dev, chan, data[1]);
5456 * NI RTSI Bus Functions
5459 static void ni_rtsi_init(struct comedi_device *dev)
5461 const struct ni_board_struct *board = comedi_board(dev);
5462 struct ni_private *devpriv = dev->private;
5464 /* Initialises the RTSI bus signal switch to a default state */
5466 /* Set clock mode to internal */
5467 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5468 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5469 printk("ni_set_master_clock failed, bug?");
5471 /* default internal lines routing to RTSI bus lines */
5472 devpriv->rtsi_trig_a_output_reg =
5473 RTSI_Trig_Output_Bits(0,
5474 NI_RTSI_OUTPUT_ADR_START1) |
5475 RTSI_Trig_Output_Bits(1,
5476 NI_RTSI_OUTPUT_ADR_START2) |
5477 RTSI_Trig_Output_Bits(2,
5478 NI_RTSI_OUTPUT_SCLKG) |
5479 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5480 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5481 RTSI_Trig_A_Output_Register);
5482 devpriv->rtsi_trig_b_output_reg =
5483 RTSI_Trig_Output_Bits(4,
5484 NI_RTSI_OUTPUT_DA_START1) |
5485 RTSI_Trig_Output_Bits(5,
5486 NI_RTSI_OUTPUT_G_SRC0) |
5487 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5488 if (board->reg_type & ni_reg_m_series_mask)
5489 devpriv->rtsi_trig_b_output_reg |=
5490 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5491 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5492 RTSI_Trig_B_Output_Register);
5495 * Sets the source and direction of the 4 on board lines
5496 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5500 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5501 struct comedi_subdevice *s,
5502 struct comedi_insn *insn, unsigned int *data)
5509 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5510 * given an arbitrary frequency input clock */
5511 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5512 unsigned *freq_divider,
5513 unsigned *freq_multiplier,
5514 unsigned *actual_period_ns)
5517 unsigned best_div = 1;
5518 static const unsigned max_div = 0x10;
5520 unsigned best_mult = 1;
5521 static const unsigned max_mult = 0x100;
5522 static const unsigned pico_per_nano = 1000;
5524 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5525 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5526 * 20 MHz for most timing clocks */
5527 static const unsigned target_picosec = 12500;
5528 static const unsigned fudge_factor_80_to_20Mhz = 4;
5529 int best_period_picosec = 0;
5530 for (div = 1; div <= max_div; ++div) {
5531 for (mult = 1; mult <= max_mult; ++mult) {
5532 unsigned new_period_ps =
5533 (reference_picosec * div) / mult;
5534 if (abs(new_period_ps - target_picosec) <
5535 abs(best_period_picosec - target_picosec)) {
5536 best_period_picosec = new_period_ps;
5542 if (best_period_picosec == 0) {
5543 printk("%s: bug, failed to find pll parameters\n", __func__);
5546 *freq_divider = best_div;
5547 *freq_multiplier = best_mult;
5549 (best_period_picosec * fudge_factor_80_to_20Mhz +
5550 (pico_per_nano / 2)) / pico_per_nano;
5554 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5556 const struct ni_board_struct *board = comedi_board(dev);
5558 if (board->reg_type & ni_reg_m_series_mask)
5564 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5565 unsigned source, unsigned period_ns)
5567 struct ni_private *devpriv = dev->private;
5568 static const unsigned min_period_ns = 50;
5569 static const unsigned max_period_ns = 1000;
5570 static const unsigned timeout = 1000;
5571 unsigned pll_control_bits;
5572 unsigned freq_divider;
5573 unsigned freq_multiplier;
5577 if (source == NI_MIO_PLL_PXI10_CLOCK)
5579 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5580 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5582 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5583 "for the phased-lock loop.\n", __func__,
5584 min_period_ns, max_period_ns);
5587 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5588 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5589 RTSI_Trig_Direction_Register);
5591 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5592 devpriv->clock_and_fout2 |=
5593 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5594 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5596 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5597 devpriv->clock_and_fout2 |=
5598 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5599 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5601 &devpriv->clock_ns);
5605 case NI_MIO_PLL_PXI10_CLOCK:
5606 /* pxi clock is 10MHz */
5607 devpriv->clock_and_fout2 |=
5608 MSeries_PLL_In_Source_Select_PXI_Clock10;
5609 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5611 &devpriv->clock_ns);
5617 unsigned rtsi_channel;
5618 static const unsigned max_rtsi_channel = 7;
5619 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5622 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5623 devpriv->clock_and_fout2 |=
5624 MSeries_PLL_In_Source_Select_RTSI_Bits
5629 if (rtsi_channel > max_rtsi_channel)
5631 retval = ni_mseries_get_pll_parameters(period_ns,
5641 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5643 MSeries_PLL_Divisor_Bits(freq_divider) |
5644 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5646 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5647 * freq_divider, freq_multiplier, pll_control_bits); */
5648 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5649 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5650 devpriv->clock_source = source;
5651 /* it seems to typically take a few hundred microseconds for PLL to lock */
5652 for (i = 0; i < timeout; ++i) {
5653 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5660 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5661 __func__, source, period_ns);
5667 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5670 const struct ni_board_struct *board = comedi_board(dev);
5671 struct ni_private *devpriv = dev->private;
5673 if (source == NI_MIO_INTERNAL_CLOCK) {
5674 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5675 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5676 RTSI_Trig_Direction_Register);
5677 devpriv->clock_ns = TIMEBASE_1_NS;
5678 if (board->reg_type & ni_reg_m_series_mask) {
5679 devpriv->clock_and_fout2 &=
5680 ~(MSeries_Timebase1_Select_Bit |
5681 MSeries_Timebase3_Select_Bit);
5682 ni_writew(devpriv->clock_and_fout2,
5683 M_Offset_Clock_and_Fout2);
5684 ni_writew(0, M_Offset_PLL_Control);
5686 devpriv->clock_source = source;
5688 if (board->reg_type & ni_reg_m_series_mask) {
5689 return ni_mseries_set_pll_master_clock(dev, source,
5692 if (source == NI_MIO_RTSI_CLOCK) {
5693 devpriv->rtsi_trig_direction_reg |=
5695 devpriv->stc_writew(dev,
5697 rtsi_trig_direction_reg,
5698 RTSI_Trig_Direction_Register);
5699 if (period_ns == 0) {
5701 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5705 devpriv->clock_ns = period_ns;
5707 devpriv->clock_source = source;
5715 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5718 const struct ni_board_struct *board = comedi_board(dev);
5720 if (chan >= num_configurable_rtsi_channels(dev)) {
5721 if (chan == old_RTSI_clock_channel) {
5722 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5726 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5727 __func__, chan, old_RTSI_clock_channel);
5734 case NI_RTSI_OUTPUT_ADR_START1:
5735 case NI_RTSI_OUTPUT_ADR_START2:
5736 case NI_RTSI_OUTPUT_SCLKG:
5737 case NI_RTSI_OUTPUT_DACUPDN:
5738 case NI_RTSI_OUTPUT_DA_START1:
5739 case NI_RTSI_OUTPUT_G_SRC0:
5740 case NI_RTSI_OUTPUT_G_GATE0:
5741 case NI_RTSI_OUTPUT_RGOUT0:
5742 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5745 case NI_RTSI_OUTPUT_RTSI_OSC:
5746 if (board->reg_type & ni_reg_m_series_mask)
5757 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5760 struct ni_private *devpriv = dev->private;
5762 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5765 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5766 devpriv->rtsi_trig_a_output_reg |=
5767 RTSI_Trig_Output_Bits(chan, source);
5768 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5769 RTSI_Trig_A_Output_Register);
5770 } else if (chan < 8) {
5771 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5772 devpriv->rtsi_trig_b_output_reg |=
5773 RTSI_Trig_Output_Bits(chan, source);
5774 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5775 RTSI_Trig_B_Output_Register);
5780 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5782 struct ni_private *devpriv = dev->private;
5785 return RTSI_Trig_Output_Source(chan,
5786 devpriv->rtsi_trig_a_output_reg);
5787 } else if (chan < num_configurable_rtsi_channels(dev)) {
5788 return RTSI_Trig_Output_Source(chan,
5789 devpriv->rtsi_trig_b_output_reg);
5791 if (chan == old_RTSI_clock_channel)
5792 return NI_RTSI_OUTPUT_RTSI_OSC;
5793 printk("%s: bug! should never get here?\n", __func__);
5798 static int ni_rtsi_insn_config(struct comedi_device *dev,
5799 struct comedi_subdevice *s,
5800 struct comedi_insn *insn, unsigned int *data)
5802 const struct ni_board_struct *board = comedi_board(dev);
5803 struct ni_private *devpriv = dev->private;
5804 unsigned int chan = CR_CHAN(insn->chanspec);
5807 case INSN_CONFIG_DIO_OUTPUT:
5808 if (chan < num_configurable_rtsi_channels(dev)) {
5809 devpriv->rtsi_trig_direction_reg |=
5810 RTSI_Output_Bit(chan,
5811 (board->reg_type & ni_reg_m_series_mask) != 0);
5812 } else if (chan == old_RTSI_clock_channel) {
5813 devpriv->rtsi_trig_direction_reg |=
5814 Drive_RTSI_Clock_Bit;
5816 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5817 RTSI_Trig_Direction_Register);
5819 case INSN_CONFIG_DIO_INPUT:
5820 if (chan < num_configurable_rtsi_channels(dev)) {
5821 devpriv->rtsi_trig_direction_reg &=
5822 ~RTSI_Output_Bit(chan,
5823 (board->reg_type & ni_reg_m_series_mask) != 0);
5824 } else if (chan == old_RTSI_clock_channel) {
5825 devpriv->rtsi_trig_direction_reg &=
5826 ~Drive_RTSI_Clock_Bit;
5828 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5829 RTSI_Trig_Direction_Register);
5831 case INSN_CONFIG_DIO_QUERY:
5832 if (chan < num_configurable_rtsi_channels(dev)) {
5834 (devpriv->rtsi_trig_direction_reg &
5835 RTSI_Output_Bit(chan,
5836 (board->reg_type & ni_reg_m_series_mask) != 0))
5837 ? INSN_CONFIG_DIO_OUTPUT
5838 : INSN_CONFIG_DIO_INPUT;
5839 } else if (chan == old_RTSI_clock_channel) {
5841 (devpriv->rtsi_trig_direction_reg &
5842 Drive_RTSI_Clock_Bit)
5843 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5847 case INSN_CONFIG_SET_CLOCK_SRC:
5848 return ni_set_master_clock(dev, data[1], data[2]);
5850 case INSN_CONFIG_GET_CLOCK_SRC:
5851 data[1] = devpriv->clock_source;
5852 data[2] = devpriv->clock_ns;
5855 case INSN_CONFIG_SET_ROUTING:
5856 return ni_set_rtsi_routing(dev, chan, data[1]);
5858 case INSN_CONFIG_GET_ROUTING:
5859 data[1] = ni_get_rtsi_routing(dev, chan);
5869 static int cs5529_wait_for_idle(struct comedi_device *dev)
5871 unsigned short status;
5872 const int timeout = HZ;
5875 for (i = 0; i < timeout; i++) {
5876 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5877 if ((status & CSS_ADC_BUSY) == 0) {
5880 set_current_state(TASK_INTERRUPTIBLE);
5881 if (schedule_timeout(1)) {
5885 /* printk("looped %i times waiting for idle\n", i); */
5887 printk("%s: %s: timeout\n", __FILE__, __func__);
5893 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5895 static const int timeout = 100;
5898 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5899 /* give time for command to start being serially clocked into cs5529.
5900 * this insures that the CSS_ADC_BUSY bit will get properly
5901 * set before we exit this function.
5903 for (i = 0; i < timeout; i++) {
5904 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5908 /* printk("looped %i times writing command to cs5529\n", i); */
5910 comedi_error(dev, "possible problem - never saw adc go busy?");
5914 /* write to cs5529 register */
5915 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5916 unsigned int reg_select_bits)
5918 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5919 CAL_ADC_Config_Data_High_Word_67xx);
5920 ni_ao_win_outw(dev, (value & 0xffff),
5921 CAL_ADC_Config_Data_Low_Word_67xx);
5922 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5923 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5924 if (cs5529_wait_for_idle(dev))
5925 comedi_error(dev, "time or signal in cs5529_config_write()");
5928 #ifdef NI_CS5529_DEBUG
5929 /* read from cs5529 register */
5930 static unsigned int cs5529_config_read(struct comedi_device *dev,
5931 unsigned int reg_select_bits)
5935 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5936 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5937 if (cs5529_wait_for_idle(dev))
5938 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5939 value = (ni_ao_win_inw(dev,
5940 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5942 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5947 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5950 unsigned short status;
5952 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5953 retval = cs5529_wait_for_idle(dev);
5956 "timeout or signal in cs5529_do_conversion()");
5959 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5960 if (status & CSS_OSC_DETECT) {
5962 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5965 if (status & CSS_OVERRANGE) {
5967 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5970 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5971 /* cs5529 returns 16 bit signed data in bipolar mode */
5977 static int cs5529_ai_insn_read(struct comedi_device *dev,
5978 struct comedi_subdevice *s,
5979 struct comedi_insn *insn, unsigned int *data)
5982 unsigned short sample;
5983 unsigned int channel_select;
5984 const unsigned int INTERNAL_REF = 0x1000;
5986 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5987 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5988 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5989 if (insn->chanspec & CR_ALT_SOURCE)
5990 channel_select = INTERNAL_REF;
5992 channel_select = CR_CHAN(insn->chanspec);
5993 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5995 for (n = 0; n < insn->n; n++) {
5996 retval = cs5529_do_conversion(dev, &sample);
6004 static int init_cs5529(struct comedi_device *dev)
6006 unsigned int config_bits =
6007 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6010 /* do self-calibration */
6011 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6012 CSCMD_CONFIG_REGISTER);
6013 /* need to force a conversion for calibration to run */
6014 cs5529_do_conversion(dev, NULL);
6016 /* force gain calibration to 1 */
6017 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6018 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6019 CSCMD_CONFIG_REGISTER);
6020 if (cs5529_wait_for_idle(dev))
6021 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6023 #ifdef NI_CS5529_DEBUG
6024 printk("config: 0x%x\n", cs5529_config_read(dev,
6025 CSCMD_CONFIG_REGISTER));
6026 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6027 printk("offset: 0x%x\n", cs5529_config_read(dev,
6028 CSCMD_OFFSET_REGISTER));