drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         The PCI-MIO E series driver was originally written by
  26         Tomasz Motylewski <...>, and ported to comedi by ds.
  27
  28         References for specifications:
  29
  30            321747b.pdf  Register Level Programmer Manual (obsolete)
  31            321747c.pdf  Register Level Programmer Manual (new)
  32            DAQ-STC reference manual
  33
  34         Other possibly relevant info:
  35
  36            320517c.pdf  User manual (obsolete)
  37            320517f.pdf  User manual (new)
  38            320889a.pdf  delete
  39            320906c.pdf  maximum signal ratings
  40            321066a.pdf  about 16x
  41            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  42            321808a.pdf  about at-mio-16e-10 rev P
  43            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  44            321838a.pdf  about at-mio-16de-10 rev N
  45
  46         ISSUES:
  47
  48 */
  49
  50 /* #define USE_KMALLOC */
  51
  52 #include "mite.h"
  53
  54 #include "comedi_fc.h"
  55 #include "../comedidev.h"
  56
  57
  58 #define PCI_MITE_SIZE           4096
  59 #define PCI_DAQ_SIZE            4096
  60 #define PCI_DAQ_SIZE_660X       8192
  61
  62 struct mite_struct *mite_devices;
  63 EXPORT_SYMBOL(mite_devices);
  64
  65 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  66
  67 static void mite_init(void)
  68 {
  69         struct pci_dev *pcidev = NULL;
  70         struct mite_struct *mite;
  71
  72         for_each_pci_dev(pcidev) {
  73                 if (pcidev->vendor == PCI_VENDOR_ID_NI) {
  74                         unsigned i;
  75
  76                         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  77                         if (!mite) {
  78                                 printk(KERN_ERR "mite: allocation failed\n");
  79                                 pci_dev_put(pcidev);
  80                                 return;
  81                         }
  82                         spin_lock_init(&mite->lock);
  83                         mite->pcidev = pci_dev_get(pcidev);
  84                         for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  85                                 mite->channels[i].mite = mite;
  86                                 mite->channels[i].channel = i;
  87                                 mite->channels[i].done = 1;
  88                         }
  89                         mite->next = mite_devices;
  90                         mite_devices = mite;
  91                 }
  92         }
  93 }
  94
  95 static void dump_chip_signature(u32 csigr_bits)
  96 {
  97         printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
  98                "interface mode = %i\n",
  99                mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
 100                mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
 101         printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
 102                "wins = %i, iowins = %i\n",
 103                mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
 104                mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
 105 }
 106
 107 unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
 108 {
 109         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
 110         unsigned empty_count = (fcr_bits >> 16) & 0xff;
 111         unsigned full_count = fcr_bits & 0xff;
 112         return empty_count + full_count;
 113 }
 114
 115 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
 116 {
 117         unsigned long length;
 118         resource_size_t addr;
 119         int i;
 120         u32 csigr_bits;
 121         unsigned unknown_dma_burst_bits;
 122
 123         if (comedi_pci_enable(mite->pcidev, "mite")) {
 124                 printk(KERN_ERR "error enabling mite and requesting io regions\n");
 125                 return -EIO;
 126         }
 127         pci_set_master(mite->pcidev);
 128
 129         addr = pci_resource_start(mite->pcidev, 0);
 130         mite->mite_phys_addr = addr;
 131         mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
 132         if (!mite->mite_io_addr) {
 133                 printk(KERN_ERR "Failed to remap mite io memory address\n");
 134                 return -ENOMEM;
 135         }
 136         printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
 137                (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
 138
 139         addr = pci_resource_start(mite->pcidev, 1);
 140         mite->daq_phys_addr = addr;
 141         length = pci_resource_len(mite->pcidev, 1);
 142         /*
 143          * In case of a 660x board, DAQ size is 8k instead of 4k
 144          * (see as shown by lspci output)
 145          */
 146         mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
 147         if (!mite->daq_io_addr) {
 148                 printk(KERN_ERR "Failed to remap daq io memory address\n");
 149                 return -ENOMEM;
 150         }
 151         printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
 152                (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
 153
 154         if (use_iodwbsr_1) {
 155                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 156                 printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
 157                 writel(mite->daq_phys_addr | WENAB |
 158                        MITE_IODWBSR_1_WSIZE_bits(length),
 159                        mite->mite_io_addr + MITE_IODWBSR_1);
 160                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 161         } else {
 162                 writel(mite->daq_phys_addr | WENAB,
 163                        mite->mite_io_addr + MITE_IODWBSR);
 164         }
 165         /*
 166          * make sure dma bursts work. I got this from running a bus analyzer
 167          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 168          * of 0x61f and bursts worked. 6281 powered up with register value of
 169          * 0x1f and bursts didn't work. The NI windows driver reads the
 170          * register, then does a bitwise-or of 0x600 with it and writes it back.
 171          */
 172         unknown_dma_burst_bits =
 173             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 174         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 175         writel(unknown_dma_burst_bits,
 176                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 177
 178         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 179         mite->num_channels = mite_csigr_dmac(csigr_bits);
 180         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 181                 printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
 182                        "channels. Setting to %i.\n",
 183                        mite->num_channels, MAX_MITE_DMA_CHANNELS);
 184                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 185         }
 186         dump_chip_signature(csigr_bits);
 187         for (i = 0; i < mite->num_channels; i++) {
 188                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 189                 /* disable interrupts */
 190                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 191                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 192                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 193                        mite->mite_io_addr + MITE_CHCR(i));
 194         }
 195         mite->fifo_size = mite_fifo_size(mite, 0);
 196         printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
 197         mite->used = 1;
 198
 199         return 0;
 200 }
 201 EXPORT_SYMBOL(mite_setup2);
 202
 203 int mite_setup(struct mite_struct *mite)
 204 {
 205         return mite_setup2(mite, 0);
 206 }
 207 EXPORT_SYMBOL(mite_setup);
 208
 209 static void mite_cleanup(void)
 210 {
 211         struct mite_struct *mite, *next;
 212
 213         for (mite = mite_devices; mite; mite = next) {
 214                 pci_dev_put(mite->pcidev);
 215                 next = mite->next;
 216                 kfree(mite);
 217         }
 218 }
 219
 220 void mite_unsetup(struct mite_struct *mite)
 221 {
 222         /* unsigned long offset, start, length; */
 223
 224         if (!mite)
 225                 return;
 226
 227         if (mite->mite_io_addr) {
 228                 iounmap(mite->mite_io_addr);
 229                 mite->mite_io_addr = NULL;
 230         }
 231         if (mite->daq_io_addr) {
 232                 iounmap(mite->daq_io_addr);
 233                 mite->daq_io_addr = NULL;
 234         }
 235         if (mite->mite_phys_addr) {
 236                 comedi_pci_disable(mite->pcidev);
 237                 mite->mite_phys_addr = 0;
 238         }
 239
 240         mite->used = 0;
 241 }
 242 EXPORT_SYMBOL(mite_unsetup);
 243
 244 void mite_list_devices(void)
 245 {
 246         struct mite_struct *mite, *next;
 247
 248         printk(KERN_INFO "Available NI device IDs:");
 249         if (mite_devices)
 250                 for (mite = mite_devices; mite; mite = next) {
 251                         next = mite->next;
 252                         printk(KERN_INFO " 0x%04x", mite_device_id(mite));
 253                         if (mite->used)
 254                                 printk(KERN_INFO "(used)");
 255                 }
 256         printk(KERN_INFO "\n");
 257 }
 258 EXPORT_SYMBOL(mite_list_devices);
 259
 260 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
 261 {
 262         struct mite_dma_descriptor_ring *ring =
 263             kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
 264
 265         if (ring == NULL)
 266                 return ring;
 267         ring->hw_dev = get_device(&mite->pcidev->dev);
 268         if (ring->hw_dev == NULL) {
 269                 kfree(ring);
 270                 return NULL;
 271         }
 272         ring->n_links = 0;
 273         ring->descriptors = NULL;
 274         ring->descriptors_dma_addr = 0;
 275         return ring;
 276 };
 277 EXPORT_SYMBOL(mite_alloc_ring);
 278
 279 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
 280 {
 281         if (ring) {
 282                 if (ring->descriptors) {
 283                         dma_free_coherent(ring->hw_dev,
 284                                           ring->n_links *
 285                                           sizeof(struct mite_dma_descriptor),
 286                                           ring->descriptors,
 287                                           ring->descriptors_dma_addr);
 288                 }
 289                 put_device(ring->hw_dev);
 290                 kfree(ring);
 291         }
 292 };
 293 EXPORT_SYMBOL(mite_free_ring);
 294
 295 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 296                                                    struct
 297                                                    mite_dma_descriptor_ring
 298                                                    *ring, unsigned min_channel,
 299                                                    unsigned max_channel)
 300 {
 301         int i;
 302         unsigned long flags;
 303         struct mite_channel *channel = NULL;
 304
 305         /* spin lock so mite_release_channel can be called safely
 306          * from interrupts
 307          */
 308         spin_lock_irqsave(&mite->lock, flags);
 309         for (i = min_channel; i <= max_channel; ++i) {
 310                 if (mite->channel_allocated[i] == 0) {
 311                         mite->channel_allocated[i] = 1;
 312                         channel = &mite->channels[i];
 313                         channel->ring = ring;
 314                         break;
 315                 }
 316         }
 317         spin_unlock_irqrestore(&mite->lock, flags);
 318         return channel;
 319 }
 320 EXPORT_SYMBOL(mite_request_channel_in_range);
 321
 322 void mite_release_channel(struct mite_channel *mite_chan)
 323 {
 324         struct mite_struct *mite = mite_chan->mite;
 325         unsigned long flags;
 326
 327         /*  spin lock to prevent races with mite_request_channel */
 328         spin_lock_irqsave(&mite->lock, flags);
 329         if (mite->channel_allocated[mite_chan->channel]) {
 330                 mite_dma_disarm(mite_chan);
 331                 mite_dma_reset(mite_chan);
 332         /*
 333          * disable all channel's interrupts (do it after disarm/reset so
 334          * MITE_CHCR reg isn't changed while dma is still active!)
 335          */
 336                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 337                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 338                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 339                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 340                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 341                 mite->channel_allocated[mite_chan->channel] = 0;
 342                 mite_chan->ring = NULL;
 343                 mmiowb();
 344         }
 345         spin_unlock_irqrestore(&mite->lock, flags);
 346 }
 347 EXPORT_SYMBOL(mite_release_channel);
 348
 349 void mite_dma_arm(struct mite_channel *mite_chan)
 350 {
 351         struct mite_struct *mite = mite_chan->mite;
 352         int chor;
 353         unsigned long flags;
 354
 355         MDPRINTK("mite_dma_arm ch%i\n", channel);
 356         /*
 357          * memory barrier is intended to insure any twiddling with the buffer
 358          * is done before writing to the mite to arm dma transfer
 359          */
 360         smp_mb();
 361         /* arm */
 362         chor = CHOR_START;
 363         spin_lock_irqsave(&mite->lock, flags);
 364         mite_chan->done = 0;
 365         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 366         mmiowb();
 367         spin_unlock_irqrestore(&mite->lock, flags);
 368 /*       mite_dma_tcr(mite, channel); */
 369 }
 370 EXPORT_SYMBOL(mite_dma_arm);
 371
 372 /**************************************/
 373
 374 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 375                     struct comedi_async *async)
 376 {
 377         unsigned int n_links;
 378         int i;
 379
 380         if (ring->descriptors) {
 381                 dma_free_coherent(ring->hw_dev,
 382                                   ring->n_links *
 383                                   sizeof(struct mite_dma_descriptor),
 384                                   ring->descriptors,
 385                                   ring->descriptors_dma_addr);
 386         }
 387         ring->descriptors = NULL;
 388         ring->descriptors_dma_addr = 0;
 389         ring->n_links = 0;
 390
 391         if (async->prealloc_bufsz == 0)
 392                 return 0;
 393
 394         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 395
 396         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 397
 398         ring->descriptors =
 399             dma_alloc_coherent(ring->hw_dev,
 400                                n_links * sizeof(struct mite_dma_descriptor),
 401                                &ring->descriptors_dma_addr, GFP_KERNEL);
 402         if (!ring->descriptors) {
 403                 printk(KERN_ERR "mite: ring buffer allocation failed\n");
 404                 return -ENOMEM;
 405         }
 406         ring->n_links = n_links;
 407
 408         for (i = 0; i < n_links; i++) {
 409                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 410                 ring->descriptors[i].addr =
 411                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 412                 ring->descriptors[i].next =
 413                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 414                                                               1) *
 415                                 sizeof(struct mite_dma_descriptor));
 416         }
 417         ring->descriptors[n_links - 1].next =
 418             cpu_to_le32(ring->descriptors_dma_addr);
 419         /*
 420          * barrier is meant to insure that all the writes to the dma descriptors
 421          * have completed before the dma controller is commanded to read them
 422          */
 423         smp_wmb();
 424         return 0;
 425 }
 426 EXPORT_SYMBOL(mite_buf_change);
 427
 428 void mite_prep_dma(struct mite_channel *mite_chan,
 429                    unsigned int num_device_bits, unsigned int num_memory_bits)
 430 {
 431         unsigned int chor, chcr, mcr, dcr, lkcr;
 432         struct mite_struct *mite = mite_chan->mite;
 433
 434         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 435
 436         /* reset DMA and FIFO */
 437         chor = CHOR_DMARESET | CHOR_FRESET;
 438         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 439
 440         /* short link chaining mode */
 441         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 442             CHCR_BURSTEN;
 443         /*
 444          * Link Complete Interrupt: interrupt every time a link
 445          * in MITE_RING is completed. This can generate a lot of
 446          * extra interrupts, but right now we update the values
 447          * of buf_int_ptr and buf_int_count at each interrupt. A
 448          * better method is to poll the MITE before each user
 449          * "read()" to calculate the number of bytes available.
 450          */
 451         chcr |= CHCR_SET_LC_IE;
 452         if (num_memory_bits == 32 && num_device_bits == 16) {
 453                 /*
 454                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 455                  * samples into the fifo in the right order. Tested doing 32 bit
 456                  * memory to 16 bit device transfers to the analog out of a
 457                  * pxi-6281, which has mite version = 1, type = 4. This also
 458                  * works for dma reads from the counters on e-series boards.
 459                  */
 460                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 461         }
 462         if (mite_chan->dir == COMEDI_INPUT)
 463                 chcr |= CHCR_DEV_TO_MEM;
 464
 465         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 466
 467         /* to/from memory */
 468         mcr = CR_RL(64) | CR_ASEQUP;
 469         switch (num_memory_bits) {
 470         case 8:
 471                 mcr |= CR_PSIZE8;
 472                 break;
 473         case 16:
 474                 mcr |= CR_PSIZE16;
 475                 break;
 476         case 32:
 477                 mcr |= CR_PSIZE32;
 478                 break;
 479         default:
 480                 printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
 481                        "transfer\n");
 482                 break;
 483         }
 484         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 485
 486         /* from/to device */
 487         dcr = CR_RL(64) | CR_ASEQUP;
 488         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 489         switch (num_device_bits) {
 490         case 8:
 491                 dcr |= CR_PSIZE8;
 492                 break;
 493         case 16:
 494                 dcr |= CR_PSIZE16;
 495                 break;
 496         case 32:
 497                 dcr |= CR_PSIZE32;
 498                 break;
 499         default:
 500                 printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
 501                        "transfer\n");
 502                 break;
 503         }
 504         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 505
 506         /* reset the DAR */
 507         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 508
 509         /* the link is 32bits */
 510         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 511         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 512
 513         /* starting address for link chaining */
 514         writel(mite_chan->ring->descriptors_dma_addr,
 515                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 516
 517         MDPRINTK("exit mite_prep_dma\n");
 518 }
 519 EXPORT_SYMBOL(mite_prep_dma);
 520
 521 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 522 {
 523         struct mite_struct *mite = mite_chan->mite;
 524         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 525 }
 526
 527 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 528 {
 529         struct mite_struct *mite = mite_chan->mite;
 530         return readl(mite->mite_io_addr +
 531                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 532 }
 533 EXPORT_SYMBOL(mite_bytes_in_transit);
 534
 535 /* returns lower bound for number of bytes transferred from device to memory */
 536 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 537 {
 538         u32 device_byte_count;
 539
 540         device_byte_count = mite_device_bytes_transferred(mite_chan);
 541         return device_byte_count - mite_bytes_in_transit(mite_chan);
 542 }
 543 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
 544
 545 /* returns upper bound for number of bytes transferred from device to memory */
 546 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 547 {
 548         u32 in_transit_count;
 549
 550         in_transit_count = mite_bytes_in_transit(mite_chan);
 551         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 552 }
 553 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
 554
 555 /* returns lower bound for number of bytes read from memory to device */
 556 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 557 {
 558         u32 device_byte_count;
 559
 560         device_byte_count = mite_device_bytes_transferred(mite_chan);
 561         return device_byte_count + mite_bytes_in_transit(mite_chan);
 562 }
 563 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
 564
 565 /* returns upper bound for number of bytes read from memory to device */
 566 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 567 {
 568         u32 in_transit_count;
 569
 570         in_transit_count = mite_bytes_in_transit(mite_chan);
 571         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 572 }
 573 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
 574
 575 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 576 {
 577         struct mite_struct *mite = mite_chan->mite;
 578         int tcr;
 579         int lkar;
 580
 581         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 582         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 583         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 584                  lkar, tcr);
 585
 586         return tcr;
 587 }
 588 EXPORT_SYMBOL(mite_dma_tcr);
 589
 590 void mite_dma_disarm(struct mite_channel *mite_chan)
 591 {
 592         struct mite_struct *mite = mite_chan->mite;
 593         unsigned chor;
 594
 595         /* disarm */
 596         chor = CHOR_ABORT;
 597         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 598 }
 599 EXPORT_SYMBOL(mite_dma_disarm);
 600
 601 int mite_sync_input_dma(struct mite_channel *mite_chan,
 602                         struct comedi_async *async)
 603 {
 604         int count;
 605         unsigned int nbytes, old_alloc_count;
 606         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 607
 608         old_alloc_count = async->buf_write_alloc_count;
 609         /* write alloc as much as we can */
 610         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 611
 612         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 613         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 614                   old_alloc_count) > 0) {
 615                 printk("mite: DMA overwrite of free area\n");
 616                 async->events |= COMEDI_CB_OVERFLOW;
 617                 return -1;
 618         }
 619
 620         count = nbytes - async->buf_write_count;
 621         /* it's possible count will be negative due to
 622          * conservative value returned by mite_bytes_written_to_memory_lb */
 623         if (count <= 0)
 624                 return 0;
 625
 626         comedi_buf_write_free(async, count);
 627
 628         async->scan_progress += count;
 629         if (async->scan_progress >= bytes_per_scan) {
 630                 async->scan_progress %= bytes_per_scan;
 631                 async->events |= COMEDI_CB_EOS;
 632         }
 633         async->events |= COMEDI_CB_BLOCK;
 634         return 0;
 635 }
 636 EXPORT_SYMBOL(mite_sync_input_dma);
 637
 638 int mite_sync_output_dma(struct mite_channel *mite_chan,
 639                          struct comedi_async *async)
 640 {
 641         int count;
 642         u32 nbytes_ub, nbytes_lb;
 643         unsigned int old_alloc_count;
 644         u32 stop_count =
 645             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 646
 647         old_alloc_count = async->buf_read_alloc_count;
 648         /*  read alloc as much as we can */
 649         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 650         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 651         if (async->cmd.stop_src == TRIG_COUNT &&
 652             (int)(nbytes_lb - stop_count) > 0)
 653                 nbytes_lb = stop_count;
 654         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 655         if (async->cmd.stop_src == TRIG_COUNT &&
 656             (int)(nbytes_ub - stop_count) > 0)
 657                 nbytes_ub = stop_count;
 658         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 659                 printk(KERN_ERR "mite: DMA underrun\n");
 660                 async->events |= COMEDI_CB_OVERFLOW;
 661                 return -1;
 662         }
 663         count = nbytes_lb - async->buf_read_count;
 664         if (count <= 0)
 665                 return 0;
 666
 667         if (count) {
 668                 comedi_buf_read_free(async, count);
 669                 async->events |= COMEDI_CB_BLOCK;
 670         }
 671         return 0;
 672 }
 673 EXPORT_SYMBOL(mite_sync_output_dma);
 674
 675 unsigned mite_get_status(struct mite_channel *mite_chan)
 676 {
 677         struct mite_struct *mite = mite_chan->mite;
 678         unsigned status;
 679         unsigned long flags;
 680
 681         spin_lock_irqsave(&mite->lock, flags);
 682         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 683         if (status & CHSR_DONE) {
 684                 mite_chan->done = 1;
 685                 writel(CHOR_CLRDONE,
 686                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 687         }
 688         mmiowb();
 689         spin_unlock_irqrestore(&mite->lock, flags);
 690         return status;
 691 }
 692 EXPORT_SYMBOL(mite_get_status);
 693
 694 int mite_done(struct mite_channel *mite_chan)
 695 {
 696         struct mite_struct *mite = mite_chan->mite;
 697         unsigned long flags;
 698         int done;
 699
 700         mite_get_status(mite_chan);
 701         spin_lock_irqsave(&mite->lock, flags);
 702         done = mite_chan->done;
 703         spin_unlock_irqrestore(&mite->lock, flags);
 704         return done;
 705 }
 706 EXPORT_SYMBOL(mite_done);
 707
 708 #ifdef DEBUG_MITE
 709
 710 static void mite_decode(char **bit_str, unsigned int bits);
 711
 712 /* names of bits in mite registers */
 713
 714 static const char *const mite_CHOR_strings[] = {
 715         "start", "cont", "stop", "abort",
 716         "freset", "clrlc", "clrrb", "clrdone",
 717         "clr_lpause", "set_lpause", "clr_send_tc",
 718         "set_send_tc", "12", "13", "14",
 719         "15", "16", "17", "18",
 720         "19", "20", "21", "22",
 721         "23", "24", "25", "26",
 722         "27", "28", "29", "30",
 723         "dmareset",
 724 };
 725
 726 static const char *const mite_CHCR_strings[] = {
 727         "continue", "ringbuff", "2", "3",
 728         "4", "5", "6", "7",
 729         "8", "9", "10", "11",
 730         "12", "13", "bursten", "fifodis",
 731         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 732         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 733         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 734         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 735 };
 736
 737 static const char *const mite_MCR_strings[] = {
 738         "amdevice", "1", "2", "3",
 739         "4", "5", "portio", "portvxi",
 740         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 741         "12", "13", "blocken", "berhand",
 742         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 743         "rd512", "rl1", "rl2", "rl8",
 744         "24", "25", "26", "27",
 745         "28", "29", "30", "stopen",
 746 };
 747
 748 static const char *const mite_DCR_strings[] = {
 749         "amdevice", "1", "2", "3",
 750         "4", "5", "portio", "portvxi",
 751         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 752         "aseqxp8", "13", "blocken", "berhand",
 753         "reqsintlim", "reqs1", "reqs2", "rd32",
 754         "rd512", "rl1", "rl2", "rl8",
 755         "23", "24", "25", "27",
 756         "28", "wsdevc", "wsdevs", "rwdevpack",
 757 };
 758
 759 static const char *const mite_LKCR_strings[] = {
 760         "amdevice", "1", "2", "3",
 761         "4", "5", "portio", "portvxi",
 762         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 763         "12", "13", "14", "berhand",
 764         "16", "17", "18", "rd32",
 765         "rd512", "rl1", "rl2", "rl8",
 766         "24", "25", "26", "27",
 767         "28", "29", "30", "chngend",
 768 };
 769
 770 static const char *const mite_CHSR_strings[] = {
 771         "d.err0", "d.err1", "m.err0", "m.err1",
 772         "l.err0", "l.err1", "drq0", "drq1",
 773         "end", "xferr", "operr0", "operr1",
 774         "stops", "habort", "sabort", "error",
 775         "16", "conts_rb", "18", "linkc",
 776         "20", "drdy", "22", "mrdy",
 777         "24", "done", "26", "sars",
 778         "28", "lpauses", "30", "int",
 779 };
 780
 781 void mite_dump_regs(struct mite_channel *mite_chan)
 782 {
 783         unsigned long mite_io_addr =
 784             (unsigned long)mite_chan->mite->mite_io_addr;
 785         unsigned long addr = 0;
 786         unsigned long temp = 0;
 787
 788         printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
 789         printk(KERN_DEBUG "mite address is  =0x%08lx\n", mite_io_addr);
 790
 791         addr = mite_io_addr + MITE_CHOR(channel);
 792         printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
 793                temp = readl(addr));
 794         mite_decode(mite_CHOR_strings, temp);
 795         addr = mite_io_addr + MITE_CHCR(channel);
 796         printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
 797                temp = readl(addr));
 798         mite_decode(mite_CHCR_strings, temp);
 799         addr = mite_io_addr + MITE_TCR(channel);
 800         printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
 801                readl(addr));
 802         addr = mite_io_addr + MITE_MCR(channel);
 803         printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
 804                temp = readl(addr));
 805         mite_decode(mite_MCR_strings, temp);
 806
 807         addr = mite_io_addr + MITE_MAR(channel);
 808         printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
 809                readl(addr));
 810         addr = mite_io_addr + MITE_DCR(channel);
 811         printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
 812                temp = readl(addr));
 813         mite_decode(mite_DCR_strings, temp);
 814         addr = mite_io_addr + MITE_DAR(channel);
 815         printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
 816                readl(addr));
 817         addr = mite_io_addr + MITE_LKCR(channel);
 818         printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
 819                temp = readl(addr));
 820         mite_decode(mite_LKCR_strings, temp);
 821         addr = mite_io_addr + MITE_LKAR(channel);
 822         printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
 823                readl(addr));
 824         addr = mite_io_addr + MITE_CHSR(channel);
 825         printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
 826                temp = readl(addr));
 827         mite_decode(mite_CHSR_strings, temp);
 828         addr = mite_io_addr + MITE_FCR(channel);
 829         printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
 830                readl(addr));
 831 }
 832 EXPORT_SYMBOL(mite_dump_regs);
 833
 834 static void mite_decode(char **bit_str, unsigned int bits)
 835 {
 836         int i;
 837
 838         for (i = 31; i >= 0; i--) {
 839                 if (bits & (1 << i))
 840                         printk(KERN_DEBUG " %s", bit_str[i]);
 841         }
 842         printk(KERN_DEBUG "\n");
 843 }
 844 EXPORT_SYMBOL(mite_decode);
 845 #endif
 846
 847 #ifdef MODULE
 848 int __init init_module(void)
 849 {
 850         mite_init();
 851         mite_list_devices();
 852
 853         return 0;
 854 }
 855
 856 void __exit cleanup_module(void)
 857 {
 858         mite_cleanup();
 859 }
 860 #endif
 861
 862 MODULE_AUTHOR("Comedi http://www.comedi.org");
 863 MODULE_DESCRIPTION("Comedi low-level driver");
 864 MODULE_LICENSE("GPL");