1 /* comedi/drivers/amplc_dio200_pci.c
3 * Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296.
5 * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
7 * COMEDI - Linux Control and Measurement Device Interface
8 * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * Driver: amplc_dio200_pci
23 * Description: Amplicon 200 Series PCI Digital I/O
24 * Author: Ian Abbott <abbotti@mev.co.uk>
25 * Devices: [Amplicon] PCI215 (amplc_dio200_pci), PCIe215, PCIe236,
27 * Updated: Mon, 18 Mar 2013 15:03:50 +0000
30 * Configuration options:
33 * Manual configuration of PCI(e) cards is not supported; they are configured
38 * PCI215 PCIe215 PCIe236
39 * ------------- ------------- -------------
42 * 1 PPI-Y UNUSED UNUSED
43 * 2 CTR-Z1 PPI-Y UNUSED
44 * 3 CTR-Z2 UNUSED UNUSED
45 * 4 INTERRUPT CTR-Z1 CTR-Z1
48 * 7 INTERRUPT INTERRUPT
52 * ------------- -------------
63 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
64 * are configurable as inputs or outputs in four groups:
66 * Port A - channels 0 to 7
67 * Port B - channels 8 to 15
68 * Port CL - channels 16 to 19
69 * Port CH - channels 20 to 23
71 * Only mode 0 of the 8255 chips is supported.
73 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
74 * channel is configured individually with INSN_CONFIG instructions. The
75 * specific type of configuration instruction is specified in data[0].
76 * Some configuration instructions expect an additional parameter in
77 * data[1]; others return a value in data[1]. The following configuration
78 * instructions are supported:
80 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
81 * BCD/binary setting specified in data[1].
83 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
84 * counter channel into data[1].
86 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
87 * specified in data[1] (this is a hardware-specific value). Not
88 * supported on PC214E. For the other boards, valid clock sources are
91 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
92 * connector. (N.B. for other values, the counter channel's CLKn
93 * pin on the SK1 connector is an output!)
94 * 1. Internal 10 MHz clock.
95 * 2. Internal 1 MHz clock.
96 * 3. Internal 100 kHz clock.
97 * 4. Internal 10 kHz clock.
98 * 5. Internal 1 kHz clock.
99 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
100 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
101 * the SK1 connector. This pin is shared by all three counter
102 * channels on the chip.
104 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
105 * and the following additional clock sources are defined:
107 * 8. HIGH logic level.
108 * 9. LOW logic level.
109 * 10. "Pattern present" signal.
110 * 11. Internal 20 MHz clock.
112 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
113 * clock source in data[1]. For internal clock sources, data[2] is set
114 * to the period in ns.
116 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
117 * specified in data[2] (this is a hardware-specific value). Not
118 * supported on PC214E. For the other boards, valid gate sources are 0
121 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
122 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
123 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
124 * connector. (N.B. for other values, the counter channel's GATn
125 * pin on the SK1 connector is an output!)
126 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
133 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
134 * the following additional clock sources and clock sources 6 and 7 are
137 * 6. /GAT n, negated version of the counter channel's dedicated
138 * GAT input (negated version of gate source 2).
139 * 7. OUT n-2, the non-inverted output of counter channel n-2
140 * (negated version of gate source 3).
141 * 8. "Pattern present" signal, HIGH while pattern present.
142 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
144 * 10. "Pattern gone away" latched signal, latches LOW when pattern
145 * goes away after it occurred.
146 * 11. Negated "pattern present" signal, LOW while pattern present
147 * (negated version of gate source 8).
148 * 12. Negated "pattern occurred" latched signal, latches LOW when
149 * pattern occurs (negated version of gate source 9).
150 * 13. Negated "pattern gone away" latched signal, latches LOW when
151 * pattern goes away after it occurred (negated version of gate
154 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
157 * Clock and gate interconnection notes:
159 * 1. Clock source OUT n-1 is the output of the preceding channel on the
160 * same counter subdevice if n > 0, or the output of channel 2 on the
161 * preceding counter subdevice (see note 3) if n = 0.
163 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
164 * same counter subdevice if n = 2, or the inverted output of channel n+1
165 * on the preceding counter subdevice (see note 3) if n < 2.
167 * 3. The counter subdevices are connected in a ring, so the highest
168 * counter subdevice precedes the lowest.
170 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
172 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
173 * digital inputs come from the interrupt status register. The number of
174 * channels matches the number of interrupt sources. The PC214E does not
175 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
180 * PCI215 PCIe215 PCIe236
181 * ------------- ------------- -------------
183 * 0 PPI-X-C0 PPI-X-C0 PPI-X-C0
184 * 1 PPI-X-C3 PPI-X-C3 PPI-X-C3
185 * 2 PPI-Y-C0 PPI-Y-C0 unused
186 * 3 PPI-Y-C3 PPI-Y-C3 unused
187 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
188 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
191 * ------------- -------------
193 * 0 PPI-X-C0 PPI-X1-C0
194 * 1 PPI-X-C3 PPI-X1-C3
195 * 2 PPI-Y-C0 PPI-Y1-C0
196 * 3 PPI-Y-C3 PPI-Y1-C3
197 * 4 PPI-Z-C0 CTR-Z1-OUT1
198 * 5 PPI-Z-C3 CTR-Z2-OUT1
200 * When an interrupt source is enabled in the interrupt source enable
201 * register, a rising edge on the source signal latches the corresponding
202 * bit to 1 in the interrupt status register.
204 * When the interrupt status register value as a whole (actually, just the
205 * 6 least significant bits) goes from zero to non-zero, the board will
206 * generate an interrupt. The interrupt will remain asserted until the
207 * interrupt status register is cleared to zero. To clear a bit to zero in
208 * the interrupt status register, the corresponding interrupt source must
209 * be disabled in the interrupt source enable register (there is no
210 * separate interrupt clear register).
214 * The driver supports a read streaming acquisition command on the
215 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
216 * to be enabled. All channels will be sampled together (convert_src ==
217 * TRIG_NOW). The scan begins a short time after the hardware interrupt
218 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
219 * scan_begin_arg == 0). The value read from the interrupt status register
220 * is packed into a short value, one bit per requested channel, in the
221 * order they appear in the channel list.
224 #include <linux/module.h>
225 #include <linux/interrupt.h>
227 #include "../comedi_pci.h"
229 #include "amplc_dio200.h"
232 * Board descriptions.
235 enum dio200_pci_model {
243 static const struct dio200_board dio200_pci_boards[] = {
249 sd_8255, sd_8255, sd_8254, sd_8254, sd_intr
251 .sdinfo = { 0x00, 0x08, 0x10, 0x14, 0x3f },
253 .has_clk_gat_sce = true,
260 sd_8255, sd_8255, sd_8255, sd_intr
262 .sdinfo = { 0x00, 0x08, 0x10, 0x3f },
270 sd_8255, sd_none, sd_8255, sd_none,
271 sd_8254, sd_8254, sd_timer, sd_intr
274 0x00, 0x00, 0x08, 0x00, 0x10, 0x14, 0x00, 0x3f
277 .has_clk_gat_sce = true,
285 sd_8255, sd_none, sd_none, sd_none,
286 sd_8254, sd_8254, sd_timer, sd_intr
289 0x00, 0x00, 0x00, 0x00, 0x10, 0x14, 0x00, 0x3f
292 .has_clk_gat_sce = true,
300 sd_8255, sd_8255, sd_8255, sd_8255,
301 sd_8254, sd_8254, sd_timer, sd_intr
304 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x00, 0x3f
307 .has_clk_gat_sce = true,
313 * This function does some special set-up for the PCIe boards
314 * PCIe215, PCIe236, PCIe296.
316 static int dio200_pcie_board_setup(struct comedi_device *dev)
318 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
319 void __iomem *brbase;
322 * The board uses Altera Cyclone IV with PCI-Express hard IP.
323 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
324 * Control registers in PCI BAR 0, offset 0, and the length of
325 * these registers is 0x4000.
327 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
328 * Enable" register at offset 0x50 to allow generation of PCIe
329 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
331 if (pci_resource_len(pcidev, 0) < 0x4000) {
332 dev_err(dev->class_dev, "error! bad PCI region!\n");
335 brbase = pci_ioremap_bar(pcidev, 0);
337 dev_err(dev->class_dev, "error! failed to map registers!\n");
340 writel(0x80, brbase + 0x50);
342 /* Enable "enhanced" features of board. */
343 amplc_dio200_set_enhance(dev, 1);
347 static int dio200_pci_auto_attach(struct comedi_device *dev,
348 unsigned long context_model)
350 struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
351 const struct dio200_board *board = NULL;
355 if (context_model < ARRAY_SIZE(dio200_pci_boards))
356 board = &dio200_pci_boards[context_model];
359 dev->board_ptr = board;
360 dev->board_name = board->name;
362 dev_info(dev->class_dev, "%s: attach pci %s (%s)\n",
363 dev->driver->driver_name, pci_name(pci_dev), dev->board_name);
365 ret = comedi_pci_enable(dev);
369 bar = board->mainbar;
370 if (pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) {
371 dev->mmio = pci_ioremap_bar(pci_dev, bar);
373 dev_err(dev->class_dev,
374 "error! cannot remap registers\n");
378 dev->iobase = pci_resource_start(pci_dev, bar);
381 if (board->is_pcie) {
382 ret = dio200_pcie_board_setup(dev);
387 return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
390 static struct comedi_driver dio200_pci_comedi_driver = {
391 .driver_name = "amplc_dio200_pci",
392 .module = THIS_MODULE,
393 .auto_attach = dio200_pci_auto_attach,
394 .detach = comedi_pci_detach,
397 static const struct pci_device_id dio200_pci_table[] = {
398 { PCI_VDEVICE(AMPLICON, 0x000b), pci215_model },
399 { PCI_VDEVICE(AMPLICON, 0x000a), pci272_model },
400 { PCI_VDEVICE(AMPLICON, 0x0011), pcie236_model },
401 { PCI_VDEVICE(AMPLICON, 0x0012), pcie215_model },
402 { PCI_VDEVICE(AMPLICON, 0x0014), pcie296_model },
406 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
408 static int dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
410 return comedi_pci_auto_config(dev, &dio200_pci_comedi_driver,
414 static struct pci_driver dio200_pci_pci_driver = {
415 .name = "amplc_dio200_pci",
416 .id_table = dio200_pci_table,
417 .probe = dio200_pci_probe,
418 .remove = comedi_pci_auto_unconfig,
420 module_comedi_pci_driver(dio200_pci_comedi_driver, dio200_pci_pci_driver);
422 MODULE_AUTHOR("Comedi http://www.comedi.org");
423 MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series PCI(e) DIO boards");
424 MODULE_LICENSE("GPL");