drivers/spmi/spmi-pmic-arb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/bitmap.h>
   6 #include <linux/delay.h>
   7 #include <linux/err.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/irqchip/chained_irq.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18 #include <linux/spmi.h>
  19
  20 /* PMIC Arbiter configuration registers */
  21 #define PMIC_ARB_VERSION                0x0000
  22 #define PMIC_ARB_VERSION_V2_MIN         0x20010000
  23 #define PMIC_ARB_VERSION_V3_MIN         0x30000000
  24 #define PMIC_ARB_VERSION_V5_MIN         0x50000000
  25 #define PMIC_ARB_INT_EN                 0x0004
  26
  27 /* PMIC Arbiter channel registers offsets */
  28 #define PMIC_ARB_CMD                    0x00
  29 #define PMIC_ARB_CONFIG                 0x04
  30 #define PMIC_ARB_STATUS                 0x08
  31 #define PMIC_ARB_WDATA0                 0x10
  32 #define PMIC_ARB_WDATA1                 0x14
  33 #define PMIC_ARB_RDATA0                 0x18
  34 #define PMIC_ARB_RDATA1                 0x1C
  35
  36 /* Mapping Table */
  37 #define SPMI_MAPPING_TABLE_REG(N)       (0x0B00 + (4 * (N)))
  38 #define SPMI_MAPPING_BIT_INDEX(X)       (((X) >> 18) & 0xF)
  39 #define SPMI_MAPPING_BIT_IS_0_FLAG(X)   (((X) >> 17) & 0x1)
  40 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
  41 #define SPMI_MAPPING_BIT_IS_1_FLAG(X)   (((X) >> 8) & 0x1)
  42 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
  43
  44 #define SPMI_MAPPING_TABLE_TREE_DEPTH   16      /* Maximum of 16-bits */
  45 #define PMIC_ARB_MAX_PPID               BIT(12) /* PPID is 12bit */
  46 #define PMIC_ARB_APID_VALID             BIT(15)
  47 #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
  48 #define INVALID_EE                              0xFF
  49
  50 /* Ownership Table */
  51 #define SPMI_OWNERSHIP_TABLE_REG(N)     (0x0700 + (4 * (N)))
  52 #define SPMI_OWNERSHIP_PERIPH2OWNER(X)  ((X) & 0x7)
  53
  54 /* Channel Status fields */
  55 enum pmic_arb_chnl_status {
  56         PMIC_ARB_STATUS_DONE    = BIT(0),
  57         PMIC_ARB_STATUS_FAILURE = BIT(1),
  58         PMIC_ARB_STATUS_DENIED  = BIT(2),
  59         PMIC_ARB_STATUS_DROPPED = BIT(3),
  60 };
  61
  62 /* Command register fields */
  63 #define PMIC_ARB_CMD_MAX_BYTE_COUNT     8
  64
  65 /* Command Opcodes */
  66 enum pmic_arb_cmd_op_code {
  67         PMIC_ARB_OP_EXT_WRITEL = 0,
  68         PMIC_ARB_OP_EXT_READL = 1,
  69         PMIC_ARB_OP_EXT_WRITE = 2,
  70         PMIC_ARB_OP_RESET = 3,
  71         PMIC_ARB_OP_SLEEP = 4,
  72         PMIC_ARB_OP_SHUTDOWN = 5,
  73         PMIC_ARB_OP_WAKEUP = 6,
  74         PMIC_ARB_OP_AUTHENTICATE = 7,
  75         PMIC_ARB_OP_MSTR_READ = 8,
  76         PMIC_ARB_OP_MSTR_WRITE = 9,
  77         PMIC_ARB_OP_EXT_READ = 13,
  78         PMIC_ARB_OP_WRITE = 14,
  79         PMIC_ARB_OP_READ = 15,
  80         PMIC_ARB_OP_ZERO_WRITE = 16,
  81 };
  82
  83 /*
  84  * PMIC arbiter version 5 uses different register offsets for read/write vs
  85  * observer channels.
  86  */
  87 enum pmic_arb_channel {
  88         PMIC_ARB_CHANNEL_RW,
  89         PMIC_ARB_CHANNEL_OBS,
  90 };
  91
  92 /* Maximum number of support PMIC peripherals */
  93 #define PMIC_ARB_MAX_PERIPHS            512
  94 #define PMIC_ARB_TIMEOUT_US             100
  95 #define PMIC_ARB_MAX_TRANS_BYTES        (8)
  96
  97 #define PMIC_ARB_APID_MASK              0xFF
  98 #define PMIC_ARB_PPID_MASK              0xFFF
  99
 100 /* interrupt enable bit */
 101 #define SPMI_PIC_ACC_ENABLE_BIT         BIT(0)
 102
 103 #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
 104         ((((slave_id) & 0xF)   << 28) | \
 105         (((periph_id) & 0xFF)  << 20) | \
 106         (((irq_id)    & 0x7)   << 16) | \
 107         (((apid)      & 0x1FF) << 0))
 108
 109 #define hwirq_to_sid(hwirq)  (((hwirq) >> 28) & 0xF)
 110 #define hwirq_to_per(hwirq)  (((hwirq) >> 20) & 0xFF)
 111 #define hwirq_to_irq(hwirq)  (((hwirq) >> 16) & 0x7)
 112 #define hwirq_to_apid(hwirq) (((hwirq) >> 0)  & 0x1FF)
 113
 114 struct pmic_arb_ver_ops;
 115
 116 struct apid_data {
 117         u16             ppid;
 118         u8              write_ee;
 119         u8              irq_ee;
 120 };
 121
 122 /**
 123  * spmi_pmic_arb - SPMI PMIC Arbiter object
 124  *
 125  * @rd_base:            on v1 "core", on v2 "observer" register base off DT.
 126  * @wr_base:            on v1 "core", on v2 "chnls"    register base off DT.
 127  * @intr:               address of the SPMI interrupt control registers.
 128  * @cnfg:               address of the PMIC Arbiter configuration registers.
 129  * @lock:               lock to synchronize accesses.
 130  * @channel:            execution environment channel to use for accesses.
 131  * @irq:                PMIC ARB interrupt.
 132  * @ee:                 the current Execution Environment
 133  * @min_apid:           minimum APID (used for bounding IRQ search)
 134  * @max_apid:           maximum APID
 135  * @mapping_table:      in-memory copy of PPID -> APID mapping table.
 136  * @domain:             irq domain object for PMIC IRQ domain
 137  * @spmic:              SPMI controller object
 138  * @ver_ops:            version dependent operations.
 139  * @ppid_to_apid        in-memory copy of PPID -> APID mapping table.
 140  */
 141 struct spmi_pmic_arb {
 142         void __iomem            *rd_base;
 143         void __iomem            *wr_base;
 144         void __iomem            *intr;
 145         void __iomem            *cnfg;
 146         void __iomem            *core;
 147         resource_size_t         core_size;
 148         raw_spinlock_t          lock;
 149         u8                      channel;
 150         int                     irq;
 151         u8                      ee;
 152         u16                     min_apid;
 153         u16                     max_apid;
 154         u32                     *mapping_table;
 155         DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
 156         struct irq_domain       *domain;
 157         struct spmi_controller  *spmic;
 158         const struct pmic_arb_ver_ops *ver_ops;
 159         u16                     *ppid_to_apid;
 160         u16                     last_apid;
 161         struct apid_data        apid_data[PMIC_ARB_MAX_PERIPHS];
 162 };
 163
 164 /**
 165  * pmic_arb_ver: version dependent functionality.
 166  *
 167  * @ver_str:            version string.
 168  * @ppid_to_apid:       finds the apid for a given ppid.
 169  * @non_data_cmd:       on v1 issues an spmi non-data command.
 170  *                      on v2 no HW support, returns -EOPNOTSUPP.
 171  * @offset:             on v1 offset of per-ee channel.
 172  *                      on v2 offset of per-ee and per-ppid channel.
 173  * @fmt_cmd:            formats a GENI/SPMI command.
 174  * @owner_acc_status:   on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
 175  *                      on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
 176  * @acc_enable:         on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
 177  *                      on v2 address of SPMI_PIC_ACC_ENABLEn.
 178  * @irq_status:         on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
 179  *                      on v2 address of SPMI_PIC_IRQ_STATUSn.
 180  * @irq_clear:          on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
 181  *                      on v2 address of SPMI_PIC_IRQ_CLEARn.
 182  * @apid_map_offset:    offset of PMIC_ARB_REG_CHNLn
 183  */
 184 struct pmic_arb_ver_ops {
 185         const char *ver_str;
 186         int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
 187         /* spmi commands (read_cmd, write_cmd, cmd) functionality */
 188         int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 189                         enum pmic_arb_channel ch_type);
 190         u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
 191         int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
 192         /* Interrupts controller functionality (offset of PIC registers) */
 193         void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
 194                                           u16 n);
 195         void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
 196         void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
 197         void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
 198         u32 (*apid_map_offset)(u16 n);
 199 };
 200
 201 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
 202                                        u32 offset, u32 val)
 203 {
 204         writel_relaxed(val, pmic_arb->wr_base + offset);
 205 }
 206
 207 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
 208                                        u32 offset, u32 val)
 209 {
 210         writel_relaxed(val, pmic_arb->rd_base + offset);
 211 }
 212
 213 /**
 214  * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
 215  * @bc:         byte count -1. range: 0..3
 216  * @reg:        register's address
 217  * @buf:        output parameter, length must be bc + 1
 218  */
 219 static void
 220 pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
 221 {
 222         u32 data = __raw_readl(pmic_arb->rd_base + reg);
 223
 224         memcpy(buf, &data, (bc & 3) + 1);
 225 }
 226
 227 /**
 228  * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
 229  * @bc:         byte-count -1. range: 0..3.
 230  * @reg:        register's address.
 231  * @buf:        buffer to write. length must be bc + 1.
 232  */
 233 static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
 234                                 u32 reg, u8 bc)
 235 {
 236         u32 data = 0;
 237
 238         memcpy(&data, buf, (bc & 3) + 1);
 239         __raw_writel(data, pmic_arb->wr_base + reg);
 240 }
 241
 242 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
 243                                   void __iomem *base, u8 sid, u16 addr,
 244                                   enum pmic_arb_channel ch_type)
 245 {
 246         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 247         u32 status = 0;
 248         u32 timeout = PMIC_ARB_TIMEOUT_US;
 249         u32 offset;
 250         int rc;
 251
 252         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
 253         if (rc < 0)
 254                 return rc;
 255
 256         offset = rc;
 257         offset += PMIC_ARB_STATUS;
 258
 259         while (timeout--) {
 260                 status = readl_relaxed(base + offset);
 261
 262                 if (status & PMIC_ARB_STATUS_DONE) {
 263                         if (status & PMIC_ARB_STATUS_DENIED) {
 264                                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n",
 265                                         __func__, sid, addr, status);
 266                                 return -EPERM;
 267                         }
 268
 269                         if (status & PMIC_ARB_STATUS_FAILURE) {
 270                                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x)\n",
 271                                         __func__, sid, addr, status);
 272                                 WARN_ON(1);
 273                                 return -EIO;
 274                         }
 275
 276                         if (status & PMIC_ARB_STATUS_DROPPED) {
 277                                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n",
 278                                         __func__, sid, addr, status);
 279                                 return -EIO;
 280                         }
 281
 282                         return 0;
 283                 }
 284                 udelay(1);
 285         }
 286
 287         dev_err(&ctrl->dev, "%s: %#x %#x: timeout, status %#x\n",
 288                 __func__, sid, addr, status);
 289         return -ETIMEDOUT;
 290 }
 291
 292 static int
 293 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
 294 {
 295         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 296         unsigned long flags;
 297         u32 cmd;
 298         int rc;
 299         u32 offset;
 300
 301         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
 302         if (rc < 0)
 303                 return rc;
 304
 305         offset = rc;
 306         cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
 307
 308         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 309         pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 310         rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
 311                                     PMIC_ARB_CHANNEL_RW);
 312         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 313
 314         return rc;
 315 }
 316
 317 static int
 318 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
 319 {
 320         return -EOPNOTSUPP;
 321 }
 322
 323 /* Non-data command */
 324 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
 325 {
 326         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 327
 328         dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
 329
 330         /* Check for valid non-data command */
 331         if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
 332                 return -EINVAL;
 333
 334         return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
 335 }
 336
 337 static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u8 sid,
 338                                  u16 addr, size_t len, u32 *cmd, u32 *offset)
 339 {
 340         u8 bc = len - 1;
 341         int rc;
 342
 343         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
 344                                        PMIC_ARB_CHANNEL_OBS);
 345         if (rc < 0)
 346                 return rc;
 347
 348         *offset = rc;
 349         if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 350                 dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 351                         PMIC_ARB_MAX_TRANS_BYTES, len);
 352                 return  -EINVAL;
 353         }
 354
 355         /* Check the opcode */
 356         if (opc >= 0x60 && opc <= 0x7F)
 357                 opc = PMIC_ARB_OP_READ;
 358         else if (opc >= 0x20 && opc <= 0x2F)
 359                 opc = PMIC_ARB_OP_EXT_READ;
 360         else if (opc >= 0x38 && opc <= 0x3F)
 361                 opc = PMIC_ARB_OP_EXT_READL;
 362         else
 363                 return -EINVAL;
 364
 365         *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 366
 367         return 0;
 368 }
 369
 370 static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
 371                                       u32 offset, u8 sid, u16 addr, u8 *buf,
 372                                       size_t len)
 373 {
 374         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 375         u8 bc = len - 1;
 376         int rc;
 377
 378         pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 379         rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
 380                                     PMIC_ARB_CHANNEL_OBS);
 381         if (rc)
 382                 return rc;
 383
 384         pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
 385                      min_t(u8, bc, 3));
 386
 387         if (bc > 3)
 388                 pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
 389                                         bc - 4);
 390         return 0;
 391 }
 392
 393 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 394                              u16 addr, u8 *buf, size_t len)
 395 {
 396         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 397         unsigned long flags;
 398         u32 cmd, offset;
 399         int rc;
 400
 401         rc = pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd,
 402                                    &offset);
 403         if (rc)
 404                 return rc;
 405
 406         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 407         rc = pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len);
 408         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 409
 410         return rc;
 411 }
 412
 413 static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc,
 414                                   u8 sid, u16 addr, size_t len, u32 *cmd,
 415                                   u32 *offset)
 416 {
 417         u8 bc = len - 1;
 418         int rc;
 419
 420         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
 421                                         PMIC_ARB_CHANNEL_RW);
 422         if (rc < 0)
 423                 return rc;
 424
 425         *offset = rc;
 426         if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 427                 dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 428                         PMIC_ARB_MAX_TRANS_BYTES, len);
 429                 return  -EINVAL;
 430         }
 431
 432         /* Check the opcode */
 433         if (opc >= 0x40 && opc <= 0x5F)
 434                 opc = PMIC_ARB_OP_WRITE;
 435         else if (opc <= 0x0F)
 436                 opc = PMIC_ARB_OP_EXT_WRITE;
 437         else if (opc >= 0x30 && opc <= 0x37)
 438                 opc = PMIC_ARB_OP_EXT_WRITEL;
 439         else if (opc >= 0x80)
 440                 opc = PMIC_ARB_OP_ZERO_WRITE;
 441         else
 442                 return -EINVAL;
 443
 444         *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 445
 446         return 0;
 447 }
 448
 449 static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
 450                                       u32 offset, u8 sid, u16 addr,
 451                                       const u8 *buf, size_t len)
 452 {
 453         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 454         u8 bc = len - 1;
 455
 456         /* Write data to FIFOs */
 457         pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
 458                                 min_t(u8, bc, 3));
 459         if (bc > 3)
 460                 pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
 461                                         bc - 4);
 462
 463         /* Start the transaction */
 464         pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 465         return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
 466                                       PMIC_ARB_CHANNEL_RW);
 467 }
 468
 469 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 470                               u16 addr, const u8 *buf, size_t len)
 471 {
 472         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 473         unsigned long flags;
 474         u32 cmd, offset;
 475         int rc;
 476
 477         rc = pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd,
 478                                     &offset);
 479         if (rc)
 480                 return rc;
 481
 482         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 483         rc = pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf,
 484                                          len);
 485         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 486
 487         return rc;
 488 }
 489
 490 static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr,
 491                                  const u8 *buf, const u8 *mask, size_t len)
 492 {
 493         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 494         u32 read_cmd, read_offset, write_cmd, write_offset;
 495         u8 temp[PMIC_ARB_MAX_TRANS_BYTES];
 496         unsigned long flags;
 497         int rc, i;
 498
 499         rc = pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len,
 500                                    &read_cmd, &read_offset);
 501         if (rc)
 502                 return rc;
 503
 504         rc = pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr,
 505                                     len, &write_cmd, &write_offset);
 506         if (rc)
 507                 return rc;
 508
 509         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 510         rc = pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr,
 511                                         temp, len);
 512         if (rc)
 513                 goto done;
 514
 515         for (i = 0; i < len; i++)
 516                 temp[i] = (temp[i] & ~mask[i]) | (buf[i] & mask[i]);
 517
 518         rc = pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid,
 519                                          addr, temp, len);
 520 done:
 521         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 522
 523         return rc;
 524 }
 525
 526 enum qpnpint_regs {
 527         QPNPINT_REG_RT_STS              = 0x10,
 528         QPNPINT_REG_SET_TYPE            = 0x11,
 529         QPNPINT_REG_POLARITY_HIGH       = 0x12,
 530         QPNPINT_REG_POLARITY_LOW        = 0x13,
 531         QPNPINT_REG_LATCHED_CLR         = 0x14,
 532         QPNPINT_REG_EN_SET              = 0x15,
 533         QPNPINT_REG_EN_CLR              = 0x16,
 534         QPNPINT_REG_LATCHED_STS         = 0x18,
 535 };
 536
 537 struct spmi_pmic_arb_qpnpint_type {
 538         u8 type; /* 1 -> edge */
 539         u8 polarity_high;
 540         u8 polarity_low;
 541 } __packed;
 542
 543 /* Simplified accessor functions for irqchip callbacks */
 544 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
 545                                size_t len)
 546 {
 547         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 548         u8 sid = hwirq_to_sid(d->hwirq);
 549         u8 per = hwirq_to_per(d->hwirq);
 550
 551         if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
 552                                (per << 8) + reg, buf, len))
 553                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
 554                                     d->irq);
 555 }
 556
 557 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
 558 {
 559         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 560         u8 sid = hwirq_to_sid(d->hwirq);
 561         u8 per = hwirq_to_per(d->hwirq);
 562
 563         if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
 564                               (per << 8) + reg, buf, len))
 565                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
 566                                     d->irq);
 567 }
 568
 569 static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg,
 570                                      const void *buf, const void *mask,
 571                                      size_t len)
 572 {
 573         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 574         u8 sid = hwirq_to_sid(d->hwirq);
 575         u8 per = hwirq_to_per(d->hwirq);
 576         int rc;
 577
 578         rc = pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf,
 579                                    mask, len);
 580         if (rc)
 581                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x rc=%d\n",
 582                                     d->irq, rc);
 583         return rc;
 584 }
 585
 586 static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
 587 {
 588         u16 ppid = pmic_arb->apid_data[apid].ppid;
 589         u8 sid = ppid >> 8;
 590         u8 per = ppid & 0xFF;
 591         u8 irq_mask = BIT(id);
 592
 593         writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
 594
 595         if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
 596                         (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
 597                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
 598                                 irq_mask, ppid);
 599
 600         if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
 601                                (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
 602                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
 603                                 irq_mask, ppid);
 604 }
 605
 606 static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
 607 {
 608         unsigned int irq;
 609         u32 status, id;
 610         u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
 611         u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
 612
 613         status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
 614         while (status) {
 615                 id = ffs(status) - 1;
 616                 status &= ~BIT(id);
 617                 irq = irq_find_mapping(pmic_arb->domain,
 618                                         spec_to_hwirq(sid, per, id, apid));
 619                 if (irq == 0) {
 620                         cleanup_irq(pmic_arb, apid, id);
 621                         continue;
 622                 }
 623                 generic_handle_irq(irq);
 624         }
 625 }
 626
 627 static void pmic_arb_chained_irq(struct irq_desc *desc)
 628 {
 629         struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
 630         const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
 631         struct irq_chip *chip = irq_desc_get_chip(desc);
 632         int first = pmic_arb->min_apid >> 5;
 633         int last = pmic_arb->max_apid >> 5;
 634         u8 ee = pmic_arb->ee;
 635         u32 status, enable;
 636         int i, id, apid;
 637
 638         chained_irq_enter(chip, desc);
 639
 640         for (i = first; i <= last; ++i) {
 641                 status = readl_relaxed(
 642                                 ver_ops->owner_acc_status(pmic_arb, ee, i));
 643                 while (status) {
 644                         id = ffs(status) - 1;
 645                         status &= ~BIT(id);
 646                         apid = id + i * 32;
 647                         enable = readl_relaxed(
 648                                         ver_ops->acc_enable(pmic_arb, apid));
 649                         if (enable & SPMI_PIC_ACC_ENABLE_BIT)
 650                                 periph_interrupt(pmic_arb, apid);
 651                 }
 652         }
 653
 654         chained_irq_exit(chip, desc);
 655 }
 656
 657 static void qpnpint_irq_ack(struct irq_data *d)
 658 {
 659         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 660         u8 irq = hwirq_to_irq(d->hwirq);
 661         u16 apid = hwirq_to_apid(d->hwirq);
 662         u8 data;
 663
 664         writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
 665
 666         data = BIT(irq);
 667         qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
 668 }
 669
 670 static void qpnpint_irq_mask(struct irq_data *d)
 671 {
 672         u8 irq = hwirq_to_irq(d->hwirq);
 673         u8 data = BIT(irq);
 674
 675         qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
 676 }
 677
 678 static void qpnpint_irq_unmask(struct irq_data *d)
 679 {
 680         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 681         const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
 682         u8 irq = hwirq_to_irq(d->hwirq);
 683         u16 apid = hwirq_to_apid(d->hwirq);
 684         u8 buf[2];
 685
 686         writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
 687                         ver_ops->acc_enable(pmic_arb, apid));
 688
 689         qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
 690         if (!(buf[0] & BIT(irq))) {
 691                 /*
 692                  * Since the interrupt is currently disabled, write to both the
 693                  * LATCHED_CLR and EN_SET registers so that a spurious interrupt
 694                  * cannot be triggered when the interrupt is enabled
 695                  */
 696                 buf[0] = BIT(irq);
 697                 buf[1] = BIT(irq);
 698                 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
 699         }
 700 }
 701
 702 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
 703 {
 704         struct spmi_pmic_arb_qpnpint_type type = {0};
 705         struct spmi_pmic_arb_qpnpint_type mask;
 706         irq_flow_handler_t flow_handler;
 707         u8 irq_bit = BIT(hwirq_to_irq(d->hwirq));
 708         int rc;
 709
 710         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 711                 type.type = irq_bit;
 712                 if (flow_type & IRQF_TRIGGER_RISING)
 713                         type.polarity_high = irq_bit;
 714                 if (flow_type & IRQF_TRIGGER_FALLING)
 715                         type.polarity_low = irq_bit;
 716
 717                 flow_handler = handle_edge_irq;
 718         } else {
 719                 if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
 720                     (flow_type & (IRQF_TRIGGER_LOW)))
 721                         return -EINVAL;
 722
 723                 if (flow_type & IRQF_TRIGGER_HIGH)
 724                         type.polarity_high = irq_bit;
 725                 else
 726                         type.polarity_low = irq_bit;
 727
 728                 flow_handler = handle_level_irq;
 729         }
 730
 731         mask.type = irq_bit;
 732         mask.polarity_high = irq_bit;
 733         mask.polarity_low = irq_bit;
 734
 735         rc = qpnpint_spmi_masked_write(d, QPNPINT_REG_SET_TYPE, &type, &mask,
 736                                        sizeof(type));
 737         irq_set_handler_locked(d, flow_handler);
 738
 739         return rc;
 740 }
 741
 742 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
 743 {
 744         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 745
 746         return irq_set_irq_wake(pmic_arb->irq, on);
 747 }
 748
 749 static int qpnpint_get_irqchip_state(struct irq_data *d,
 750                                      enum irqchip_irq_state which,
 751                                      bool *state)
 752 {
 753         u8 irq = hwirq_to_irq(d->hwirq);
 754         u8 status = 0;
 755
 756         if (which != IRQCHIP_STATE_LINE_LEVEL)
 757                 return -EINVAL;
 758
 759         qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
 760         *state = !!(status & BIT(irq));
 761
 762         return 0;
 763 }
 764
 765 static int qpnpint_irq_domain_activate(struct irq_domain *domain,
 766                                        struct irq_data *d, bool reserve)
 767 {
 768         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 769         u16 periph = hwirq_to_per(d->hwirq);
 770         u16 apid = hwirq_to_apid(d->hwirq);
 771         u16 sid = hwirq_to_sid(d->hwirq);
 772         u16 irq = hwirq_to_irq(d->hwirq);
 773
 774         if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
 775                 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
 776                         sid, periph, irq, pmic_arb->ee,
 777                         pmic_arb->apid_data[apid].irq_ee);
 778                 return -ENODEV;
 779         }
 780
 781         return 0;
 782 }
 783
 784 static struct irq_chip pmic_arb_irqchip = {
 785         .name           = "pmic_arb",
 786         .irq_ack        = qpnpint_irq_ack,
 787         .irq_mask       = qpnpint_irq_mask,
 788         .irq_unmask     = qpnpint_irq_unmask,
 789         .irq_set_type   = qpnpint_irq_set_type,
 790         .irq_set_wake   = qpnpint_irq_set_wake,
 791         .irq_get_irqchip_state  = qpnpint_get_irqchip_state,
 792         .flags          = IRQCHIP_MASK_ON_SUSPEND,
 793 };
 794
 795 static int qpnpint_irq_domain_translate(struct irq_domain *d,
 796                                         struct irq_fwspec *fwspec,
 797                                         unsigned long *out_hwirq,
 798                                         unsigned int *out_type)
 799 {
 800         struct spmi_pmic_arb *pmic_arb = d->host_data;
 801         u32 *intspec = fwspec->param;
 802         u16 apid, ppid;
 803         int rc;
 804
 805         dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
 806                 intspec[0], intspec[1], intspec[2]);
 807
 808         if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
 809                 return -EINVAL;
 810         if (fwspec->param_count != 4)
 811                 return -EINVAL;
 812         if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
 813                 return -EINVAL;
 814
 815         ppid = intspec[0] << 8 | intspec[1];
 816         rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
 817         if (rc < 0) {
 818                 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
 819                 intspec[0], intspec[1], intspec[2], rc);
 820                 return rc;
 821         }
 822
 823         apid = rc;
 824         /* Keep track of {max,min}_apid for bounding search during interrupt */
 825         if (apid > pmic_arb->max_apid)
 826                 pmic_arb->max_apid = apid;
 827         if (apid < pmic_arb->min_apid)
 828                 pmic_arb->min_apid = apid;
 829
 830         *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
 831         *out_type  = intspec[3] & IRQ_TYPE_SENSE_MASK;
 832
 833         dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
 834
 835         return 0;
 836 }
 837
 838 static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;
 839
 840 static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
 841                                    struct irq_domain *domain, unsigned int virq,
 842                                    irq_hw_number_t hwirq, unsigned int type)
 843 {
 844         irq_flow_handler_t handler;
 845
 846         dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
 847                 virq, hwirq, type);
 848
 849         if (type & IRQ_TYPE_EDGE_BOTH)
 850                 handler = handle_edge_irq;
 851         else
 852                 handler = handle_level_irq;
 853
 854
 855         irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,
 856                               &qpnpint_irq_request_class);
 857         irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
 858                             handler, NULL, NULL);
 859 }
 860
 861 static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
 862                                     unsigned int virq, unsigned int nr_irqs,
 863                                     void *data)
 864 {
 865         struct spmi_pmic_arb *pmic_arb = domain->host_data;
 866         struct irq_fwspec *fwspec = data;
 867         irq_hw_number_t hwirq;
 868         unsigned int type;
 869         int ret, i;
 870
 871         ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);
 872         if (ret)
 873                 return ret;
 874
 875         for (i = 0; i < nr_irqs; i++)
 876                 qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
 877                                        type);
 878
 879         return 0;
 880 }
 881
 882 static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 883 {
 884         u32 *mapping_table = pmic_arb->mapping_table;
 885         int index = 0, i;
 886         u16 apid_valid;
 887         u16 apid;
 888         u32 data;
 889
 890         apid_valid = pmic_arb->ppid_to_apid[ppid];
 891         if (apid_valid & PMIC_ARB_APID_VALID) {
 892                 apid = apid_valid & ~PMIC_ARB_APID_VALID;
 893                 return apid;
 894         }
 895
 896         for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
 897                 if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
 898                         mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
 899                                                 SPMI_MAPPING_TABLE_REG(index));
 900
 901                 data = mapping_table[index];
 902
 903                 if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
 904                         if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
 905                                 index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 906                         } else {
 907                                 apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 908                                 pmic_arb->ppid_to_apid[ppid]
 909                                         = apid | PMIC_ARB_APID_VALID;
 910                                 pmic_arb->apid_data[apid].ppid = ppid;
 911                                 return apid;
 912                         }
 913                 } else {
 914                         if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
 915                                 index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 916                         } else {
 917                                 apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 918                                 pmic_arb->ppid_to_apid[ppid]
 919                                         = apid | PMIC_ARB_APID_VALID;
 920                                 pmic_arb->apid_data[apid].ppid = ppid;
 921                                 return apid;
 922                         }
 923                 }
 924         }
 925
 926         return -ENODEV;
 927 }
 928
 929 /* v1 offset per ee */
 930 static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 931                         enum pmic_arb_channel ch_type)
 932 {
 933         return 0x800 + 0x80 * pmic_arb->channel;
 934 }
 935
 936 static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 937 {
 938         struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
 939         u32 regval, offset;
 940         u16 id, apid;
 941
 942         for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
 943                 offset = pmic_arb->ver_ops->apid_map_offset(apid);
 944                 if (offset >= pmic_arb->core_size)
 945                         break;
 946
 947                 regval = readl_relaxed(pmic_arb->cnfg +
 948                                       SPMI_OWNERSHIP_TABLE_REG(apid));
 949                 apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
 950                 apidd->write_ee = apidd->irq_ee;
 951
 952                 regval = readl_relaxed(pmic_arb->core + offset);
 953                 if (!regval)
 954                         continue;
 955
 956                 id = (regval >> 8) & PMIC_ARB_PPID_MASK;
 957                 pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
 958                 apidd->ppid = id;
 959                 if (id == ppid) {
 960                         apid |= PMIC_ARB_APID_VALID;
 961                         break;
 962                 }
 963         }
 964         pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
 965
 966         return apid;
 967 }
 968
 969 static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 970 {
 971         u16 apid_valid;
 972
 973         apid_valid = pmic_arb->ppid_to_apid[ppid];
 974         if (!(apid_valid & PMIC_ARB_APID_VALID))
 975                 apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
 976         if (!(apid_valid & PMIC_ARB_APID_VALID))
 977                 return -ENODEV;
 978
 979         return apid_valid & ~PMIC_ARB_APID_VALID;
 980 }
 981
 982 static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
 983 {
 984         struct apid_data *apidd = pmic_arb->apid_data;
 985         struct apid_data *prev_apidd;
 986         u16 i, apid, ppid;
 987         bool valid, is_irq_ee;
 988         u32 regval, offset;
 989
 990         /*
 991          * In order to allow multiple EEs to write to a single PPID in arbiter
 992          * version 5, there is more than one APID mapped to each PPID.
 993          * The owner field for each of these mappings specifies the EE which is
 994          * allowed to write to the APID.  The owner of the last (highest) APID
 995          * for a given PPID will receive interrupts from the PPID.
 996          */
 997         for (i = 0; ; i++, apidd++) {
 998                 offset = pmic_arb->ver_ops->apid_map_offset(i);
 999                 if (offset >= pmic_arb->core_size)
1000                         break;
1001
1002                 regval = readl_relaxed(pmic_arb->core + offset);
1003                 if (!regval)
1004                         continue;
1005                 ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
1006                 is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
1007
1008                 regval = readl_relaxed(pmic_arb->cnfg +
1009                                       SPMI_OWNERSHIP_TABLE_REG(i));
1010                 apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
1011
1012                 apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
1013
1014                 valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
1015                 apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1016                 prev_apidd = &pmic_arb->apid_data[apid];
1017
1018                 if (valid && is_irq_ee &&
1019                                 prev_apidd->write_ee == pmic_arb->ee) {
1020                         /*
1021                          * Duplicate PPID mapping after the one for this EE;
1022                          * override the irq owner
1023                          */
1024                         prev_apidd->irq_ee = apidd->irq_ee;
1025                 } else if (!valid || is_irq_ee) {
1026                         /* First PPID mapping or duplicate for another EE */
1027                         pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
1028                 }
1029
1030                 apidd->ppid = ppid;
1031                 pmic_arb->last_apid = i;
1032         }
1033
1034         /* Dump the mapping table for debug purposes. */
1035         dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
1036         for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
1037                 apid = pmic_arb->ppid_to_apid[ppid];
1038                 if (apid & PMIC_ARB_APID_VALID) {
1039                         apid &= ~PMIC_ARB_APID_VALID;
1040                         apidd = &pmic_arb->apid_data[apid];
1041                         dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
1042                               ppid, apid, apidd->write_ee, apidd->irq_ee);
1043                 }
1044         }
1045
1046         return 0;
1047 }
1048
1049 static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
1050 {
1051         if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
1052                 return -ENODEV;
1053
1054         return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1055 }
1056
1057 /* v2 offset per ppid and per ee */
1058 static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1059                            enum pmic_arb_channel ch_type)
1060 {
1061         u16 apid;
1062         u16 ppid;
1063         int rc;
1064
1065         ppid = sid << 8 | ((addr >> 8) & 0xFF);
1066         rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
1067         if (rc < 0)
1068                 return rc;
1069
1070         apid = rc;
1071         return 0x1000 * pmic_arb->ee + 0x8000 * apid;
1072 }
1073
1074 /*
1075  * v5 offset per ee and per apid for observer channels and per apid for
1076  * read/write channels.
1077  */
1078 static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1079                            enum pmic_arb_channel ch_type)
1080 {
1081         u16 apid;
1082         int rc;
1083         u32 offset = 0;
1084         u16 ppid = (sid << 8) | (addr >> 8);
1085
1086         rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
1087         if (rc < 0)
1088                 return rc;
1089
1090         apid = rc;
1091         switch (ch_type) {
1092         case PMIC_ARB_CHANNEL_OBS:
1093                 offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
1094                 break;
1095         case PMIC_ARB_CHANNEL_RW:
1096                 offset = 0x10000 * apid;
1097                 break;
1098         }
1099
1100         return offset;
1101 }
1102
1103 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
1104 {
1105         return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
1106 }
1107
1108 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
1109 {
1110         return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
1111 }
1112
1113 static void __iomem *
1114 pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1115 {
1116         return pmic_arb->intr + 0x20 * m + 0x4 * n;
1117 }
1118
1119 static void __iomem *
1120 pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1121 {
1122         return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
1123 }
1124
1125 static void __iomem *
1126 pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1127 {
1128         return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
1129 }
1130
1131 static void __iomem *
1132 pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1133 {
1134         return pmic_arb->intr + 0x10000 * m + 0x4 * n;
1135 }
1136
1137 static void __iomem *
1138 pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1139 {
1140         return pmic_arb->intr + 0x200 + 0x4 * n;
1141 }
1142
1143 static void __iomem *
1144 pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1145 {
1146         return pmic_arb->intr + 0x1000 * n;
1147 }
1148
1149 static void __iomem *
1150 pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1151 {
1152         return pmic_arb->wr_base + 0x100 + 0x10000 * n;
1153 }
1154
1155 static void __iomem *
1156 pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1157 {
1158         return pmic_arb->intr + 0x600 + 0x4 * n;
1159 }
1160
1161 static void __iomem *
1162 pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1163 {
1164         return pmic_arb->intr + 0x4 + 0x1000 * n;
1165 }
1166
1167 static void __iomem *
1168 pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1169 {
1170         return pmic_arb->wr_base + 0x104 + 0x10000 * n;
1171 }
1172
1173 static void __iomem *
1174 pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1175 {
1176         return pmic_arb->intr + 0xA00 + 0x4 * n;
1177 }
1178
1179 static void __iomem *
1180 pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1181 {
1182         return pmic_arb->intr + 0x8 + 0x1000 * n;
1183 }
1184
1185 static void __iomem *
1186 pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1187 {
1188         return pmic_arb->wr_base + 0x108 + 0x10000 * n;
1189 }
1190
1191 static u32 pmic_arb_apid_map_offset_v2(u16 n)
1192 {
1193         return 0x800 + 0x4 * n;
1194 }
1195
1196 static u32 pmic_arb_apid_map_offset_v5(u16 n)
1197 {
1198         return 0x900 + 0x4 * n;
1199 }
1200
1201 static const struct pmic_arb_ver_ops pmic_arb_v1 = {
1202         .ver_str                = "v1",
1203         .ppid_to_apid           = pmic_arb_ppid_to_apid_v1,
1204         .non_data_cmd           = pmic_arb_non_data_cmd_v1,
1205         .offset                 = pmic_arb_offset_v1,
1206         .fmt_cmd                = pmic_arb_fmt_cmd_v1,
1207         .owner_acc_status       = pmic_arb_owner_acc_status_v1,
1208         .acc_enable             = pmic_arb_acc_enable_v1,
1209         .irq_status             = pmic_arb_irq_status_v1,
1210         .irq_clear              = pmic_arb_irq_clear_v1,
1211         .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1212 };
1213
1214 static const struct pmic_arb_ver_ops pmic_arb_v2 = {
1215         .ver_str                = "v2",
1216         .ppid_to_apid           = pmic_arb_ppid_to_apid_v2,
1217         .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1218         .offset                 = pmic_arb_offset_v2,
1219         .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1220         .owner_acc_status       = pmic_arb_owner_acc_status_v2,
1221         .acc_enable             = pmic_arb_acc_enable_v2,
1222         .irq_status             = pmic_arb_irq_status_v2,
1223         .irq_clear              = pmic_arb_irq_clear_v2,
1224         .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1225 };
1226
1227 static const struct pmic_arb_ver_ops pmic_arb_v3 = {
1228         .ver_str                = "v3",
1229         .ppid_to_apid           = pmic_arb_ppid_to_apid_v2,
1230         .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1231         .offset                 = pmic_arb_offset_v2,
1232         .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1233         .owner_acc_status       = pmic_arb_owner_acc_status_v3,
1234         .acc_enable             = pmic_arb_acc_enable_v2,
1235         .irq_status             = pmic_arb_irq_status_v2,
1236         .irq_clear              = pmic_arb_irq_clear_v2,
1237         .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1238 };
1239
1240 static const struct pmic_arb_ver_ops pmic_arb_v5 = {
1241         .ver_str                = "v5",
1242         .ppid_to_apid           = pmic_arb_ppid_to_apid_v5,
1243         .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1244         .offset                 = pmic_arb_offset_v5,
1245         .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1246         .owner_acc_status       = pmic_arb_owner_acc_status_v5,
1247         .acc_enable             = pmic_arb_acc_enable_v5,
1248         .irq_status             = pmic_arb_irq_status_v5,
1249         .irq_clear              = pmic_arb_irq_clear_v5,
1250         .apid_map_offset        = pmic_arb_apid_map_offset_v5,
1251 };
1252
1253 static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
1254         .activate = qpnpint_irq_domain_activate,
1255         .alloc = qpnpint_irq_domain_alloc,
1256         .free = irq_domain_free_irqs_common,
1257         .translate = qpnpint_irq_domain_translate,
1258 };
1259
1260 static int spmi_pmic_arb_probe(struct platform_device *pdev)
1261 {
1262         struct spmi_pmic_arb *pmic_arb;
1263         struct spmi_controller *ctrl;
1264         struct resource *res;
1265         void __iomem *core;
1266         u32 *mapping_table;
1267         u32 channel, ee, hw_ver;
1268         int err;
1269
1270         ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
1271         if (!ctrl)
1272                 return -ENOMEM;
1273
1274         pmic_arb = spmi_controller_get_drvdata(ctrl);
1275         pmic_arb->spmic = ctrl;
1276
1277         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
1278         core = devm_ioremap_resource(&ctrl->dev, res);
1279         if (IS_ERR(core)) {
1280                 err = PTR_ERR(core);
1281                 goto err_put_ctrl;
1282         }
1283
1284         pmic_arb->core_size = resource_size(res);
1285
1286         pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
1287                                               sizeof(*pmic_arb->ppid_to_apid),
1288                                               GFP_KERNEL);
1289         if (!pmic_arb->ppid_to_apid) {
1290                 err = -ENOMEM;
1291                 goto err_put_ctrl;
1292         }
1293
1294         hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
1295
1296         if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
1297                 pmic_arb->ver_ops = &pmic_arb_v1;
1298                 pmic_arb->wr_base = core;
1299                 pmic_arb->rd_base = core;
1300         } else {
1301                 pmic_arb->core = core;
1302
1303                 if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
1304                         pmic_arb->ver_ops = &pmic_arb_v2;
1305                 else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
1306                         pmic_arb->ver_ops = &pmic_arb_v3;
1307                 else
1308                         pmic_arb->ver_ops = &pmic_arb_v5;
1309
1310                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1311                                                    "obsrvr");
1312                 pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
1313                 if (IS_ERR(pmic_arb->rd_base)) {
1314                         err = PTR_ERR(pmic_arb->rd_base);
1315                         goto err_put_ctrl;
1316                 }
1317
1318                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1319                                                    "chnls");
1320                 pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
1321                 if (IS_ERR(pmic_arb->wr_base)) {
1322                         err = PTR_ERR(pmic_arb->wr_base);
1323                         goto err_put_ctrl;
1324                 }
1325         }
1326
1327         dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
1328                  pmic_arb->ver_ops->ver_str, hw_ver);
1329
1330         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
1331         pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
1332         if (IS_ERR(pmic_arb->intr)) {
1333                 err = PTR_ERR(pmic_arb->intr);
1334                 goto err_put_ctrl;
1335         }
1336
1337         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
1338         pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
1339         if (IS_ERR(pmic_arb->cnfg)) {
1340                 err = PTR_ERR(pmic_arb->cnfg);
1341                 goto err_put_ctrl;
1342         }
1343
1344         pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
1345         if (pmic_arb->irq < 0) {
1346                 err = pmic_arb->irq;
1347                 goto err_put_ctrl;
1348         }
1349
1350         err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
1351         if (err) {
1352                 dev_err(&pdev->dev, "channel unspecified.\n");
1353                 goto err_put_ctrl;
1354         }
1355
1356         if (channel > 5) {
1357                 dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
1358                         channel);
1359                 err = -EINVAL;
1360                 goto err_put_ctrl;
1361         }
1362
1363         pmic_arb->channel = channel;
1364
1365         err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
1366         if (err) {
1367                 dev_err(&pdev->dev, "EE unspecified.\n");
1368                 goto err_put_ctrl;
1369         }
1370
1371         if (ee > 5) {
1372                 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
1373                 err = -EINVAL;
1374                 goto err_put_ctrl;
1375         }
1376
1377         pmic_arb->ee = ee;
1378         mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
1379                                         sizeof(*mapping_table), GFP_KERNEL);
1380         if (!mapping_table) {
1381                 err = -ENOMEM;
1382                 goto err_put_ctrl;
1383         }
1384
1385         pmic_arb->mapping_table = mapping_table;
1386         /* Initialize max_apid/min_apid to the opposite bounds, during
1387          * the irq domain translation, we are sure to update these */
1388         pmic_arb->max_apid = 0;
1389         pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
1390
1391         platform_set_drvdata(pdev, ctrl);
1392         raw_spin_lock_init(&pmic_arb->lock);
1393
1394         ctrl->cmd = pmic_arb_cmd;
1395         ctrl->read_cmd = pmic_arb_read_cmd;
1396         ctrl->write_cmd = pmic_arb_write_cmd;
1397
1398         if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
1399                 err = pmic_arb_read_apid_map_v5(pmic_arb);
1400                 if (err) {
1401                         dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
1402                                 err);
1403                         goto err_put_ctrl;
1404                 }
1405         }
1406
1407         dev_dbg(&pdev->dev, "adding irq domain\n");
1408         pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
1409                                          &pmic_arb_irq_domain_ops, pmic_arb);
1410         if (!pmic_arb->domain) {
1411                 dev_err(&pdev->dev, "unable to create irq_domain\n");
1412                 err = -ENOMEM;
1413                 goto err_put_ctrl;
1414         }
1415
1416         irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
1417                                         pmic_arb);
1418         err = spmi_controller_add(ctrl);
1419         if (err)
1420                 goto err_domain_remove;
1421
1422         return 0;
1423
1424 err_domain_remove:
1425         irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1426         irq_domain_remove(pmic_arb->domain);
1427 err_put_ctrl:
1428         spmi_controller_put(ctrl);
1429         return err;
1430 }
1431
1432 static int spmi_pmic_arb_remove(struct platform_device *pdev)
1433 {
1434         struct spmi_controller *ctrl = platform_get_drvdata(pdev);
1435         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
1436         spmi_controller_remove(ctrl);
1437         irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1438         irq_domain_remove(pmic_arb->domain);
1439         spmi_controller_put(ctrl);
1440         return 0;
1441 }
1442
1443 static const struct of_device_id spmi_pmic_arb_match_table[] = {
1444         { .compatible = "qcom,spmi-pmic-arb", },
1445         {},
1446 };
1447 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
1448
1449 static struct platform_driver spmi_pmic_arb_driver = {
1450         .probe          = spmi_pmic_arb_probe,
1451         .remove         = spmi_pmic_arb_remove,
1452         .driver         = {
1453                 .name   = "spmi_pmic_arb",
1454                 .of_match_table = spmi_pmic_arb_match_table,
1455         },
1456 };
1457 module_platform_driver(spmi_pmic_arb_driver);
1458
1459 MODULE_LICENSE("GPL v2");
1460 MODULE_ALIAS("platform:spmi_pmic_arb");