drivers/spi/spi-zynqmp-gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
   4  * (master mode only)
   5  *
   6  * Copyright (C) 2009 - 2015 Xilinx, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/firmware/xlnx-zynqmp.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_address.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24
  25 /* Generic QSPI register offsets */
  26 #define GQSPI_CONFIG_OFST               0x00000100
  27 #define GQSPI_ISR_OFST                  0x00000104
  28 #define GQSPI_IDR_OFST                  0x0000010C
  29 #define GQSPI_IER_OFST                  0x00000108
  30 #define GQSPI_IMASK_OFST                0x00000110
  31 #define GQSPI_EN_OFST                   0x00000114
  32 #define GQSPI_TXD_OFST                  0x0000011C
  33 #define GQSPI_RXD_OFST                  0x00000120
  34 #define GQSPI_TX_THRESHOLD_OFST         0x00000128
  35 #define GQSPI_RX_THRESHOLD_OFST         0x0000012C
  36 #define GQSPI_LPBK_DLY_ADJ_OFST         0x00000138
  37 #define GQSPI_GEN_FIFO_OFST             0x00000140
  38 #define GQSPI_SEL_OFST                  0x00000144
  39 #define GQSPI_GF_THRESHOLD_OFST         0x00000150
  40 #define GQSPI_FIFO_CTRL_OFST            0x0000014C
  41 #define GQSPI_QSPIDMA_DST_CTRL_OFST     0x0000080C
  42 #define GQSPI_QSPIDMA_DST_SIZE_OFST     0x00000804
  43 #define GQSPI_QSPIDMA_DST_STS_OFST      0x00000808
  44 #define GQSPI_QSPIDMA_DST_I_STS_OFST    0x00000814
  45 #define GQSPI_QSPIDMA_DST_I_EN_OFST     0x00000818
  46 #define GQSPI_QSPIDMA_DST_I_DIS_OFST    0x0000081C
  47 #define GQSPI_QSPIDMA_DST_I_MASK_OFST   0x00000820
  48 #define GQSPI_QSPIDMA_DST_ADDR_OFST     0x00000800
  49 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
  50
  51 /* GQSPI register bit masks */
  52 #define GQSPI_SEL_MASK                          0x00000001
  53 #define GQSPI_EN_MASK                           0x00000001
  54 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK        0x00000020
  55 #define GQSPI_ISR_WR_TO_CLR_MASK                0x00000002
  56 #define GQSPI_IDR_ALL_MASK                      0x00000FBE
  57 #define GQSPI_CFG_MODE_EN_MASK                  0xC0000000
  58 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK      0x20000000
  59 #define GQSPI_CFG_ENDIAN_MASK                   0x04000000
  60 #define GQSPI_CFG_EN_POLL_TO_MASK               0x00100000
  61 #define GQSPI_CFG_WP_HOLD_MASK                  0x00080000
  62 #define GQSPI_CFG_BAUD_RATE_DIV_MASK            0x00000038
  63 #define GQSPI_CFG_CLK_PHA_MASK                  0x00000004
  64 #define GQSPI_CFG_CLK_POL_MASK                  0x00000002
  65 #define GQSPI_CFG_START_GEN_FIFO_MASK           0x10000000
  66 #define GQSPI_GENFIFO_IMM_DATA_MASK             0x000000FF
  67 #define GQSPI_GENFIFO_DATA_XFER                 0x00000100
  68 #define GQSPI_GENFIFO_EXP                       0x00000200
  69 #define GQSPI_GENFIFO_MODE_SPI                  0x00000400
  70 #define GQSPI_GENFIFO_MODE_DUALSPI              0x00000800
  71 #define GQSPI_GENFIFO_MODE_QUADSPI              0x00000C00
  72 #define GQSPI_GENFIFO_MODE_MASK                 0x00000C00
  73 #define GQSPI_GENFIFO_CS_LOWER                  0x00001000
  74 #define GQSPI_GENFIFO_CS_UPPER                  0x00002000
  75 #define GQSPI_GENFIFO_BUS_LOWER                 0x00004000
  76 #define GQSPI_GENFIFO_BUS_UPPER                 0x00008000
  77 #define GQSPI_GENFIFO_BUS_BOTH                  0x0000C000
  78 #define GQSPI_GENFIFO_BUS_MASK                  0x0000C000
  79 #define GQSPI_GENFIFO_TX                        0x00010000
  80 #define GQSPI_GENFIFO_RX                        0x00020000
  81 #define GQSPI_GENFIFO_STRIPE                    0x00040000
  82 #define GQSPI_GENFIFO_POLL                      0x00080000
  83 #define GQSPI_GENFIFO_EXP_START                 0x00000100
  84 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK        0x00000004
  85 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK        0x00000002
  86 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK       0x00000001
  87 #define GQSPI_ISR_RXEMPTY_MASK                  0x00000800
  88 #define GQSPI_ISR_GENFIFOFULL_MASK              0x00000400
  89 #define GQSPI_ISR_GENFIFONOT_FULL_MASK          0x00000200
  90 #define GQSPI_ISR_TXEMPTY_MASK                  0x00000100
  91 #define GQSPI_ISR_GENFIFOEMPTY_MASK             0x00000080
  92 #define GQSPI_ISR_RXFULL_MASK                   0x00000020
  93 #define GQSPI_ISR_RXNEMPTY_MASK                 0x00000010
  94 #define GQSPI_ISR_TXFULL_MASK                   0x00000008
  95 #define GQSPI_ISR_TXNOT_FULL_MASK               0x00000004
  96 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK         0x00000002
  97 #define GQSPI_IER_TXNOT_FULL_MASK               0x00000004
  98 #define GQSPI_IER_RXEMPTY_MASK                  0x00000800
  99 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK         0x00000002
 100 #define GQSPI_IER_RXNEMPTY_MASK                 0x00000010
 101 #define GQSPI_IER_GENFIFOEMPTY_MASK             0x00000080
 102 #define GQSPI_IER_TXEMPTY_MASK                  0x00000100
 103 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK         0x000000FE
 104 #define GQSPI_QSPIDMA_DST_STS_WTC               0x0000E000
 105 #define GQSPI_CFG_MODE_EN_DMA_MASK              0x80000000
 106 #define GQSPI_ISR_IDR_MASK                      0x00000994
 107 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK        0x00000002
 108 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK       0x00000002
 109 #define GQSPI_IRQ_MASK                          0x00000980
 110
 111 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT           3
 112 #define GQSPI_GENFIFO_CS_SETUP                  0x4
 113 #define GQSPI_GENFIFO_CS_HOLD                   0x3
 114 #define GQSPI_TXD_DEPTH                         64
 115 #define GQSPI_RX_FIFO_THRESHOLD                 32
 116 #define GQSPI_RX_FIFO_FILL      (GQSPI_RX_FIFO_THRESHOLD * 4)
 117 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL       32
 118 #define GQSPI_TX_FIFO_FILL      (GQSPI_TXD_DEPTH -\
 119                                 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
 120 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL      0X10
 121 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL        0x803FFA00
 122 #define GQSPI_SELECT_FLASH_CS_LOWER             0x1
 123 #define GQSPI_SELECT_FLASH_CS_UPPER             0x2
 124 #define GQSPI_SELECT_FLASH_CS_BOTH              0x3
 125 #define GQSPI_SELECT_FLASH_BUS_LOWER            0x1
 126 #define GQSPI_SELECT_FLASH_BUS_UPPER            0x2
 127 #define GQSPI_SELECT_FLASH_BUS_BOTH             0x3
 128 #define GQSPI_BAUD_DIV_MAX      7       /* Baud rate divisor maximum */
 129 #define GQSPI_BAUD_DIV_SHIFT    2       /* Baud rate divisor shift */
 130 #define GQSPI_SELECT_MODE_SPI           0x1
 131 #define GQSPI_SELECT_MODE_DUALSPI       0x2
 132 #define GQSPI_SELECT_MODE_QUADSPI       0x4
 133 #define GQSPI_DMA_UNALIGN               0x3
 134 #define GQSPI_DEFAULT_NUM_CS    1       /* Default number of chip selects */
 135
 136 #define SPI_AUTOSUSPEND_TIMEOUT         3000
 137 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
 138
 139 /**
 140  * struct zynqmp_qspi - Defines qspi driver instance
 141  * @regs:               Virtual address of the QSPI controller registers
 142  * @refclk:             Pointer to the peripheral clock
 143  * @pclk:               Pointer to the APB clock
 144  * @irq:                IRQ number
 145  * @dev:                Pointer to struct device
 146  * @txbuf:              Pointer to the TX buffer
 147  * @rxbuf:              Pointer to the RX buffer
 148  * @bytes_to_transfer:  Number of bytes left to transfer
 149  * @bytes_to_receive:   Number of bytes left to receive
 150  * @genfifocs:          Used for chip select
 151  * @genfifobus:         Used to select the upper or lower bus
 152  * @dma_rx_bytes:       Remaining bytes to receive by DMA mode
 153  * @dma_addr:           DMA address after mapping the kernel buffer
 154  * @genfifoentry:       Used for storing the genfifoentry instruction.
 155  * @mode:               Defines the mode in which QSPI is operating
 156  */
 157 struct zynqmp_qspi {
 158         void __iomem *regs;
 159         struct clk *refclk;
 160         struct clk *pclk;
 161         int irq;
 162         struct device *dev;
 163         const void *txbuf;
 164         void *rxbuf;
 165         int bytes_to_transfer;
 166         int bytes_to_receive;
 167         u32 genfifocs;
 168         u32 genfifobus;
 169         u32 dma_rx_bytes;
 170         dma_addr_t dma_addr;
 171         u32 genfifoentry;
 172         enum mode_type mode;
 173 };
 174
 175 /**
 176  * zynqmp_gqspi_read:   For GQSPI controller read operation
 177  * @xqspi:      Pointer to the zynqmp_qspi structure
 178  * @offset:     Offset from where to read
 179  */
 180 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
 181 {
 182         return readl_relaxed(xqspi->regs + offset);
 183 }
 184
 185 /**
 186  * zynqmp_gqspi_write:  For GQSPI controller write operation
 187  * @xqspi:      Pointer to the zynqmp_qspi structure
 188  * @offset:     Offset where to write
 189  * @val:        Value to be written
 190  */
 191 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
 192                                       u32 val)
 193 {
 194         writel_relaxed(val, (xqspi->regs + offset));
 195 }
 196
 197 /**
 198  * zynqmp_gqspi_selectslave:    For selection of slave device
 199  * @instanceptr:        Pointer to the zynqmp_qspi structure
 200  * @slavecs:    For chip select
 201  * @slavebus:   To check which bus is selected- upper or lower
 202  */
 203 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
 204                                      u8 slavecs, u8 slavebus)
 205 {
 206         /*
 207          * Bus and CS lines selected here will be updated in the instance and
 208          * used for subsequent GENFIFO entries during transfer.
 209          */
 210
 211         /* Choose slave select line */
 212         switch (slavecs) {
 213         case GQSPI_SELECT_FLASH_CS_BOTH:
 214                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
 215                         GQSPI_GENFIFO_CS_UPPER;
 216                 break;
 217         case GQSPI_SELECT_FLASH_CS_UPPER:
 218                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
 219                 break;
 220         case GQSPI_SELECT_FLASH_CS_LOWER:
 221                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 222                 break;
 223         default:
 224                 dev_warn(instanceptr->dev, "Invalid slave select\n");
 225         }
 226
 227         /* Choose the bus */
 228         switch (slavebus) {
 229         case GQSPI_SELECT_FLASH_BUS_BOTH:
 230                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
 231                         GQSPI_GENFIFO_BUS_UPPER;
 232                 break;
 233         case GQSPI_SELECT_FLASH_BUS_UPPER:
 234                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
 235                 break;
 236         case GQSPI_SELECT_FLASH_BUS_LOWER:
 237                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 238                 break;
 239         default:
 240                 dev_warn(instanceptr->dev, "Invalid slave bus\n");
 241         }
 242 }
 243
 244 /**
 245  * zynqmp_qspi_init_hw: Initialize the hardware
 246  * @xqspi:      Pointer to the zynqmp_qspi structure
 247  *
 248  * The default settings of the QSPI controller's configurable parameters on
 249  * reset are
 250  *      - Master mode
 251  *      - TX threshold set to 1
 252  *      - RX threshold set to 1
 253  *      - Flash memory interface mode enabled
 254  * This function performs the following actions
 255  *      - Disable and clear all the interrupts
 256  *      - Enable manual slave select
 257  *      - Enable manual start
 258  *      - Deselect all the chip select lines
 259  *      - Set the little endian mode of TX FIFO and
 260  *      - Enable the QSPI controller
 261  */
 262 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 263 {
 264         u32 config_reg;
 265
 266         /* Select the GQSPI mode */
 267         zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
 268         /* Clear and disable interrupts */
 269         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
 270                            zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
 271                            GQSPI_ISR_WR_TO_CLR_MASK);
 272         /* Clear the DMA STS */
 273         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 274                            zynqmp_gqspi_read(xqspi,
 275                                              GQSPI_QSPIDMA_DST_I_STS_OFST));
 276         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
 277                            zynqmp_gqspi_read(xqspi,
 278                                              GQSPI_QSPIDMA_DST_STS_OFST) |
 279                                              GQSPI_QSPIDMA_DST_STS_WTC);
 280         zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
 281         zynqmp_gqspi_write(xqspi,
 282                            GQSPI_QSPIDMA_DST_I_DIS_OFST,
 283                            GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
 284         /* Disable the GQSPI */
 285         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 286         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 287         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 288         /* Manual start */
 289         config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
 290         /* Little endian by default */
 291         config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
 292         /* Disable poll time out */
 293         config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
 294         /* Set hold bit */
 295         config_reg |= GQSPI_CFG_WP_HOLD_MASK;
 296         /* Clear pre-scalar by default */
 297         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 298         /* CPHA 0 */
 299         config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
 300         /* CPOL 0 */
 301         config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
 302         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 303
 304         /* Clear the TX and RX FIFO */
 305         zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
 306                            GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
 307                            GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
 308                            GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
 309         /* Set by default to allow for high frequencies */
 310         zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
 311                            zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
 312                            GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 313         /* Reset thresholds */
 314         zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
 315                            GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
 316         zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
 317                            GQSPI_RX_FIFO_THRESHOLD);
 318         zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
 319                            GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
 320         zynqmp_gqspi_selectslave(xqspi,
 321                                  GQSPI_SELECT_FLASH_CS_LOWER,
 322                                  GQSPI_SELECT_FLASH_BUS_LOWER);
 323         /* Initialize DMA */
 324         zynqmp_gqspi_write(xqspi,
 325                         GQSPI_QSPIDMA_DST_CTRL_OFST,
 326                         GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
 327
 328         /* Enable the GQSPI */
 329         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 330 }
 331
 332 /**
 333  * zynqmp_qspi_copy_read_data:  Copy data to RX buffer
 334  * @xqspi:      Pointer to the zynqmp_qspi structure
 335  * @data:       The variable where data is stored
 336  * @size:       Number of bytes to be copied from data to RX buffer
 337  */
 338 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
 339                                        ulong data, u8 size)
 340 {
 341         memcpy(xqspi->rxbuf, &data, size);
 342         xqspi->rxbuf += size;
 343         xqspi->bytes_to_receive -= size;
 344 }
 345
 346 /**
 347  * zynqmp_prepare_transfer_hardware:    Prepares hardware for transfer.
 348  * @master:     Pointer to the spi_master structure which provides
 349  *              information about the controller.
 350  *
 351  * This function enables SPI master controller.
 352  *
 353  * Return:      0 on success; error value otherwise
 354  */
 355 static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
 356 {
 357         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 358
 359         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 360         return 0;
 361 }
 362
 363 /**
 364  * zynqmp_unprepare_transfer_hardware:  Relaxes hardware after transfer
 365  * @master:     Pointer to the spi_master structure which provides
 366  *              information about the controller.
 367  *
 368  * This function disables the SPI master controller.
 369  *
 370  * Return:      Always 0
 371  */
 372 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
 373 {
 374         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 375
 376         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 377         return 0;
 378 }
 379
 380 /**
 381  * zynqmp_qspi_chipselect:      Select or deselect the chip select line
 382  * @qspi:       Pointer to the spi_device structure
 383  * @is_high:    Select(0) or deselect (1) the chip select line
 384  */
 385 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
 386 {
 387         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 388         ulong timeout;
 389         u32 genfifoentry = 0x0, statusreg;
 390
 391         genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 392         genfifoentry |= xqspi->genfifobus;
 393
 394         if (!is_high) {
 395                 genfifoentry |= xqspi->genfifocs;
 396                 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
 397         } else {
 398                 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
 399         }
 400
 401         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 402
 403         /* Manually start the generic FIFO command */
 404         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 405                         zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 406                         GQSPI_CFG_START_GEN_FIFO_MASK);
 407
 408         timeout = jiffies + msecs_to_jiffies(1000);
 409
 410         /* Wait until the generic FIFO command is empty */
 411         do {
 412                 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 413
 414                 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
 415                         (statusreg & GQSPI_ISR_TXEMPTY_MASK))
 416                         break;
 417                 else
 418                         cpu_relax();
 419         } while (!time_after_eq(jiffies, timeout));
 420
 421         if (time_after_eq(jiffies, timeout))
 422                 dev_err(xqspi->dev, "Chip select timed out\n");
 423 }
 424
 425 /**
 426  * zynqmp_qspi_setup_transfer:  Configure QSPI controller for specified
 427  *                              transfer
 428  * @qspi:       Pointer to the spi_device structure
 429  * @transfer:   Pointer to the spi_transfer structure which provides
 430  *              information about next transfer setup parameters
 431  *
 432  * Sets the operational mode of QSPI controller for the next QSPI transfer and
 433  * sets the requested clock frequency.
 434  *
 435  * Return:      Always 0
 436  *
 437  * Note:
 438  *      If the requested frequency is not an exact match with what can be
 439  *      obtained using the pre-scalar value, the driver sets the clock
 440  *      frequency which is lower than the requested frequency (maximum lower)
 441  *      for the transfer.
 442  *
 443  *      If the requested frequency is higher or lower than that is supported
 444  *      by the QSPI controller the driver will set the highest or lowest
 445  *      frequency supported by controller.
 446  */
 447 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
 448                                       struct spi_transfer *transfer)
 449 {
 450         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 451         ulong clk_rate;
 452         u32 config_reg, req_hz, baud_rate_val = 0;
 453
 454         if (transfer)
 455                 req_hz = transfer->speed_hz;
 456         else
 457                 req_hz = qspi->max_speed_hz;
 458
 459         /* Set the clock frequency */
 460         /* If req_hz == 0, default to lowest speed */
 461         clk_rate = clk_get_rate(xqspi->refclk);
 462
 463         while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
 464                (clk_rate /
 465                 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
 466                 baud_rate_val++;
 467
 468         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 469
 470         /* Set the QSPI clock phase and clock polarity */
 471         config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
 472
 473         if (qspi->mode & SPI_CPHA)
 474                 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
 475         if (qspi->mode & SPI_CPOL)
 476                 config_reg |= GQSPI_CFG_CLK_POL_MASK;
 477
 478         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 479         config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
 480         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 481         return 0;
 482 }
 483
 484 /**
 485  * zynqmp_qspi_setup:   Configure the QSPI controller
 486  * @qspi:       Pointer to the spi_device structure
 487  *
 488  * Sets the operational mode of QSPI controller for the next QSPI transfer,
 489  * baud rate and divisor value to setup the requested qspi clock.
 490  *
 491  * Return:      0 on success; error value otherwise.
 492  */
 493 static int zynqmp_qspi_setup(struct spi_device *qspi)
 494 {
 495         if (qspi->master->busy)
 496                 return -EBUSY;
 497         return 0;
 498 }
 499
 500 /**
 501  * zynqmp_qspi_filltxfifo:      Fills the TX FIFO as long as there is room in
 502  *                              the FIFO or the bytes required to be
 503  *                              transmitted.
 504  * @xqspi:      Pointer to the zynqmp_qspi structure
 505  * @size:       Number of bytes to be copied from TX buffer to TX FIFO
 506  */
 507 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
 508 {
 509         u32 count = 0, intermediate;
 510
 511         while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
 512                 memcpy(&intermediate, xqspi->txbuf, 4);
 513                 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
 514
 515                 if (xqspi->bytes_to_transfer >= 4) {
 516                         xqspi->txbuf += 4;
 517                         xqspi->bytes_to_transfer -= 4;
 518                 } else {
 519                         xqspi->txbuf += xqspi->bytes_to_transfer;
 520                         xqspi->bytes_to_transfer = 0;
 521                 }
 522                 count++;
 523         }
 524 }
 525
 526 /**
 527  * zynqmp_qspi_readrxfifo:      Fills the RX FIFO as long as there is room in
 528  *                              the FIFO.
 529  * @xqspi:      Pointer to the zynqmp_qspi structure
 530  * @size:       Number of bytes to be copied from RX buffer to RX FIFO
 531  */
 532 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
 533 {
 534         ulong data;
 535         int count = 0;
 536
 537         while ((count < size) && (xqspi->bytes_to_receive > 0)) {
 538                 if (xqspi->bytes_to_receive >= 4) {
 539                         (*(u32 *) xqspi->rxbuf) =
 540                         zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 541                         xqspi->rxbuf += 4;
 542                         xqspi->bytes_to_receive -= 4;
 543                         count += 4;
 544                 } else {
 545                         data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 546                         count += xqspi->bytes_to_receive;
 547                         zynqmp_qspi_copy_read_data(xqspi, data,
 548                                                    xqspi->bytes_to_receive);
 549                         xqspi->bytes_to_receive = 0;
 550                 }
 551         }
 552 }
 553
 554 /**
 555  * zynqmp_process_dma_irq:      Handler for DMA done interrupt of QSPI
 556  *                              controller
 557  * @xqspi:      zynqmp_qspi instance pointer
 558  *
 559  * This function handles DMA interrupt only.
 560  */
 561 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
 562 {
 563         u32 config_reg, genfifoentry;
 564
 565         dma_unmap_single(xqspi->dev, xqspi->dma_addr,
 566                                 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
 567         xqspi->rxbuf += xqspi->dma_rx_bytes;
 568         xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
 569         xqspi->dma_rx_bytes = 0;
 570
 571         /* Disabling the DMA interrupts */
 572         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
 573                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 574
 575         if (xqspi->bytes_to_receive > 0) {
 576                 /* Switch to IO mode,for remaining bytes to receive */
 577                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 578                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 579                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 580
 581                 /* Initiate the transfer of remaining bytes */
 582                 genfifoentry = xqspi->genfifoentry;
 583                 genfifoentry |= xqspi->bytes_to_receive;
 584                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 585
 586                 /* Dummy generic FIFO entry */
 587                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 588
 589                 /* Manual start */
 590                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 591                         (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 592                         GQSPI_CFG_START_GEN_FIFO_MASK));
 593
 594                 /* Enable the RX interrupts for IO mode */
 595                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 596                                 GQSPI_IER_GENFIFOEMPTY_MASK |
 597                                 GQSPI_IER_RXNEMPTY_MASK |
 598                                 GQSPI_IER_RXEMPTY_MASK);
 599         }
 600 }
 601
 602 /**
 603  * zynqmp_qspi_irq:     Interrupt service routine of the QSPI controller
 604  * @irq:        IRQ number
 605  * @dev_id:     Pointer to the xqspi structure
 606  *
 607  * This function handles TX empty only.
 608  * On TX empty interrupt this function reads the received data from RX FIFO
 609  * and fills the TX FIFO if there is any data remaining to be transferred.
 610  *
 611  * Return:      IRQ_HANDLED when interrupt is handled
 612  *              IRQ_NONE otherwise.
 613  */
 614 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
 615 {
 616         struct spi_master *master = dev_id;
 617         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 618         int ret = IRQ_NONE;
 619         u32 status, mask, dma_status = 0;
 620
 621         status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 622         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
 623         mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
 624
 625         /* Read and clear DMA status */
 626         if (xqspi->mode == GQSPI_MODE_DMA) {
 627                 dma_status =
 628                         zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
 629                 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 630                                                                 dma_status);
 631         }
 632
 633         if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
 634                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
 635                 ret = IRQ_HANDLED;
 636         }
 637
 638         if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
 639                 zynqmp_process_dma_irq(xqspi);
 640                 ret = IRQ_HANDLED;
 641         } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
 642                         (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
 643                 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
 644                 ret = IRQ_HANDLED;
 645         }
 646
 647         if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
 648                         && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
 649                 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
 650                 spi_finalize_current_transfer(master);
 651                 ret = IRQ_HANDLED;
 652         }
 653         return ret;
 654 }
 655
 656 /**
 657  * zynqmp_qspi_selectspimode:   Selects SPI mode - x1 or x2 or x4.
 658  * @xqspi:      xqspi is a pointer to the GQSPI instance
 659  * @spimode:    spimode - SPI or DUAL or QUAD.
 660  * Return:      Mask to set desired SPI mode in GENFIFO entry.
 661  */
 662 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
 663                                                 u8 spimode)
 664 {
 665         u32 mask = 0;
 666
 667         switch (spimode) {
 668         case GQSPI_SELECT_MODE_DUALSPI:
 669                 mask = GQSPI_GENFIFO_MODE_DUALSPI;
 670                 break;
 671         case GQSPI_SELECT_MODE_QUADSPI:
 672                 mask = GQSPI_GENFIFO_MODE_QUADSPI;
 673                 break;
 674         case GQSPI_SELECT_MODE_SPI:
 675                 mask = GQSPI_GENFIFO_MODE_SPI;
 676                 break;
 677         default:
 678                 dev_warn(xqspi->dev, "Invalid SPI mode\n");
 679         }
 680
 681         return mask;
 682 }
 683
 684 /**
 685  * zynq_qspi_setuprxdma:        This function sets up the RX DMA operation
 686  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 687  */
 688 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
 689 {
 690         u32 rx_bytes, rx_rem, config_reg;
 691         dma_addr_t addr;
 692         u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
 693
 694         if ((xqspi->bytes_to_receive < 8) ||
 695                 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
 696                 /* Setting to IO mode */
 697                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 698                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 699                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 700                 xqspi->mode = GQSPI_MODE_IO;
 701                 xqspi->dma_rx_bytes = 0;
 702                 return;
 703         }
 704
 705         rx_rem = xqspi->bytes_to_receive % 4;
 706         rx_bytes = (xqspi->bytes_to_receive - rx_rem);
 707
 708         addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
 709                                                 rx_bytes, DMA_FROM_DEVICE);
 710         if (dma_mapping_error(xqspi->dev, addr))
 711                 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
 712
 713         xqspi->dma_rx_bytes = rx_bytes;
 714         xqspi->dma_addr = addr;
 715         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
 716                                 (u32)(addr & 0xffffffff));
 717         addr = ((addr >> 16) >> 16);
 718         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
 719                                 ((u32)addr) & 0xfff);
 720
 721         /* Enabling the DMA mode */
 722         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 723         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 724         config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
 725         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 726
 727         /* Switch to DMA mode */
 728         xqspi->mode = GQSPI_MODE_DMA;
 729
 730         /* Write the number of bytes to transfer */
 731         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
 732 }
 733
 734 /**
 735  * zynqmp_qspi_txrxsetup:       This function checks the TX/RX buffers in
 736  *                              the transfer and sets up the GENFIFO entries,
 737  *                              TX FIFO as required.
 738  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 739  * @transfer:   It is a pointer to the structure containing transfer data.
 740  * @genfifoentry:       genfifoentry is pointer to the variable in which
 741  *                      GENFIFO mask is returned to calling function
 742  */
 743 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
 744                                   struct spi_transfer *transfer,
 745                                   u32 *genfifoentry)
 746 {
 747         u32 config_reg;
 748
 749         /* Transmit */
 750         if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
 751                 /* Setup data to be TXed */
 752                 *genfifoentry &= ~GQSPI_GENFIFO_RX;
 753                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 754                 *genfifoentry |= GQSPI_GENFIFO_TX;
 755                 *genfifoentry |=
 756                         zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
 757                 xqspi->bytes_to_transfer = transfer->len;
 758                 if (xqspi->mode == GQSPI_MODE_DMA) {
 759                         config_reg = zynqmp_gqspi_read(xqspi,
 760                                                         GQSPI_CONFIG_OFST);
 761                         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 762                         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 763                                                                 config_reg);
 764                         xqspi->mode = GQSPI_MODE_IO;
 765                 }
 766                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
 767                 /* Discard RX data */
 768                 xqspi->bytes_to_receive = 0;
 769         } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
 770                 /* Receive */
 771
 772                 /* TX auto fill */
 773                 *genfifoentry &= ~GQSPI_GENFIFO_TX;
 774                 /* Setup RX */
 775                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 776                 *genfifoentry |= GQSPI_GENFIFO_RX;
 777                 *genfifoentry |=
 778                         zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
 779                 xqspi->bytes_to_transfer = 0;
 780                 xqspi->bytes_to_receive = transfer->len;
 781                 zynq_qspi_setuprxdma(xqspi);
 782         }
 783 }
 784
 785 /**
 786  * zynqmp_qspi_start_transfer:  Initiates the QSPI transfer
 787  * @master:     Pointer to the spi_master structure which provides
 788  *              information about the controller.
 789  * @qspi:       Pointer to the spi_device structure
 790  * @transfer:   Pointer to the spi_transfer structure which provide information
 791  *              about next transfer parameters
 792  *
 793  * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 794  * transfer to be completed.
 795  *
 796  * Return:      Number of bytes transferred in the last transfer
 797  */
 798 static int zynqmp_qspi_start_transfer(struct spi_master *master,
 799                                       struct spi_device *qspi,
 800                                       struct spi_transfer *transfer)
 801 {
 802         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 803         u32 genfifoentry = 0x0, transfer_len;
 804
 805         xqspi->txbuf = transfer->tx_buf;
 806         xqspi->rxbuf = transfer->rx_buf;
 807
 808         zynqmp_qspi_setup_transfer(qspi, transfer);
 809
 810         genfifoentry |= xqspi->genfifocs;
 811         genfifoentry |= xqspi->genfifobus;
 812
 813         zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
 814
 815         if (xqspi->mode == GQSPI_MODE_DMA)
 816                 transfer_len = xqspi->dma_rx_bytes;
 817         else
 818                 transfer_len = transfer->len;
 819
 820         xqspi->genfifoentry = genfifoentry;
 821         if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
 822                 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 823                 genfifoentry |= transfer_len;
 824                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 825         } else {
 826                 int tempcount = transfer_len;
 827                 u32 exponent = 8;       /* 2^8 = 256 */
 828                 u8 imm_data = tempcount & 0xFF;
 829
 830                 tempcount &= ~(tempcount & 0xFF);
 831                 /* Immediate entry */
 832                 if (tempcount != 0) {
 833                         /* Exponent entries */
 834                         genfifoentry |= GQSPI_GENFIFO_EXP;
 835                         while (tempcount != 0) {
 836                                 if (tempcount & GQSPI_GENFIFO_EXP_START) {
 837                                         genfifoentry &=
 838                                             ~GQSPI_GENFIFO_IMM_DATA_MASK;
 839                                         genfifoentry |= exponent;
 840                                         zynqmp_gqspi_write(xqspi,
 841                                                            GQSPI_GEN_FIFO_OFST,
 842                                                            genfifoentry);
 843                                 }
 844                                 tempcount = tempcount >> 1;
 845                                 exponent++;
 846                         }
 847                 }
 848                 if (imm_data != 0) {
 849                         genfifoentry &= ~GQSPI_GENFIFO_EXP;
 850                         genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 851                         genfifoentry |= (u8) (imm_data & 0xFF);
 852                         zynqmp_gqspi_write(xqspi,
 853                                            GQSPI_GEN_FIFO_OFST, genfifoentry);
 854                 }
 855         }
 856
 857         if ((xqspi->mode == GQSPI_MODE_IO) &&
 858                         (xqspi->rxbuf != NULL)) {
 859                 /* Dummy generic FIFO entry */
 860                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 861         }
 862
 863         /* Since we are using manual mode */
 864         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 865                            zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 866                            GQSPI_CFG_START_GEN_FIFO_MASK);
 867
 868         if (xqspi->txbuf != NULL)
 869                 /* Enable interrupts for TX */
 870                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 871                                    GQSPI_IER_TXEMPTY_MASK |
 872                                         GQSPI_IER_GENFIFOEMPTY_MASK |
 873                                         GQSPI_IER_TXNOT_FULL_MASK);
 874
 875         if (xqspi->rxbuf != NULL) {
 876                 /* Enable interrupts for RX */
 877                 if (xqspi->mode == GQSPI_MODE_DMA) {
 878                         /* Enable DMA interrupts */
 879                         zynqmp_gqspi_write(xqspi,
 880                                         GQSPI_QSPIDMA_DST_I_EN_OFST,
 881                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 882                 } else {
 883                         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 884                                         GQSPI_IER_GENFIFOEMPTY_MASK |
 885                                         GQSPI_IER_RXNEMPTY_MASK |
 886                                         GQSPI_IER_RXEMPTY_MASK);
 887                 }
 888         }
 889
 890         return transfer->len;
 891 }
 892
 893 /**
 894  * zynqmp_qspi_suspend: Suspend method for the QSPI driver
 895  * @dev:        Address of the platform_device structure
 896  *
 897  * This function stops the QSPI driver queue and disables the QSPI controller
 898  *
 899  * Return:      Always 0
 900  */
 901 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
 902 {
 903         struct spi_master *master = dev_get_drvdata(dev);
 904
 905         spi_master_suspend(master);
 906
 907         zynqmp_unprepare_transfer_hardware(master);
 908
 909         return 0;
 910 }
 911
 912 /**
 913  * zynqmp_qspi_resume:  Resume method for the QSPI driver
 914  * @dev:        Address of the platform_device structure
 915  *
 916  * The function starts the QSPI driver queue and initializes the QSPI
 917  * controller
 918  *
 919  * Return:      0 on success; error value otherwise
 920  */
 921 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
 922 {
 923         struct spi_master *master = dev_get_drvdata(dev);
 924         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 925         int ret = 0;
 926
 927         ret = clk_enable(xqspi->pclk);
 928         if (ret) {
 929                 dev_err(dev, "Cannot enable APB clock.\n");
 930                 return ret;
 931         }
 932
 933         ret = clk_enable(xqspi->refclk);
 934         if (ret) {
 935                 dev_err(dev, "Cannot enable device clock.\n");
 936                 clk_disable(xqspi->pclk);
 937                 return ret;
 938         }
 939
 940         spi_master_resume(master);
 941
 942         clk_disable(xqspi->refclk);
 943         clk_disable(xqspi->pclk);
 944         return 0;
 945 }
 946
 947 /**
 948  * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
 949  * @dev:        Address of the platform_device structure
 950  *
 951  * This function disables the clocks
 952  *
 953  * Return:      Always 0
 954  */
 955 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
 956 {
 957         struct spi_master *master = dev_get_drvdata(dev);
 958         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 959
 960         clk_disable(xqspi->refclk);
 961         clk_disable(xqspi->pclk);
 962
 963         return 0;
 964 }
 965
 966 /**
 967  * zynqmp_runtime_resume - Runtime resume method for the SPI driver
 968  * @dev:        Address of the platform_device structure
 969  *
 970  * This function enables the clocks
 971  *
 972  * Return:      0 on success and error value on error
 973  */
 974 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
 975 {
 976         struct spi_master *master = dev_get_drvdata(dev);
 977         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 978         int ret;
 979
 980         ret = clk_enable(xqspi->pclk);
 981         if (ret) {
 982                 dev_err(dev, "Cannot enable APB clock.\n");
 983                 return ret;
 984         }
 985
 986         ret = clk_enable(xqspi->refclk);
 987         if (ret) {
 988                 dev_err(dev, "Cannot enable device clock.\n");
 989                 clk_disable(xqspi->pclk);
 990                 return ret;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
 997         SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
 998                            zynqmp_runtime_resume, NULL)
 999         SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1000 };
1001
1002 /**
1003  * zynqmp_qspi_probe:   Probe method for the QSPI driver
1004  * @pdev:       Pointer to the platform_device structure
1005  *
1006  * This function initializes the driver data structures and the hardware.
1007  *
1008  * Return:      0 on success; error value otherwise
1009  */
1010 static int zynqmp_qspi_probe(struct platform_device *pdev)
1011 {
1012         int ret = 0;
1013         struct spi_master *master;
1014         struct zynqmp_qspi *xqspi;
1015         struct device *dev = &pdev->dev;
1016
1017         master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1018         if (!master)
1019                 return -ENOMEM;
1020
1021         xqspi = spi_master_get_devdata(master);
1022         master->dev.of_node = pdev->dev.of_node;
1023         platform_set_drvdata(pdev, master);
1024
1025         xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1026         if (IS_ERR(xqspi->regs)) {
1027                 ret = PTR_ERR(xqspi->regs);
1028                 goto remove_master;
1029         }
1030
1031         xqspi->dev = dev;
1032         xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1033         if (IS_ERR(xqspi->pclk)) {
1034                 dev_err(dev, "pclk clock not found.\n");
1035                 ret = PTR_ERR(xqspi->pclk);
1036                 goto remove_master;
1037         }
1038
1039         ret = clk_prepare_enable(xqspi->pclk);
1040         if (ret) {
1041                 dev_err(dev, "Unable to enable APB clock.\n");
1042                 goto remove_master;
1043         }
1044
1045         xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1046         if (IS_ERR(xqspi->refclk)) {
1047                 dev_err(dev, "ref_clk clock not found.\n");
1048                 ret = PTR_ERR(xqspi->refclk);
1049                 goto clk_dis_pclk;
1050         }
1051
1052         ret = clk_prepare_enable(xqspi->refclk);
1053         if (ret) {
1054                 dev_err(dev, "Unable to enable device clock.\n");
1055                 goto clk_dis_pclk;
1056         }
1057
1058         pm_runtime_use_autosuspend(&pdev->dev);
1059         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1060         pm_runtime_set_active(&pdev->dev);
1061         pm_runtime_enable(&pdev->dev);
1062         /* QSPI controller initializations */
1063         zynqmp_qspi_init_hw(xqspi);
1064
1065         pm_runtime_mark_last_busy(&pdev->dev);
1066         pm_runtime_put_autosuspend(&pdev->dev);
1067         xqspi->irq = platform_get_irq(pdev, 0);
1068         if (xqspi->irq <= 0) {
1069                 ret = -ENXIO;
1070                 goto clk_dis_all;
1071         }
1072         ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1073                                0, pdev->name, master);
1074         if (ret != 0) {
1075                 ret = -ENXIO;
1076                 dev_err(dev, "request_irq failed\n");
1077                 goto clk_dis_all;
1078         }
1079
1080         master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1081
1082         master->setup = zynqmp_qspi_setup;
1083         master->set_cs = zynqmp_qspi_chipselect;
1084         master->transfer_one = zynqmp_qspi_start_transfer;
1085         master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1086         master->unprepare_transfer_hardware =
1087                                         zynqmp_unprepare_transfer_hardware;
1088         master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1089         master->bits_per_word_mask = SPI_BPW_MASK(8);
1090         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1091                             SPI_TX_DUAL | SPI_TX_QUAD;
1092
1093         if (master->dev.parent == NULL)
1094                 master->dev.parent = &master->dev;
1095
1096         ret = spi_register_master(master);
1097         if (ret)
1098                 goto clk_dis_all;
1099
1100         return 0;
1101
1102 clk_dis_all:
1103         pm_runtime_set_suspended(&pdev->dev);
1104         pm_runtime_disable(&pdev->dev);
1105         clk_disable_unprepare(xqspi->refclk);
1106 clk_dis_pclk:
1107         clk_disable_unprepare(xqspi->pclk);
1108 remove_master:
1109         spi_master_put(master);
1110
1111         return ret;
1112 }
1113
1114 /**
1115  * zynqmp_qspi_remove:  Remove method for the QSPI driver
1116  * @pdev:       Pointer to the platform_device structure
1117  *
1118  * This function is called if a device is physically removed from the system or
1119  * if the driver module is being unloaded. It frees all resources allocated to
1120  * the device.
1121  *
1122  * Return:      0 Always
1123  */
1124 static int zynqmp_qspi_remove(struct platform_device *pdev)
1125 {
1126         struct spi_master *master = platform_get_drvdata(pdev);
1127         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1128
1129         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1130         clk_disable_unprepare(xqspi->refclk);
1131         clk_disable_unprepare(xqspi->pclk);
1132         pm_runtime_set_suspended(&pdev->dev);
1133         pm_runtime_disable(&pdev->dev);
1134
1135         spi_unregister_master(master);
1136
1137         return 0;
1138 }
1139
1140 static const struct of_device_id zynqmp_qspi_of_match[] = {
1141         { .compatible = "xlnx,zynqmp-qspi-1.0", },
1142         { /* End of table */ }
1143 };
1144
1145 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1146
1147 static struct platform_driver zynqmp_qspi_driver = {
1148         .probe = zynqmp_qspi_probe,
1149         .remove = zynqmp_qspi_remove,
1150         .driver = {
1151                 .name = "zynqmp-qspi",
1152                 .of_match_table = zynqmp_qspi_of_match,
1153                 .pm = &zynqmp_qspi_dev_pm_ops,
1154         },
1155 };
1156
1157 module_platform_driver(zynqmp_qspi_driver);
1158
1159 MODULE_AUTHOR("Xilinx, Inc.");
1160 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1161 MODULE_LICENSE("GPL");