drivers/spi/spi-zynqmp-gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
   4  * (master mode only)
   5  *
   6  * Copyright (C) 2009 - 2015 Xilinx, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/firmware/xlnx-zynqmp.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_address.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/spi/spi-mem.h>
  25
  26 /* Generic QSPI register offsets */
  27 #define GQSPI_CONFIG_OFST               0x00000100
  28 #define GQSPI_ISR_OFST                  0x00000104
  29 #define GQSPI_IDR_OFST                  0x0000010C
  30 #define GQSPI_IER_OFST                  0x00000108
  31 #define GQSPI_IMASK_OFST                0x00000110
  32 #define GQSPI_EN_OFST                   0x00000114
  33 #define GQSPI_TXD_OFST                  0x0000011C
  34 #define GQSPI_RXD_OFST                  0x00000120
  35 #define GQSPI_TX_THRESHOLD_OFST         0x00000128
  36 #define GQSPI_RX_THRESHOLD_OFST         0x0000012C
  37 #define GQSPI_LPBK_DLY_ADJ_OFST         0x00000138
  38 #define GQSPI_GEN_FIFO_OFST             0x00000140
  39 #define GQSPI_SEL_OFST                  0x00000144
  40 #define GQSPI_GF_THRESHOLD_OFST         0x00000150
  41 #define GQSPI_FIFO_CTRL_OFST            0x0000014C
  42 #define GQSPI_QSPIDMA_DST_CTRL_OFST     0x0000080C
  43 #define GQSPI_QSPIDMA_DST_SIZE_OFST     0x00000804
  44 #define GQSPI_QSPIDMA_DST_STS_OFST      0x00000808
  45 #define GQSPI_QSPIDMA_DST_I_STS_OFST    0x00000814
  46 #define GQSPI_QSPIDMA_DST_I_EN_OFST     0x00000818
  47 #define GQSPI_QSPIDMA_DST_I_DIS_OFST    0x0000081C
  48 #define GQSPI_QSPIDMA_DST_I_MASK_OFST   0x00000820
  49 #define GQSPI_QSPIDMA_DST_ADDR_OFST     0x00000800
  50 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
  51
  52 /* GQSPI register bit masks */
  53 #define GQSPI_SEL_MASK                          0x00000001
  54 #define GQSPI_EN_MASK                           0x00000001
  55 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK        0x00000020
  56 #define GQSPI_ISR_WR_TO_CLR_MASK                0x00000002
  57 #define GQSPI_IDR_ALL_MASK                      0x00000FBE
  58 #define GQSPI_CFG_MODE_EN_MASK                  0xC0000000
  59 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK      0x20000000
  60 #define GQSPI_CFG_ENDIAN_MASK                   0x04000000
  61 #define GQSPI_CFG_EN_POLL_TO_MASK               0x00100000
  62 #define GQSPI_CFG_WP_HOLD_MASK                  0x00080000
  63 #define GQSPI_CFG_BAUD_RATE_DIV_MASK            0x00000038
  64 #define GQSPI_CFG_CLK_PHA_MASK                  0x00000004
  65 #define GQSPI_CFG_CLK_POL_MASK                  0x00000002
  66 #define GQSPI_CFG_START_GEN_FIFO_MASK           0x10000000
  67 #define GQSPI_GENFIFO_IMM_DATA_MASK             0x000000FF
  68 #define GQSPI_GENFIFO_DATA_XFER                 0x00000100
  69 #define GQSPI_GENFIFO_EXP                       0x00000200
  70 #define GQSPI_GENFIFO_MODE_SPI                  0x00000400
  71 #define GQSPI_GENFIFO_MODE_DUALSPI              0x00000800
  72 #define GQSPI_GENFIFO_MODE_QUADSPI              0x00000C00
  73 #define GQSPI_GENFIFO_MODE_MASK                 0x00000C00
  74 #define GQSPI_GENFIFO_CS_LOWER                  0x00001000
  75 #define GQSPI_GENFIFO_CS_UPPER                  0x00002000
  76 #define GQSPI_GENFIFO_BUS_LOWER                 0x00004000
  77 #define GQSPI_GENFIFO_BUS_UPPER                 0x00008000
  78 #define GQSPI_GENFIFO_BUS_BOTH                  0x0000C000
  79 #define GQSPI_GENFIFO_BUS_MASK                  0x0000C000
  80 #define GQSPI_GENFIFO_TX                        0x00010000
  81 #define GQSPI_GENFIFO_RX                        0x00020000
  82 #define GQSPI_GENFIFO_STRIPE                    0x00040000
  83 #define GQSPI_GENFIFO_POLL                      0x00080000
  84 #define GQSPI_GENFIFO_EXP_START                 0x00000100
  85 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK        0x00000004
  86 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK        0x00000002
  87 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK       0x00000001
  88 #define GQSPI_ISR_RXEMPTY_MASK                  0x00000800
  89 #define GQSPI_ISR_GENFIFOFULL_MASK              0x00000400
  90 #define GQSPI_ISR_GENFIFONOT_FULL_MASK          0x00000200
  91 #define GQSPI_ISR_TXEMPTY_MASK                  0x00000100
  92 #define GQSPI_ISR_GENFIFOEMPTY_MASK             0x00000080
  93 #define GQSPI_ISR_RXFULL_MASK                   0x00000020
  94 #define GQSPI_ISR_RXNEMPTY_MASK                 0x00000010
  95 #define GQSPI_ISR_TXFULL_MASK                   0x00000008
  96 #define GQSPI_ISR_TXNOT_FULL_MASK               0x00000004
  97 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK         0x00000002
  98 #define GQSPI_IER_TXNOT_FULL_MASK               0x00000004
  99 #define GQSPI_IER_RXEMPTY_MASK                  0x00000800
 100 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK         0x00000002
 101 #define GQSPI_IER_RXNEMPTY_MASK                 0x00000010
 102 #define GQSPI_IER_GENFIFOEMPTY_MASK             0x00000080
 103 #define GQSPI_IER_TXEMPTY_MASK                  0x00000100
 104 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK         0x000000FE
 105 #define GQSPI_QSPIDMA_DST_STS_WTC               0x0000E000
 106 #define GQSPI_CFG_MODE_EN_DMA_MASK              0x80000000
 107 #define GQSPI_ISR_IDR_MASK                      0x00000994
 108 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK        0x00000002
 109 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK       0x00000002
 110 #define GQSPI_IRQ_MASK                          0x00000980
 111
 112 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT           3
 113 #define GQSPI_GENFIFO_CS_SETUP                  0x4
 114 #define GQSPI_GENFIFO_CS_HOLD                   0x3
 115 #define GQSPI_TXD_DEPTH                         64
 116 #define GQSPI_RX_FIFO_THRESHOLD                 32
 117 #define GQSPI_RX_FIFO_FILL      (GQSPI_RX_FIFO_THRESHOLD * 4)
 118 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL       32
 119 #define GQSPI_TX_FIFO_FILL      (GQSPI_TXD_DEPTH -\
 120                                 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
 121 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL      0X10
 122 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL        0x803FFA00
 123 #define GQSPI_SELECT_FLASH_CS_LOWER             0x1
 124 #define GQSPI_SELECT_FLASH_CS_UPPER             0x2
 125 #define GQSPI_SELECT_FLASH_CS_BOTH              0x3
 126 #define GQSPI_SELECT_FLASH_BUS_LOWER            0x1
 127 #define GQSPI_SELECT_FLASH_BUS_UPPER            0x2
 128 #define GQSPI_SELECT_FLASH_BUS_BOTH             0x3
 129 #define GQSPI_BAUD_DIV_MAX      7       /* Baud rate divisor maximum */
 130 #define GQSPI_BAUD_DIV_SHIFT    2       /* Baud rate divisor shift */
 131 #define GQSPI_SELECT_MODE_SPI           0x1
 132 #define GQSPI_SELECT_MODE_DUALSPI       0x2
 133 #define GQSPI_SELECT_MODE_QUADSPI       0x4
 134 #define GQSPI_DMA_UNALIGN               0x3
 135 #define GQSPI_DEFAULT_NUM_CS    1       /* Default number of chip selects */
 136
 137 #define SPI_AUTOSUSPEND_TIMEOUT         3000
 138 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
 139
 140 /**
 141  * struct zynqmp_qspi - Defines qspi driver instance
 142  * @regs:               Virtual address of the QSPI controller registers
 143  * @refclk:             Pointer to the peripheral clock
 144  * @pclk:               Pointer to the APB clock
 145  * @irq:                IRQ number
 146  * @dev:                Pointer to struct device
 147  * @txbuf:              Pointer to the TX buffer
 148  * @rxbuf:              Pointer to the RX buffer
 149  * @bytes_to_transfer:  Number of bytes left to transfer
 150  * @bytes_to_receive:   Number of bytes left to receive
 151  * @genfifocs:          Used for chip select
 152  * @genfifobus:         Used to select the upper or lower bus
 153  * @dma_rx_bytes:       Remaining bytes to receive by DMA mode
 154  * @dma_addr:           DMA address after mapping the kernel buffer
 155  * @genfifoentry:       Used for storing the genfifoentry instruction.
 156  * @mode:               Defines the mode in which QSPI is operating
 157  * @data_completion:    completion structure
 158  */
 159 struct zynqmp_qspi {
 160         void __iomem *regs;
 161         struct clk *refclk;
 162         struct clk *pclk;
 163         int irq;
 164         struct device *dev;
 165         const void *txbuf;
 166         void *rxbuf;
 167         int bytes_to_transfer;
 168         int bytes_to_receive;
 169         u32 genfifocs;
 170         u32 genfifobus;
 171         u32 dma_rx_bytes;
 172         dma_addr_t dma_addr;
 173         u32 genfifoentry;
 174         enum mode_type mode;
 175         struct completion data_completion;
 176 };
 177
 178 /**
 179  * zynqmp_gqspi_read - For GQSPI controller read operation
 180  * @xqspi:      Pointer to the zynqmp_qspi structure
 181  * @offset:     Offset from where to read
 182  * Return:      Value at the offset
 183  */
 184 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
 185 {
 186         return readl_relaxed(xqspi->regs + offset);
 187 }
 188
 189 /**
 190  * zynqmp_gqspi_write - For GQSPI controller write operation
 191  * @xqspi:      Pointer to the zynqmp_qspi structure
 192  * @offset:     Offset where to write
 193  * @val:        Value to be written
 194  */
 195 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
 196                                       u32 val)
 197 {
 198         writel_relaxed(val, (xqspi->regs + offset));
 199 }
 200
 201 /**
 202  * zynqmp_gqspi_selectslave - For selection of slave device
 203  * @instanceptr:        Pointer to the zynqmp_qspi structure
 204  * @slavecs:    For chip select
 205  * @slavebus:   To check which bus is selected- upper or lower
 206  */
 207 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
 208                                      u8 slavecs, u8 slavebus)
 209 {
 210         /*
 211          * Bus and CS lines selected here will be updated in the instance and
 212          * used for subsequent GENFIFO entries during transfer.
 213          */
 214
 215         /* Choose slave select line */
 216         switch (slavecs) {
 217         case GQSPI_SELECT_FLASH_CS_BOTH:
 218                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
 219                         GQSPI_GENFIFO_CS_UPPER;
 220                 break;
 221         case GQSPI_SELECT_FLASH_CS_UPPER:
 222                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
 223                 break;
 224         case GQSPI_SELECT_FLASH_CS_LOWER:
 225                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 226                 break;
 227         default:
 228                 dev_warn(instanceptr->dev, "Invalid slave select\n");
 229         }
 230
 231         /* Choose the bus */
 232         switch (slavebus) {
 233         case GQSPI_SELECT_FLASH_BUS_BOTH:
 234                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
 235                         GQSPI_GENFIFO_BUS_UPPER;
 236                 break;
 237         case GQSPI_SELECT_FLASH_BUS_UPPER:
 238                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
 239                 break;
 240         case GQSPI_SELECT_FLASH_BUS_LOWER:
 241                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 242                 break;
 243         default:
 244                 dev_warn(instanceptr->dev, "Invalid slave bus\n");
 245         }
 246 }
 247
 248 /**
 249  * zynqmp_qspi_init_hw - Initialize the hardware
 250  * @xqspi:      Pointer to the zynqmp_qspi structure
 251  *
 252  * The default settings of the QSPI controller's configurable parameters on
 253  * reset are
 254  *      - Master mode
 255  *      - TX threshold set to 1
 256  *      - RX threshold set to 1
 257  *      - Flash memory interface mode enabled
 258  * This function performs the following actions
 259  *      - Disable and clear all the interrupts
 260  *      - Enable manual slave select
 261  *      - Enable manual start
 262  *      - Deselect all the chip select lines
 263  *      - Set the little endian mode of TX FIFO and
 264  *      - Enable the QSPI controller
 265  */
 266 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 267 {
 268         u32 config_reg;
 269
 270         /* Select the GQSPI mode */
 271         zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
 272         /* Clear and disable interrupts */
 273         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
 274                            zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
 275                            GQSPI_ISR_WR_TO_CLR_MASK);
 276         /* Clear the DMA STS */
 277         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 278                            zynqmp_gqspi_read(xqspi,
 279                                              GQSPI_QSPIDMA_DST_I_STS_OFST));
 280         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
 281                            zynqmp_gqspi_read(xqspi,
 282                                              GQSPI_QSPIDMA_DST_STS_OFST) |
 283                                              GQSPI_QSPIDMA_DST_STS_WTC);
 284         zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
 285         zynqmp_gqspi_write(xqspi,
 286                            GQSPI_QSPIDMA_DST_I_DIS_OFST,
 287                            GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
 288         /* Disable the GQSPI */
 289         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 290         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 291         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 292         /* Manual start */
 293         config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
 294         /* Little endian by default */
 295         config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
 296         /* Disable poll time out */
 297         config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
 298         /* Set hold bit */
 299         config_reg |= GQSPI_CFG_WP_HOLD_MASK;
 300         /* Clear pre-scalar by default */
 301         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 302         /* CPHA 0 */
 303         config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
 304         /* CPOL 0 */
 305         config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
 306         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 307
 308         /* Clear the TX and RX FIFO */
 309         zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
 310                            GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
 311                            GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
 312                            GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
 313         /* Set by default to allow for high frequencies */
 314         zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
 315                            zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
 316                            GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 317         /* Reset thresholds */
 318         zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
 319                            GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
 320         zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
 321                            GQSPI_RX_FIFO_THRESHOLD);
 322         zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
 323                            GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
 324         zynqmp_gqspi_selectslave(xqspi,
 325                                  GQSPI_SELECT_FLASH_CS_LOWER,
 326                                  GQSPI_SELECT_FLASH_BUS_LOWER);
 327         /* Initialize DMA */
 328         zynqmp_gqspi_write(xqspi,
 329                            GQSPI_QSPIDMA_DST_CTRL_OFST,
 330                            GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
 331
 332         /* Enable the GQSPI */
 333         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 334 }
 335
 336 /**
 337  * zynqmp_qspi_copy_read_data - Copy data to RX buffer
 338  * @xqspi:      Pointer to the zynqmp_qspi structure
 339  * @data:       The variable where data is stored
 340  * @size:       Number of bytes to be copied from data to RX buffer
 341  */
 342 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
 343                                        ulong data, u8 size)
 344 {
 345         memcpy(xqspi->rxbuf, &data, size);
 346         xqspi->rxbuf += size;
 347         xqspi->bytes_to_receive -= size;
 348 }
 349
 350 /**
 351  * zynqmp_qspi_chipselect - Select or deselect the chip select line
 352  * @qspi:       Pointer to the spi_device structure
 353  * @is_high:    Select(0) or deselect (1) the chip select line
 354  */
 355 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
 356 {
 357         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 358         ulong timeout;
 359         u32 genfifoentry = 0, statusreg;
 360
 361         genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 362
 363         if (!is_high) {
 364                 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 365                 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 366                 genfifoentry |= xqspi->genfifobus;
 367                 genfifoentry |= xqspi->genfifocs;
 368                 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
 369         } else {
 370                 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
 371         }
 372
 373         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 374
 375         /* Manually start the generic FIFO command */
 376         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 377                            zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 378                            GQSPI_CFG_START_GEN_FIFO_MASK);
 379
 380         timeout = jiffies + msecs_to_jiffies(1000);
 381
 382         /* Wait until the generic FIFO command is empty */
 383         do {
 384                 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 385
 386                 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
 387                     (statusreg & GQSPI_ISR_TXEMPTY_MASK))
 388                         break;
 389                 cpu_relax();
 390         } while (!time_after_eq(jiffies, timeout));
 391
 392         if (time_after_eq(jiffies, timeout))
 393                 dev_err(xqspi->dev, "Chip select timed out\n");
 394 }
 395
 396 /**
 397  * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
 398  * @xqspi:      xqspi is a pointer to the GQSPI instance
 399  * @spimode:    spimode - SPI or DUAL or QUAD.
 400  * Return:      Mask to set desired SPI mode in GENFIFO entry.
 401  */
 402 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
 403                                             u8 spimode)
 404 {
 405         u32 mask = 0;
 406
 407         switch (spimode) {
 408         case GQSPI_SELECT_MODE_DUALSPI:
 409                 mask = GQSPI_GENFIFO_MODE_DUALSPI;
 410                 break;
 411         case GQSPI_SELECT_MODE_QUADSPI:
 412                 mask = GQSPI_GENFIFO_MODE_QUADSPI;
 413                 break;
 414         case GQSPI_SELECT_MODE_SPI:
 415                 mask = GQSPI_GENFIFO_MODE_SPI;
 416                 break;
 417         default:
 418                 dev_warn(xqspi->dev, "Invalid SPI mode\n");
 419         }
 420
 421         return mask;
 422 }
 423
 424 /**
 425  * zynqmp_qspi_config_op - Configure QSPI controller for specified
 426  *                              transfer
 427  * @xqspi:      Pointer to the zynqmp_qspi structure
 428  * @qspi:       Pointer to the spi_device structure
 429  *
 430  * Sets the operational mode of QSPI controller for the next QSPI transfer and
 431  * sets the requested clock frequency.
 432  *
 433  * Return:      Always 0
 434  *
 435  * Note:
 436  *      If the requested frequency is not an exact match with what can be
 437  *      obtained using the pre-scalar value, the driver sets the clock
 438  *      frequency which is lower than the requested frequency (maximum lower)
 439  *      for the transfer.
 440  *
 441  *      If the requested frequency is higher or lower than that is supported
 442  *      by the QSPI controller the driver will set the highest or lowest
 443  *      frequency supported by controller.
 444  */
 445 static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
 446                                  struct spi_device *qspi)
 447 {
 448         ulong clk_rate;
 449         u32 config_reg, baud_rate_val = 0;
 450
 451         /* Set the clock frequency */
 452         /* If req_hz == 0, default to lowest speed */
 453         clk_rate = clk_get_rate(xqspi->refclk);
 454
 455         while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
 456                (clk_rate /
 457                 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
 458                 baud_rate_val++;
 459
 460         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 461
 462         /* Set the QSPI clock phase and clock polarity */
 463         config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
 464
 465         if (qspi->mode & SPI_CPHA)
 466                 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
 467         if (qspi->mode & SPI_CPOL)
 468                 config_reg |= GQSPI_CFG_CLK_POL_MASK;
 469
 470         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 471         config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
 472         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 473         return 0;
 474 }
 475
 476 /**
 477  * zynqmp_qspi_setup_op - Configure the QSPI controller
 478  * @qspi:       Pointer to the spi_device structure
 479  *
 480  * Sets the operational mode of QSPI controller for the next QSPI transfer,
 481  * baud rate and divisor value to setup the requested qspi clock.
 482  *
 483  * Return:      0 on success; error value otherwise.
 484  */
 485 static int zynqmp_qspi_setup_op(struct spi_device *qspi)
 486 {
 487         struct spi_controller *ctlr = qspi->master;
 488         struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
 489         struct device *dev = &ctlr->dev;
 490         int ret;
 491
 492         if (ctlr->busy)
 493                 return -EBUSY;
 494
 495         ret = clk_enable(xqspi->refclk);
 496         if (ret) {
 497                 dev_err(dev, "Cannot enable device clock.\n");
 498                 return ret;
 499         }
 500
 501         ret = clk_enable(xqspi->pclk);
 502         if (ret) {
 503                 dev_err(dev, "Cannot enable APB clock.\n");
 504                 clk_disable(xqspi->refclk);
 505                 return ret;
 506         }
 507         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 508
 509         return 0;
 510 }
 511
 512 /**
 513  * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
 514  *                              the FIFO or the bytes required to be
 515  *                              transmitted.
 516  * @xqspi:      Pointer to the zynqmp_qspi structure
 517  * @size:       Number of bytes to be copied from TX buffer to TX FIFO
 518  */
 519 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
 520 {
 521         u32 count = 0, intermediate;
 522
 523         while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
 524                 memcpy(&intermediate, xqspi->txbuf, 4);
 525                 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
 526
 527                 if (xqspi->bytes_to_transfer >= 4) {
 528                         xqspi->txbuf += 4;
 529                         xqspi->bytes_to_transfer -= 4;
 530                 } else {
 531                         xqspi->txbuf += xqspi->bytes_to_transfer;
 532                         xqspi->bytes_to_transfer = 0;
 533                 }
 534                 count++;
 535         }
 536 }
 537
 538 /**
 539  * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
 540  *                              the FIFO.
 541  * @xqspi:      Pointer to the zynqmp_qspi structure
 542  * @size:       Number of bytes to be copied from RX buffer to RX FIFO
 543  */
 544 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
 545 {
 546         ulong data;
 547         int count = 0;
 548
 549         while ((count < size) && (xqspi->bytes_to_receive > 0)) {
 550                 if (xqspi->bytes_to_receive >= 4) {
 551                         (*(u32 *)xqspi->rxbuf) =
 552                         zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 553                         xqspi->rxbuf += 4;
 554                         xqspi->bytes_to_receive -= 4;
 555                         count += 4;
 556                 } else {
 557                         data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 558                         count += xqspi->bytes_to_receive;
 559                         zynqmp_qspi_copy_read_data(xqspi, data,
 560                                                    xqspi->bytes_to_receive);
 561                         xqspi->bytes_to_receive = 0;
 562                 }
 563         }
 564 }
 565
 566 /**
 567  * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
 568  * @xqspi:      Pointer to the zynqmp_qspi structure
 569  * @nbits:      Transfer/Receive buswidth.
 570  * @genfifoentry:       Variable in which GENFIFO mask is saved
 571  */
 572 static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
 573                                     u32 genfifoentry)
 574 {
 575         u32 transfer_len = 0;
 576
 577         if (xqspi->txbuf) {
 578                 genfifoentry &= ~GQSPI_GENFIFO_RX;
 579                 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 580                 genfifoentry |= GQSPI_GENFIFO_TX;
 581                 transfer_len = xqspi->bytes_to_transfer;
 582         } else {
 583                 genfifoentry &= ~GQSPI_GENFIFO_TX;
 584                 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 585                 genfifoentry |= GQSPI_GENFIFO_RX;
 586                 if (xqspi->mode == GQSPI_MODE_DMA)
 587                         transfer_len = xqspi->dma_rx_bytes;
 588                 else
 589                         transfer_len = xqspi->bytes_to_receive;
 590         }
 591         genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
 592         xqspi->genfifoentry = genfifoentry;
 593
 594         if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
 595                 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 596                 genfifoentry |= transfer_len;
 597                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 598         } else {
 599                 int tempcount = transfer_len;
 600                 u32 exponent = 8;       /* 2^8 = 256 */
 601                 u8 imm_data = tempcount & 0xFF;
 602
 603                 tempcount &= ~(tempcount & 0xFF);
 604                 /* Immediate entry */
 605                 if (tempcount != 0) {
 606                         /* Exponent entries */
 607                         genfifoentry |= GQSPI_GENFIFO_EXP;
 608                         while (tempcount != 0) {
 609                                 if (tempcount & GQSPI_GENFIFO_EXP_START) {
 610                                         genfifoentry &=
 611                                                 ~GQSPI_GENFIFO_IMM_DATA_MASK;
 612                                         genfifoentry |= exponent;
 613                                         zynqmp_gqspi_write(xqspi,
 614                                                            GQSPI_GEN_FIFO_OFST,
 615                                                            genfifoentry);
 616                                 }
 617                                 tempcount = tempcount >> 1;
 618                                 exponent++;
 619                         }
 620                 }
 621                 if (imm_data != 0) {
 622                         genfifoentry &= ~GQSPI_GENFIFO_EXP;
 623                         genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 624                         genfifoentry |= (u8)(imm_data & 0xFF);
 625                         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
 626                                            genfifoentry);
 627                 }
 628         }
 629         if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
 630                 /* Dummy generic FIFO entry */
 631                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 632         }
 633 }
 634
 635 /**
 636  * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
 637  *                              controller
 638  * @xqspi:      zynqmp_qspi instance pointer
 639  *
 640  * This function handles DMA interrupt only.
 641  */
 642 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
 643 {
 644         u32 config_reg, genfifoentry;
 645
 646         dma_unmap_single(xqspi->dev, xqspi->dma_addr,
 647                          xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
 648         xqspi->rxbuf += xqspi->dma_rx_bytes;
 649         xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
 650         xqspi->dma_rx_bytes = 0;
 651
 652         /* Disabling the DMA interrupts */
 653         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
 654                            GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 655
 656         if (xqspi->bytes_to_receive > 0) {
 657                 /* Switch to IO mode,for remaining bytes to receive */
 658                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 659                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 660                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 661
 662                 /* Initiate the transfer of remaining bytes */
 663                 genfifoentry = xqspi->genfifoentry;
 664                 genfifoentry |= xqspi->bytes_to_receive;
 665                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 666
 667                 /* Dummy generic FIFO entry */
 668                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 669
 670                 /* Manual start */
 671                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 672                                    (zynqmp_gqspi_read(xqspi,
 673                                                       GQSPI_CONFIG_OFST) |
 674                                    GQSPI_CFG_START_GEN_FIFO_MASK));
 675
 676                 /* Enable the RX interrupts for IO mode */
 677                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 678                                    GQSPI_IER_GENFIFOEMPTY_MASK |
 679                                    GQSPI_IER_RXNEMPTY_MASK |
 680                                    GQSPI_IER_RXEMPTY_MASK);
 681         }
 682 }
 683
 684 /**
 685  * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
 686  * @irq:        IRQ number
 687  * @dev_id:     Pointer to the xqspi structure
 688  *
 689  * This function handles TX empty only.
 690  * On TX empty interrupt this function reads the received data from RX FIFO
 691  * and fills the TX FIFO if there is any data remaining to be transferred.
 692  *
 693  * Return:      IRQ_HANDLED when interrupt is handled
 694  *              IRQ_NONE otherwise.
 695  */
 696 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
 697 {
 698         struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
 699         irqreturn_t ret = IRQ_NONE;
 700         u32 status, mask, dma_status = 0;
 701
 702         status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 703         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
 704         mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
 705
 706         /* Read and clear DMA status */
 707         if (xqspi->mode == GQSPI_MODE_DMA) {
 708                 dma_status =
 709                         zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
 710                 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 711                                    dma_status);
 712         }
 713
 714         if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
 715                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
 716                 ret = IRQ_HANDLED;
 717         }
 718
 719         if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
 720                 zynqmp_process_dma_irq(xqspi);
 721                 ret = IRQ_HANDLED;
 722         } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
 723                         (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
 724                 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
 725                 ret = IRQ_HANDLED;
 726         }
 727
 728         if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
 729             ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
 730                 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
 731                 complete(&xqspi->data_completion);
 732                 ret = IRQ_HANDLED;
 733         }
 734         return ret;
 735 }
 736
 737 /**
 738  * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
 739  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 740  */
 741 static void zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
 742 {
 743         u32 rx_bytes, rx_rem, config_reg;
 744         dma_addr_t addr;
 745         u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
 746
 747         if (xqspi->bytes_to_receive < 8 ||
 748             ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
 749                 /* Setting to IO mode */
 750                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 751                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 752                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 753                 xqspi->mode = GQSPI_MODE_IO;
 754                 xqspi->dma_rx_bytes = 0;
 755                 return;
 756         }
 757
 758         rx_rem = xqspi->bytes_to_receive % 4;
 759         rx_bytes = (xqspi->bytes_to_receive - rx_rem);
 760
 761         addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
 762                               rx_bytes, DMA_FROM_DEVICE);
 763         if (dma_mapping_error(xqspi->dev, addr))
 764                 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
 765
 766         xqspi->dma_rx_bytes = rx_bytes;
 767         xqspi->dma_addr = addr;
 768         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
 769                            (u32)(addr & 0xffffffff));
 770         addr = ((addr >> 16) >> 16);
 771         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
 772                            ((u32)addr) & 0xfff);
 773
 774         /* Enabling the DMA mode */
 775         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 776         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 777         config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
 778         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 779
 780         /* Switch to DMA mode */
 781         xqspi->mode = GQSPI_MODE_DMA;
 782
 783         /* Write the number of bytes to transfer */
 784         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
 785 }
 786
 787 /**
 788  * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
 789  *                      TX FIFO, and fills the TX FIFO with as many
 790  *                      bytes as possible.
 791  * @xqspi:      Pointer to the GQSPI instance.
 792  * @tx_nbits:   Transfer buswidth.
 793  * @genfifoentry:       Variable in which GENFIFO mask is returned
 794  *                      to calling function
 795  */
 796 static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
 797                                  u32 genfifoentry)
 798 {
 799         u32 config_reg;
 800
 801         zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
 802         zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
 803         if (xqspi->mode == GQSPI_MODE_DMA) {
 804                 config_reg = zynqmp_gqspi_read(xqspi,
 805                                                GQSPI_CONFIG_OFST);
 806                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 807                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 808                                    config_reg);
 809                 xqspi->mode = GQSPI_MODE_IO;
 810         }
 811 }
 812
 813 /**
 814  * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
 815  *                              RX DMA operation.
 816  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 817  * @rx_nbits:   Receive buswidth.
 818  * @genfifoentry:       genfifoentry is pointer to the variable in which
 819  *                      GENFIFO mask is returned to calling function
 820  */
 821 static void zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
 822                                 u32 genfifoentry)
 823 {
 824         zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
 825         zynqmp_qspi_setuprxdma(xqspi);
 826 }
 827
 828 /**
 829  * zynqmp_qspi_suspend - Suspend method for the QSPI driver
 830  * @dev:        Address of the platform_device structure
 831  *
 832  * This function stops the QSPI driver queue and disables the QSPI controller
 833  *
 834  * Return:      Always 0
 835  */
 836 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
 837 {
 838         struct spi_controller *ctlr = dev_get_drvdata(dev);
 839         struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
 840
 841         spi_controller_suspend(ctlr);
 842
 843         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 844
 845         return 0;
 846 }
 847
 848 /**
 849  * zynqmp_qspi_resume - Resume method for the QSPI driver
 850  * @dev:        Address of the platform_device structure
 851  *
 852  * The function starts the QSPI driver queue and initializes the QSPI
 853  * controller
 854  *
 855  * Return:      0 on success; error value otherwise
 856  */
 857 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
 858 {
 859         struct spi_controller *ctlr = dev_get_drvdata(dev);
 860         struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
 861         int ret = 0;
 862
 863         ret = clk_enable(xqspi->pclk);
 864         if (ret) {
 865                 dev_err(dev, "Cannot enable APB clock.\n");
 866                 return ret;
 867         }
 868
 869         ret = clk_enable(xqspi->refclk);
 870         if (ret) {
 871                 dev_err(dev, "Cannot enable device clock.\n");
 872                 clk_disable(xqspi->pclk);
 873                 return ret;
 874         }
 875
 876         spi_controller_resume(ctlr);
 877
 878         clk_disable(xqspi->refclk);
 879         clk_disable(xqspi->pclk);
 880         return 0;
 881 }
 882
 883 /**
 884  * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
 885  * @dev:        Address of the platform_device structure
 886  *
 887  * This function disables the clocks
 888  *
 889  * Return:      Always 0
 890  */
 891 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
 892 {
 893         struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_get_drvdata(dev);
 894
 895         clk_disable(xqspi->refclk);
 896         clk_disable(xqspi->pclk);
 897
 898         return 0;
 899 }
 900
 901 /**
 902  * zynqmp_runtime_resume - Runtime resume method for the SPI driver
 903  * @dev:        Address of the platform_device structure
 904  *
 905  * This function enables the clocks
 906  *
 907  * Return:      0 on success and error value on error
 908  */
 909 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
 910 {
 911         struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_get_drvdata(dev);
 912         int ret;
 913
 914         ret = clk_enable(xqspi->pclk);
 915         if (ret) {
 916                 dev_err(dev, "Cannot enable APB clock.\n");
 917                 return ret;
 918         }
 919
 920         ret = clk_enable(xqspi->refclk);
 921         if (ret) {
 922                 dev_err(dev, "Cannot enable device clock.\n");
 923                 clk_disable(xqspi->pclk);
 924                 return ret;
 925         }
 926
 927         return 0;
 928 }
 929
 930 /**
 931  * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
 932  * @mem: The SPI memory
 933  * @op: The memory operation to execute
 934  *
 935  * Executes a memory operation.
 936  *
 937  * This function first selects the chip and starts the memory operation.
 938  *
 939  * Return: 0 in case of success, a negative error code otherwise.
 940  */
 941 static int zynqmp_qspi_exec_op(struct spi_mem *mem,
 942                                const struct spi_mem_op *op)
 943 {
 944         struct zynqmp_qspi *xqspi = spi_controller_get_devdata
 945                                     (mem->spi->master);
 946         int err = 0, i;
 947         u8 *tmpbuf;
 948         u32 genfifoentry = 0;
 949
 950         dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
 951                 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 952                 op->dummy.buswidth, op->data.buswidth);
 953
 954         zynqmp_qspi_config_op(xqspi, mem->spi);
 955         zynqmp_qspi_chipselect(mem->spi, false);
 956         genfifoentry |= xqspi->genfifocs;
 957         genfifoentry |= xqspi->genfifobus;
 958
 959         if (op->cmd.opcode) {
 960                 tmpbuf = kzalloc(op->cmd.nbytes, GFP_KERNEL | GFP_DMA);
 961                 if (!tmpbuf)
 962                         return -ENOMEM;
 963                 tmpbuf[0] = op->cmd.opcode;
 964                 reinit_completion(&xqspi->data_completion);
 965                 xqspi->txbuf = tmpbuf;
 966                 xqspi->rxbuf = NULL;
 967                 xqspi->bytes_to_transfer = op->cmd.nbytes;
 968                 xqspi->bytes_to_receive = 0;
 969                 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
 970                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 971                                    zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 972                                    GQSPI_CFG_START_GEN_FIFO_MASK);
 973                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 974                                    GQSPI_IER_GENFIFOEMPTY_MASK |
 975                                    GQSPI_IER_TXNOT_FULL_MASK);
 976                 if (!wait_for_completion_interruptible_timeout
 977                     (&xqspi->data_completion, msecs_to_jiffies(1000))) {
 978                         err = -ETIMEDOUT;
 979                         kfree(tmpbuf);
 980                         goto return_err;
 981                 }
 982                 kfree(tmpbuf);
 983         }
 984
 985         if (op->addr.nbytes) {
 986                 for (i = 0; i < op->addr.nbytes; i++) {
 987                         *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
 988                                         (8 * (op->addr.nbytes - i - 1));
 989                 }
 990
 991                 reinit_completion(&xqspi->data_completion);
 992                 xqspi->rxbuf = NULL;
 993                 xqspi->bytes_to_transfer = op->addr.nbytes;
 994                 xqspi->bytes_to_receive = 0;
 995                 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
 996                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 997                                    zynqmp_gqspi_read(xqspi,
 998                                                      GQSPI_CONFIG_OFST) |
 999                                    GQSPI_CFG_START_GEN_FIFO_MASK);
1000                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1001                                    GQSPI_IER_TXEMPTY_MASK |
1002                                    GQSPI_IER_GENFIFOEMPTY_MASK |
1003                                    GQSPI_IER_TXNOT_FULL_MASK);
1004                 if (!wait_for_completion_interruptible_timeout
1005                     (&xqspi->data_completion, msecs_to_jiffies(1000))) {
1006                         err = -ETIMEDOUT;
1007                         goto return_err;
1008                 }
1009         }
1010
1011         if (op->dummy.nbytes) {
1012                 tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL | GFP_DMA);
1013                 if (!tmpbuf)
1014                         return -ENOMEM;
1015                 memset(tmpbuf, 0xff, op->dummy.nbytes);
1016                 reinit_completion(&xqspi->data_completion);
1017                 xqspi->txbuf = tmpbuf;
1018                 xqspi->rxbuf = NULL;
1019                 xqspi->bytes_to_transfer = op->dummy.nbytes;
1020                 xqspi->bytes_to_receive = 0;
1021                 zynqmp_qspi_write_op(xqspi, op->dummy.buswidth,
1022                                      genfifoentry);
1023                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1024                                    zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1025                                    GQSPI_CFG_START_GEN_FIFO_MASK);
1026                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1027                                    GQSPI_IER_TXEMPTY_MASK |
1028                                    GQSPI_IER_GENFIFOEMPTY_MASK |
1029                                    GQSPI_IER_TXNOT_FULL_MASK);
1030                 if (!wait_for_completion_interruptible_timeout
1031                     (&xqspi->data_completion, msecs_to_jiffies(1000))) {
1032                         err = -ETIMEDOUT;
1033                         kfree(tmpbuf);
1034                         goto return_err;
1035                 }
1036
1037                 kfree(tmpbuf);
1038         }
1039
1040         if (op->data.nbytes) {
1041                 reinit_completion(&xqspi->data_completion);
1042                 if (op->data.dir == SPI_MEM_DATA_OUT) {
1043                         xqspi->txbuf = (u8 *)op->data.buf.out;
1044                         xqspi->rxbuf = NULL;
1045                         xqspi->bytes_to_transfer = op->data.nbytes;
1046                         xqspi->bytes_to_receive = 0;
1047                         zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1048                                              genfifoentry);
1049                         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1050                                            zynqmp_gqspi_read
1051                                            (xqspi, GQSPI_CONFIG_OFST) |
1052                                            GQSPI_CFG_START_GEN_FIFO_MASK);
1053                         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1054                                            GQSPI_IER_TXEMPTY_MASK |
1055                                            GQSPI_IER_GENFIFOEMPTY_MASK |
1056                                            GQSPI_IER_TXNOT_FULL_MASK);
1057                 } else {
1058                         xqspi->txbuf = NULL;
1059                         xqspi->rxbuf = (u8 *)op->data.buf.in;
1060                         xqspi->bytes_to_receive = op->data.nbytes;
1061                         xqspi->bytes_to_transfer = 0;
1062                         zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1063                                             genfifoentry);
1064                         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1065                                            zynqmp_gqspi_read
1066                                            (xqspi, GQSPI_CONFIG_OFST) |
1067                                            GQSPI_CFG_START_GEN_FIFO_MASK);
1068                         if (xqspi->mode == GQSPI_MODE_DMA) {
1069                                 zynqmp_gqspi_write
1070                                         (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1071                                          GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1072                         } else {
1073                                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1074                                                    GQSPI_IER_GENFIFOEMPTY_MASK |
1075                                                    GQSPI_IER_RXNEMPTY_MASK |
1076                                                    GQSPI_IER_RXEMPTY_MASK);
1077                         }
1078                 }
1079                 if (!wait_for_completion_interruptible_timeout
1080                     (&xqspi->data_completion, msecs_to_jiffies(1000)))
1081                         err = -ETIMEDOUT;
1082         }
1083
1084 return_err:
1085
1086         zynqmp_qspi_chipselect(mem->spi, true);
1087
1088         return err;
1089 }
1090
1091 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1092         SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1093                            zynqmp_runtime_resume, NULL)
1094         SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1095 };
1096
1097 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1098         .exec_op = zynqmp_qspi_exec_op,
1099 };
1100
1101 /**
1102  * zynqmp_qspi_probe - Probe method for the QSPI driver
1103  * @pdev:       Pointer to the platform_device structure
1104  *
1105  * This function initializes the driver data structures and the hardware.
1106  *
1107  * Return:      0 on success; error value otherwise
1108  */
1109 static int zynqmp_qspi_probe(struct platform_device *pdev)
1110 {
1111         int ret = 0;
1112         struct spi_controller *ctlr;
1113         struct zynqmp_qspi *xqspi;
1114         struct device *dev = &pdev->dev;
1115         struct device_node *np = dev->of_node;
1116
1117         ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1118         if (!ctlr)
1119                 return -ENOMEM;
1120
1121         xqspi = spi_controller_get_devdata(ctlr);
1122         xqspi->dev = dev;
1123         platform_set_drvdata(pdev, xqspi);
1124
1125         xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1126         if (IS_ERR(xqspi->regs)) {
1127                 ret = PTR_ERR(xqspi->regs);
1128                 goto remove_master;
1129         }
1130
1131         xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1132         if (IS_ERR(xqspi->pclk)) {
1133                 dev_err(dev, "pclk clock not found.\n");
1134                 ret = PTR_ERR(xqspi->pclk);
1135                 goto remove_master;
1136         }
1137
1138         init_completion(&xqspi->data_completion);
1139
1140         xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1141         if (IS_ERR(xqspi->refclk)) {
1142                 dev_err(dev, "ref_clk clock not found.\n");
1143                 ret = PTR_ERR(xqspi->refclk);
1144                 goto clk_dis_pclk;
1145         }
1146
1147         ret = clk_prepare_enable(xqspi->pclk);
1148         if (ret) {
1149                 dev_err(dev, "Unable to enable APB clock.\n");
1150                 goto remove_master;
1151         }
1152
1153         ret = clk_prepare_enable(xqspi->refclk);
1154         if (ret) {
1155                 dev_err(dev, "Unable to enable device clock.\n");
1156                 goto clk_dis_pclk;
1157         }
1158
1159         pm_runtime_use_autosuspend(&pdev->dev);
1160         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1161         pm_runtime_set_active(&pdev->dev);
1162         pm_runtime_enable(&pdev->dev);
1163         /* QSPI controller initializations */
1164         zynqmp_qspi_init_hw(xqspi);
1165
1166         pm_runtime_mark_last_busy(&pdev->dev);
1167         pm_runtime_put_autosuspend(&pdev->dev);
1168         xqspi->irq = platform_get_irq(pdev, 0);
1169         if (xqspi->irq <= 0) {
1170                 ret = -ENXIO;
1171                 goto clk_dis_all;
1172         }
1173         ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1174                                0, pdev->name, xqspi);
1175         if (ret != 0) {
1176                 ret = -ENXIO;
1177                 dev_err(dev, "request_irq failed\n");
1178                 goto clk_dis_all;
1179         }
1180
1181         ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1182         ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1183         ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1184         ctlr->setup = zynqmp_qspi_setup_op;
1185         ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1186         ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1187         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1188                             SPI_TX_DUAL | SPI_TX_QUAD;
1189         ctlr->dev.of_node = np;
1190
1191         ret = devm_spi_register_controller(&pdev->dev, ctlr);
1192         if (ret) {
1193                 dev_err(&pdev->dev, "spi_register_controller failed\n");
1194                 goto clk_dis_all;
1195         }
1196
1197         return 0;
1198
1199 clk_dis_all:
1200         pm_runtime_set_suspended(&pdev->dev);
1201         pm_runtime_disable(&pdev->dev);
1202         clk_disable_unprepare(xqspi->refclk);
1203 clk_dis_pclk:
1204         clk_disable_unprepare(xqspi->pclk);
1205 remove_master:
1206         spi_controller_put(ctlr);
1207
1208         return ret;
1209 }
1210
1211 /**
1212  * zynqmp_qspi_remove - Remove method for the QSPI driver
1213  * @pdev:       Pointer to the platform_device structure
1214  *
1215  * This function is called if a device is physically removed from the system or
1216  * if the driver module is being unloaded. It frees all resources allocated to
1217  * the device.
1218  *
1219  * Return:      0 Always
1220  */
1221 static int zynqmp_qspi_remove(struct platform_device *pdev)
1222 {
1223         struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
1224
1225         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1226         clk_disable_unprepare(xqspi->refclk);
1227         clk_disable_unprepare(xqspi->pclk);
1228         pm_runtime_set_suspended(&pdev->dev);
1229         pm_runtime_disable(&pdev->dev);
1230
1231         return 0;
1232 }
1233
1234 static const struct of_device_id zynqmp_qspi_of_match[] = {
1235         { .compatible = "xlnx,zynqmp-qspi-1.0", },
1236         { /* End of table */ }
1237 };
1238
1239 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1240
1241 static struct platform_driver zynqmp_qspi_driver = {
1242         .probe = zynqmp_qspi_probe,
1243         .remove = zynqmp_qspi_remove,
1244         .driver = {
1245                 .name = "zynqmp-qspi",
1246                 .of_match_table = zynqmp_qspi_of_match,
1247                 .pm = &zynqmp_qspi_dev_pm_ops,
1248         },
1249 };
1250
1251 module_platform_driver(zynqmp_qspi_driver);
1252
1253 MODULE_AUTHOR("Xilinx, Inc.");
1254 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1255 MODULE_LICENSE("GPL");