drivers/spi/spi-tegra114.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * SPI driver for NVIDIA's Tegra114 SPI Controller.
   4  *
   5  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmapool.h>
  14 #include <linux/err.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/kthread.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/reset.h>
  25 #include <linux/spi/spi.h>
  26
  27 #define SPI_COMMAND1                            0x000
  28 #define SPI_BIT_LENGTH(x)                       (((x) & 0x1f) << 0)
  29 #define SPI_PACKED                              (1 << 5)
  30 #define SPI_TX_EN                               (1 << 11)
  31 #define SPI_RX_EN                               (1 << 12)
  32 #define SPI_BOTH_EN_BYTE                        (1 << 13)
  33 #define SPI_BOTH_EN_BIT                         (1 << 14)
  34 #define SPI_LSBYTE_FE                           (1 << 15)
  35 #define SPI_LSBIT_FE                            (1 << 16)
  36 #define SPI_BIDIROE                             (1 << 17)
  37 #define SPI_IDLE_SDA_DRIVE_LOW                  (0 << 18)
  38 #define SPI_IDLE_SDA_DRIVE_HIGH                 (1 << 18)
  39 #define SPI_IDLE_SDA_PULL_LOW                   (2 << 18)
  40 #define SPI_IDLE_SDA_PULL_HIGH                  (3 << 18)
  41 #define SPI_IDLE_SDA_MASK                       (3 << 18)
  42 #define SPI_CS_SW_VAL                           (1 << 20)
  43 #define SPI_CS_SW_HW                            (1 << 21)
  44 /* SPI_CS_POL_INACTIVE bits are default high */
  45                                                 /* n from 0 to 3 */
  46 #define SPI_CS_POL_INACTIVE(n)                  (1 << (22 + (n)))
  47 #define SPI_CS_POL_INACTIVE_MASK                (0xF << 22)
  48
  49 #define SPI_CS_SEL_0                            (0 << 26)
  50 #define SPI_CS_SEL_1                            (1 << 26)
  51 #define SPI_CS_SEL_2                            (2 << 26)
  52 #define SPI_CS_SEL_3                            (3 << 26)
  53 #define SPI_CS_SEL_MASK                         (3 << 26)
  54 #define SPI_CS_SEL(x)                           (((x) & 0x3) << 26)
  55 #define SPI_CONTROL_MODE_0                      (0 << 28)
  56 #define SPI_CONTROL_MODE_1                      (1 << 28)
  57 #define SPI_CONTROL_MODE_2                      (2 << 28)
  58 #define SPI_CONTROL_MODE_3                      (3 << 28)
  59 #define SPI_CONTROL_MODE_MASK                   (3 << 28)
  60 #define SPI_MODE_SEL(x)                         (((x) & 0x3) << 28)
  61 #define SPI_M_S                                 (1 << 30)
  62 #define SPI_PIO                                 (1 << 31)
  63
  64 #define SPI_COMMAND2                            0x004
  65 #define SPI_TX_TAP_DELAY(x)                     (((x) & 0x3F) << 6)
  66 #define SPI_RX_TAP_DELAY(x)                     (((x) & 0x3F) << 0)
  67
  68 #define SPI_CS_TIMING1                          0x008
  69 #define SPI_SETUP_HOLD(setup, hold)             (((setup) << 4) | (hold))
  70 #define SPI_CS_SETUP_HOLD(reg, cs, val)                 \
  71                 ((((val) & 0xFFu) << ((cs) * 8)) |      \
  72                 ((reg) & ~(0xFFu << ((cs) * 8))))
  73
  74 #define SPI_CS_TIMING2                          0x00C
  75 #define CYCLES_BETWEEN_PACKETS_0(x)             (((x) & 0x1F) << 0)
  76 #define CS_ACTIVE_BETWEEN_PACKETS_0             (1 << 5)
  77 #define CYCLES_BETWEEN_PACKETS_1(x)             (((x) & 0x1F) << 8)
  78 #define CS_ACTIVE_BETWEEN_PACKETS_1             (1 << 13)
  79 #define CYCLES_BETWEEN_PACKETS_2(x)             (((x) & 0x1F) << 16)
  80 #define CS_ACTIVE_BETWEEN_PACKETS_2             (1 << 21)
  81 #define CYCLES_BETWEEN_PACKETS_3(x)             (((x) & 0x1F) << 24)
  82 #define CS_ACTIVE_BETWEEN_PACKETS_3             (1 << 29)
  83 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)         \
  84                 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) |      \
  85                         ((reg) & ~(1 << ((cs) * 8 + 5))))
  86 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)            \
  87                 (reg = (((val) & 0x1F) << ((cs) * 8)) |         \
  88                         ((reg) & ~(0x1F << ((cs) * 8))))
  89 #define MAX_SETUP_HOLD_CYCLES                   16
  90 #define MAX_INACTIVE_CYCLES                     32
  91
  92 #define SPI_TRANS_STATUS                        0x010
  93 #define SPI_BLK_CNT(val)                        (((val) >> 0) & 0xFFFF)
  94 #define SPI_SLV_IDLE_COUNT(val)                 (((val) >> 16) & 0xFF)
  95 #define SPI_RDY                                 (1 << 30)
  96
  97 #define SPI_FIFO_STATUS                         0x014
  98 #define SPI_RX_FIFO_EMPTY                       (1 << 0)
  99 #define SPI_RX_FIFO_FULL                        (1 << 1)
 100 #define SPI_TX_FIFO_EMPTY                       (1 << 2)
 101 #define SPI_TX_FIFO_FULL                        (1 << 3)
 102 #define SPI_RX_FIFO_UNF                         (1 << 4)
 103 #define SPI_RX_FIFO_OVF                         (1 << 5)
 104 #define SPI_TX_FIFO_UNF                         (1 << 6)
 105 #define SPI_TX_FIFO_OVF                         (1 << 7)
 106 #define SPI_ERR                                 (1 << 8)
 107 #define SPI_TX_FIFO_FLUSH                       (1 << 14)
 108 #define SPI_RX_FIFO_FLUSH                       (1 << 15)
 109 #define SPI_TX_FIFO_EMPTY_COUNT(val)            (((val) >> 16) & 0x7F)
 110 #define SPI_RX_FIFO_FULL_COUNT(val)             (((val) >> 23) & 0x7F)
 111 #define SPI_FRAME_END                           (1 << 30)
 112 #define SPI_CS_INACTIVE                         (1 << 31)
 113
 114 #define SPI_FIFO_ERROR                          (SPI_RX_FIFO_UNF | \
 115                         SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
 116 #define SPI_FIFO_EMPTY                  (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
 117
 118 #define SPI_TX_DATA                             0x018
 119 #define SPI_RX_DATA                             0x01C
 120
 121 #define SPI_DMA_CTL                             0x020
 122 #define SPI_TX_TRIG_1                           (0 << 15)
 123 #define SPI_TX_TRIG_4                           (1 << 15)
 124 #define SPI_TX_TRIG_8                           (2 << 15)
 125 #define SPI_TX_TRIG_16                          (3 << 15)
 126 #define SPI_TX_TRIG_MASK                        (3 << 15)
 127 #define SPI_RX_TRIG_1                           (0 << 19)
 128 #define SPI_RX_TRIG_4                           (1 << 19)
 129 #define SPI_RX_TRIG_8                           (2 << 19)
 130 #define SPI_RX_TRIG_16                          (3 << 19)
 131 #define SPI_RX_TRIG_MASK                        (3 << 19)
 132 #define SPI_IE_TX                               (1 << 28)
 133 #define SPI_IE_RX                               (1 << 29)
 134 #define SPI_CONT                                (1 << 30)
 135 #define SPI_DMA                                 (1 << 31)
 136 #define SPI_DMA_EN                              SPI_DMA
 137
 138 #define SPI_DMA_BLK                             0x024
 139 #define SPI_DMA_BLK_SET(x)                      (((x) & 0xFFFF) << 0)
 140
 141 #define SPI_TX_FIFO                             0x108
 142 #define SPI_RX_FIFO                             0x188
 143 #define SPI_INTR_MASK                           0x18c
 144 #define SPI_INTR_ALL_MASK                       (0x1fUL << 25)
 145 #define MAX_CHIP_SELECT                         4
 146 #define SPI_FIFO_DEPTH                          64
 147 #define DATA_DIR_TX                             (1 << 0)
 148 #define DATA_DIR_RX                             (1 << 1)
 149
 150 #define SPI_DMA_TIMEOUT                         (msecs_to_jiffies(1000))
 151 #define DEFAULT_SPI_DMA_BUF_LEN                 (16*1024)
 152 #define TX_FIFO_EMPTY_COUNT_MAX                 SPI_TX_FIFO_EMPTY_COUNT(0x40)
 153 #define RX_FIFO_FULL_COUNT_ZERO                 SPI_RX_FIFO_FULL_COUNT(0)
 154 #define MAX_HOLD_CYCLES                         16
 155 #define SPI_DEFAULT_SPEED                       25000000
 156
 157 struct tegra_spi_soc_data {
 158         bool has_intr_mask_reg;
 159 };
 160
 161 struct tegra_spi_client_data {
 162         int tx_clk_tap_delay;
 163         int rx_clk_tap_delay;
 164 };
 165
 166 struct tegra_spi_data {
 167         struct device                           *dev;
 168         struct spi_master                       *master;
 169         spinlock_t                              lock;
 170
 171         struct clk                              *clk;
 172         struct reset_control                    *rst;
 173         void __iomem                            *base;
 174         phys_addr_t                             phys;
 175         unsigned                                irq;
 176         u32                                     cur_speed;
 177
 178         struct spi_device                       *cur_spi;
 179         struct spi_device                       *cs_control;
 180         unsigned                                cur_pos;
 181         unsigned                                words_per_32bit;
 182         unsigned                                bytes_per_word;
 183         unsigned                                curr_dma_words;
 184         unsigned                                cur_direction;
 185
 186         unsigned                                cur_rx_pos;
 187         unsigned                                cur_tx_pos;
 188
 189         unsigned                                dma_buf_size;
 190         unsigned                                max_buf_size;
 191         bool                                    is_curr_dma_xfer;
 192         bool                                    use_hw_based_cs;
 193
 194         struct completion                       rx_dma_complete;
 195         struct completion                       tx_dma_complete;
 196
 197         u32                                     tx_status;
 198         u32                                     rx_status;
 199         u32                                     status_reg;
 200         bool                                    is_packed;
 201
 202         u32                                     command1_reg;
 203         u32                                     dma_control_reg;
 204         u32                                     def_command1_reg;
 205         u32                                     def_command2_reg;
 206         u32                                     spi_cs_timing1;
 207         u32                                     spi_cs_timing2;
 208         u8                                      last_used_cs;
 209
 210         struct completion                       xfer_completion;
 211         struct spi_transfer                     *curr_xfer;
 212         struct dma_chan                         *rx_dma_chan;
 213         u32                                     *rx_dma_buf;
 214         dma_addr_t                              rx_dma_phys;
 215         struct dma_async_tx_descriptor          *rx_dma_desc;
 216
 217         struct dma_chan                         *tx_dma_chan;
 218         u32                                     *tx_dma_buf;
 219         dma_addr_t                              tx_dma_phys;
 220         struct dma_async_tx_descriptor          *tx_dma_desc;
 221         const struct tegra_spi_soc_data         *soc_data;
 222 };
 223
 224 static int tegra_spi_runtime_suspend(struct device *dev);
 225 static int tegra_spi_runtime_resume(struct device *dev);
 226
 227 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
 228                 unsigned long reg)
 229 {
 230         return readl(tspi->base + reg);
 231 }
 232
 233 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
 234                 u32 val, unsigned long reg)
 235 {
 236         writel(val, tspi->base + reg);
 237
 238         /* Read back register to make sure that register writes completed */
 239         if (reg != SPI_TX_FIFO)
 240                 readl(tspi->base + SPI_COMMAND1);
 241 }
 242
 243 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
 244 {
 245         u32 val;
 246
 247         /* Write 1 to clear status register */
 248         val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
 249         tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
 250
 251         /* Clear fifo status error if any */
 252         val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 253         if (val & SPI_ERR)
 254                 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
 255                                 SPI_FIFO_STATUS);
 256 }
 257
 258 static unsigned tegra_spi_calculate_curr_xfer_param(
 259         struct spi_device *spi, struct tegra_spi_data *tspi,
 260         struct spi_transfer *t)
 261 {
 262         unsigned remain_len = t->len - tspi->cur_pos;
 263         unsigned max_word;
 264         unsigned bits_per_word = t->bits_per_word;
 265         unsigned max_len;
 266         unsigned total_fifo_words;
 267
 268         tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
 269
 270         if ((bits_per_word == 8 || bits_per_word == 16 ||
 271              bits_per_word == 32) && t->len > 3) {
 272                 tspi->is_packed = true;
 273                 tspi->words_per_32bit = 32/bits_per_word;
 274         } else {
 275                 tspi->is_packed = false;
 276                 tspi->words_per_32bit = 1;
 277         }
 278
 279         if (tspi->is_packed) {
 280                 max_len = min(remain_len, tspi->max_buf_size);
 281                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
 282                 total_fifo_words = (max_len + 3) / 4;
 283         } else {
 284                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
 285                 max_word = min(max_word, tspi->max_buf_size/4);
 286                 tspi->curr_dma_words = max_word;
 287                 total_fifo_words = max_word;
 288         }
 289         return total_fifo_words;
 290 }
 291
 292 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 293         struct tegra_spi_data *tspi, struct spi_transfer *t)
 294 {
 295         unsigned nbytes;
 296         unsigned tx_empty_count;
 297         u32 fifo_status;
 298         unsigned max_n_32bit;
 299         unsigned i, count;
 300         unsigned int written_words;
 301         unsigned fifo_words_left;
 302         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 303
 304         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 305         tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
 306
 307         if (tspi->is_packed) {
 308                 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
 309                 written_words = min(fifo_words_left, tspi->curr_dma_words);
 310                 nbytes = written_words * tspi->bytes_per_word;
 311                 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
 312                 for (count = 0; count < max_n_32bit; count++) {
 313                         u32 x = 0;
 314
 315                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
 316                                 x |= (u32)(*tx_buf++) << (i * 8);
 317                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 318                 }
 319
 320                 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 321         } else {
 322                 unsigned int write_bytes;
 323                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 324                 written_words = max_n_32bit;
 325                 nbytes = written_words * tspi->bytes_per_word;
 326                 if (nbytes > t->len - tspi->cur_pos)
 327                         nbytes = t->len - tspi->cur_pos;
 328                 write_bytes = nbytes;
 329                 for (count = 0; count < max_n_32bit; count++) {
 330                         u32 x = 0;
 331
 332                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
 333                                                         i++, nbytes--)
 334                                 x |= (u32)(*tx_buf++) << (i * 8);
 335                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 336                 }
 337
 338                 tspi->cur_tx_pos += write_bytes;
 339         }
 340
 341         return written_words;
 342 }
 343
 344 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
 345                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 346 {
 347         unsigned rx_full_count;
 348         u32 fifo_status;
 349         unsigned i, count;
 350         unsigned int read_words = 0;
 351         unsigned len;
 352         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
 353
 354         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 355         rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
 356         if (tspi->is_packed) {
 357                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 358                 for (count = 0; count < rx_full_count; count++) {
 359                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 360
 361                         for (i = 0; len && (i < 4); i++, len--)
 362                                 *rx_buf++ = (x >> i*8) & 0xFF;
 363                 }
 364                 read_words += tspi->curr_dma_words;
 365                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 366         } else {
 367                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 368                 u8 bytes_per_word = tspi->bytes_per_word;
 369                 unsigned int read_bytes;
 370
 371                 len = rx_full_count * bytes_per_word;
 372                 if (len > t->len - tspi->cur_pos)
 373                         len = t->len - tspi->cur_pos;
 374                 read_bytes = len;
 375                 for (count = 0; count < rx_full_count; count++) {
 376                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
 377
 378                         for (i = 0; len && (i < bytes_per_word); i++, len--)
 379                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 380                 }
 381                 read_words += rx_full_count;
 382                 tspi->cur_rx_pos += read_bytes;
 383         }
 384
 385         return read_words;
 386 }
 387
 388 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 389                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 390 {
 391         /* Make the dma buffer to read by cpu */
 392         dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
 393                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 394
 395         if (tspi->is_packed) {
 396                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 397
 398                 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
 399                 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 400         } else {
 401                 unsigned int i;
 402                 unsigned int count;
 403                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 404                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 405                 unsigned int write_bytes;
 406
 407                 if (consume > t->len - tspi->cur_pos)
 408                         consume = t->len - tspi->cur_pos;
 409                 write_bytes = consume;
 410                 for (count = 0; count < tspi->curr_dma_words; count++) {
 411                         u32 x = 0;
 412
 413                         for (i = 0; consume && (i < tspi->bytes_per_word);
 414                                                         i++, consume--)
 415                                 x |= (u32)(*tx_buf++) << (i * 8);
 416                         tspi->tx_dma_buf[count] = x;
 417                 }
 418
 419                 tspi->cur_tx_pos += write_bytes;
 420         }
 421
 422         /* Make the dma buffer to read by dma */
 423         dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
 424                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 425 }
 426
 427 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
 428                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 429 {
 430         /* Make the dma buffer to read by cpu */
 431         dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
 432                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 433
 434         if (tspi->is_packed) {
 435                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 436
 437                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
 438                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 439         } else {
 440                 unsigned int i;
 441                 unsigned int count;
 442                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 443                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 444                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 445                 unsigned int read_bytes;
 446
 447                 if (consume > t->len - tspi->cur_pos)
 448                         consume = t->len - tspi->cur_pos;
 449                 read_bytes = consume;
 450                 for (count = 0; count < tspi->curr_dma_words; count++) {
 451                         u32 x = tspi->rx_dma_buf[count] & rx_mask;
 452
 453                         for (i = 0; consume && (i < tspi->bytes_per_word);
 454                                                         i++, consume--)
 455                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 456                 }
 457
 458                 tspi->cur_rx_pos += read_bytes;
 459         }
 460
 461         /* Make the dma buffer to read by dma */
 462         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 463                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 464 }
 465
 466 static void tegra_spi_dma_complete(void *args)
 467 {
 468         struct completion *dma_complete = args;
 469
 470         complete(dma_complete);
 471 }
 472
 473 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
 474 {
 475         reinit_completion(&tspi->tx_dma_complete);
 476         tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
 477                                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
 478                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 479         if (!tspi->tx_dma_desc) {
 480                 dev_err(tspi->dev, "Not able to get desc for Tx\n");
 481                 return -EIO;
 482         }
 483
 484         tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
 485         tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
 486
 487         dmaengine_submit(tspi->tx_dma_desc);
 488         dma_async_issue_pending(tspi->tx_dma_chan);
 489         return 0;
 490 }
 491
 492 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
 493 {
 494         reinit_completion(&tspi->rx_dma_complete);
 495         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
 496                                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
 497                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 498         if (!tspi->rx_dma_desc) {
 499                 dev_err(tspi->dev, "Not able to get desc for Rx\n");
 500                 return -EIO;
 501         }
 502
 503         tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
 504         tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
 505
 506         dmaengine_submit(tspi->rx_dma_desc);
 507         dma_async_issue_pending(tspi->rx_dma_chan);
 508         return 0;
 509 }
 510
 511 static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
 512 {
 513         unsigned long timeout = jiffies + HZ;
 514         u32 status;
 515
 516         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 517         if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 518                 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
 519                 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
 520                 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 521                         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 522                         if (time_after(jiffies, timeout)) {
 523                                 dev_err(tspi->dev,
 524                                         "timeout waiting for fifo flush\n");
 525                                 return -EIO;
 526                         }
 527
 528                         udelay(1);
 529                 }
 530         }
 531
 532         return 0;
 533 }
 534
 535 static int tegra_spi_start_dma_based_transfer(
 536                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 537 {
 538         u32 val;
 539         unsigned int len;
 540         int ret = 0;
 541         u8 dma_burst;
 542         struct dma_slave_config dma_sconfig = {0};
 543
 544         val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
 545         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 546
 547         if (tspi->is_packed)
 548                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
 549                                         4) * 4;
 550         else
 551                 len = tspi->curr_dma_words * 4;
 552
 553         /* Set attention level based on length of transfer */
 554         if (len & 0xF) {
 555                 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
 556                 dma_burst = 1;
 557         } else if (((len) >> 4) & 0x1) {
 558                 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
 559                 dma_burst = 4;
 560         } else {
 561                 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
 562                 dma_burst = 8;
 563         }
 564
 565         if (!tspi->soc_data->has_intr_mask_reg) {
 566                 if (tspi->cur_direction & DATA_DIR_TX)
 567                         val |= SPI_IE_TX;
 568
 569                 if (tspi->cur_direction & DATA_DIR_RX)
 570                         val |= SPI_IE_RX;
 571         }
 572
 573         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 574         tspi->dma_control_reg = val;
 575
 576         dma_sconfig.device_fc = true;
 577         if (tspi->cur_direction & DATA_DIR_TX) {
 578                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
 579                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 580                 dma_sconfig.dst_maxburst = dma_burst;
 581                 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
 582                 if (ret < 0) {
 583                         dev_err(tspi->dev,
 584                                 "DMA slave config failed: %d\n", ret);
 585                         return ret;
 586                 }
 587
 588                 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
 589                 ret = tegra_spi_start_tx_dma(tspi, len);
 590                 if (ret < 0) {
 591                         dev_err(tspi->dev,
 592                                 "Starting tx dma failed, err %d\n", ret);
 593                         return ret;
 594                 }
 595         }
 596
 597         if (tspi->cur_direction & DATA_DIR_RX) {
 598                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 599                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 600                 dma_sconfig.src_maxburst = dma_burst;
 601                 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
 602                 if (ret < 0) {
 603                         dev_err(tspi->dev,
 604                                 "DMA slave config failed: %d\n", ret);
 605                         return ret;
 606                 }
 607
 608                 /* Make the dma buffer to read by dma */
 609                 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 610                                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 611
 612                 ret = tegra_spi_start_rx_dma(tspi, len);
 613                 if (ret < 0) {
 614                         dev_err(tspi->dev,
 615                                 "Starting rx dma failed, err %d\n", ret);
 616                         if (tspi->cur_direction & DATA_DIR_TX)
 617                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 618                         return ret;
 619                 }
 620         }
 621         tspi->is_curr_dma_xfer = true;
 622         tspi->dma_control_reg = val;
 623
 624         val |= SPI_DMA_EN;
 625         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 626         return ret;
 627 }
 628
 629 static int tegra_spi_start_cpu_based_transfer(
 630                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 631 {
 632         u32 val;
 633         unsigned cur_words;
 634
 635         if (tspi->cur_direction & DATA_DIR_TX)
 636                 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
 637         else
 638                 cur_words = tspi->curr_dma_words;
 639
 640         val = SPI_DMA_BLK_SET(cur_words - 1);
 641         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 642
 643         val = 0;
 644         if (tspi->cur_direction & DATA_DIR_TX)
 645                 val |= SPI_IE_TX;
 646
 647         if (tspi->cur_direction & DATA_DIR_RX)
 648                 val |= SPI_IE_RX;
 649
 650         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 651         tspi->dma_control_reg = val;
 652
 653         tspi->is_curr_dma_xfer = false;
 654
 655         val = tspi->command1_reg;
 656         val |= SPI_PIO;
 657         tegra_spi_writel(tspi, val, SPI_COMMAND1);
 658         return 0;
 659 }
 660
 661 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 662                         bool dma_to_memory)
 663 {
 664         struct dma_chan *dma_chan;
 665         u32 *dma_buf;
 666         dma_addr_t dma_phys;
 667         int ret;
 668
 669         dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
 670         if (IS_ERR(dma_chan)) {
 671                 ret = PTR_ERR(dma_chan);
 672                 if (ret != -EPROBE_DEFER)
 673                         dev_err(tspi->dev,
 674                                 "Dma channel is not available: %d\n", ret);
 675                 return ret;
 676         }
 677
 678         dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
 679                                 &dma_phys, GFP_KERNEL);
 680         if (!dma_buf) {
 681                 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
 682                 dma_release_channel(dma_chan);
 683                 return -ENOMEM;
 684         }
 685
 686         if (dma_to_memory) {
 687                 tspi->rx_dma_chan = dma_chan;
 688                 tspi->rx_dma_buf = dma_buf;
 689                 tspi->rx_dma_phys = dma_phys;
 690         } else {
 691                 tspi->tx_dma_chan = dma_chan;
 692                 tspi->tx_dma_buf = dma_buf;
 693                 tspi->tx_dma_phys = dma_phys;
 694         }
 695         return 0;
 696 }
 697
 698 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 699         bool dma_to_memory)
 700 {
 701         u32 *dma_buf;
 702         dma_addr_t dma_phys;
 703         struct dma_chan *dma_chan;
 704
 705         if (dma_to_memory) {
 706                 dma_buf = tspi->rx_dma_buf;
 707                 dma_chan = tspi->rx_dma_chan;
 708                 dma_phys = tspi->rx_dma_phys;
 709                 tspi->rx_dma_chan = NULL;
 710                 tspi->rx_dma_buf = NULL;
 711         } else {
 712                 dma_buf = tspi->tx_dma_buf;
 713                 dma_chan = tspi->tx_dma_chan;
 714                 dma_phys = tspi->tx_dma_phys;
 715                 tspi->tx_dma_buf = NULL;
 716                 tspi->tx_dma_chan = NULL;
 717         }
 718         if (!dma_chan)
 719                 return;
 720
 721         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 722         dma_release_channel(dma_chan);
 723 }
 724
 725 static int tegra_spi_set_hw_cs_timing(struct spi_device *spi,
 726                                       struct spi_delay *setup,
 727                                       struct spi_delay *hold,
 728                                       struct spi_delay *inactive)
 729 {
 730         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 731         u8 setup_dly, hold_dly, inactive_dly;
 732         u32 setup_hold;
 733         u32 spi_cs_timing;
 734         u32 inactive_cycles;
 735         u8 cs_state;
 736
 737         if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) ||
 738             (hold && hold->unit != SPI_DELAY_UNIT_SCK) ||
 739             (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) {
 740                 dev_err(&spi->dev,
 741                         "Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n",
 742                         SPI_DELAY_UNIT_SCK);
 743                 return -EINVAL;
 744         }
 745
 746         setup_dly = setup ? setup->value : 0;
 747         hold_dly = hold ? hold->value : 0;
 748         inactive_dly = inactive ? inactive->value : 0;
 749
 750         setup_dly = min_t(u8, setup_dly, MAX_SETUP_HOLD_CYCLES);
 751         hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES);
 752         if (setup_dly && hold_dly) {
 753                 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
 754                 spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
 755                                                   spi->chip_select,
 756                                                   setup_hold);
 757                 if (tspi->spi_cs_timing1 != spi_cs_timing) {
 758                         tspi->spi_cs_timing1 = spi_cs_timing;
 759                         tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
 760                 }
 761         }
 762
 763         inactive_cycles = min_t(u8, inactive_dly, MAX_INACTIVE_CYCLES);
 764         if (inactive_cycles)
 765                 inactive_cycles--;
 766         cs_state = inactive_cycles ? 0 : 1;
 767         spi_cs_timing = tspi->spi_cs_timing2;
 768         SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
 769                                           cs_state);
 770         SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
 771                                        inactive_cycles);
 772         if (tspi->spi_cs_timing2 != spi_cs_timing) {
 773                 tspi->spi_cs_timing2 = spi_cs_timing;
 774                 tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
 775         }
 776
 777         return 0;
 778 }
 779
 780 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 781                                         struct spi_transfer *t,
 782                                         bool is_first_of_msg,
 783                                         bool is_single_xfer)
 784 {
 785         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 786         struct tegra_spi_client_data *cdata = spi->controller_data;
 787         u32 speed = t->speed_hz;
 788         u8 bits_per_word = t->bits_per_word;
 789         u32 command1, command2;
 790         int req_mode;
 791         u32 tx_tap = 0, rx_tap = 0;
 792
 793         if (speed != tspi->cur_speed) {
 794                 clk_set_rate(tspi->clk, speed);
 795                 tspi->cur_speed = speed;
 796         }
 797
 798         tspi->cur_spi = spi;
 799         tspi->cur_pos = 0;
 800         tspi->cur_rx_pos = 0;
 801         tspi->cur_tx_pos = 0;
 802         tspi->curr_xfer = t;
 803
 804         if (is_first_of_msg) {
 805                 tegra_spi_clear_status(tspi);
 806
 807                 command1 = tspi->def_command1_reg;
 808                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 809
 810                 command1 &= ~SPI_CONTROL_MODE_MASK;
 811                 req_mode = spi->mode & 0x3;
 812                 if (req_mode == SPI_MODE_0)
 813                         command1 |= SPI_CONTROL_MODE_0;
 814                 else if (req_mode == SPI_MODE_1)
 815                         command1 |= SPI_CONTROL_MODE_1;
 816                 else if (req_mode == SPI_MODE_2)
 817                         command1 |= SPI_CONTROL_MODE_2;
 818                 else if (req_mode == SPI_MODE_3)
 819                         command1 |= SPI_CONTROL_MODE_3;
 820
 821                 if (spi->mode & SPI_LSB_FIRST)
 822                         command1 |= SPI_LSBIT_FE;
 823                 else
 824                         command1 &= ~SPI_LSBIT_FE;
 825
 826                 if (spi->mode & SPI_3WIRE)
 827                         command1 |= SPI_BIDIROE;
 828                 else
 829                         command1 &= ~SPI_BIDIROE;
 830
 831                 if (tspi->cs_control) {
 832                         if (tspi->cs_control != spi)
 833                                 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 834                         tspi->cs_control = NULL;
 835                 } else
 836                         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 837
 838                 /* GPIO based chip select control */
 839                 if (spi->cs_gpiod)
 840                         gpiod_set_value(spi->cs_gpiod, 1);
 841
 842                 if (is_single_xfer && !(t->cs_change)) {
 843                         tspi->use_hw_based_cs = true;
 844                         command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
 845                 } else {
 846                         tspi->use_hw_based_cs = false;
 847                         command1 |= SPI_CS_SW_HW;
 848                         if (spi->mode & SPI_CS_HIGH)
 849                                 command1 |= SPI_CS_SW_VAL;
 850                         else
 851                                 command1 &= ~SPI_CS_SW_VAL;
 852                 }
 853
 854                 if (tspi->last_used_cs != spi->chip_select) {
 855                         if (cdata && cdata->tx_clk_tap_delay)
 856                                 tx_tap = cdata->tx_clk_tap_delay;
 857                         if (cdata && cdata->rx_clk_tap_delay)
 858                                 rx_tap = cdata->rx_clk_tap_delay;
 859                         command2 = SPI_TX_TAP_DELAY(tx_tap) |
 860                                    SPI_RX_TAP_DELAY(rx_tap);
 861                         if (command2 != tspi->def_command2_reg)
 862                                 tegra_spi_writel(tspi, command2, SPI_COMMAND2);
 863                         tspi->last_used_cs = spi->chip_select;
 864                 }
 865
 866         } else {
 867                 command1 = tspi->command1_reg;
 868                 command1 &= ~SPI_BIT_LENGTH(~0);
 869                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 870         }
 871
 872         return command1;
 873 }
 874
 875 static int tegra_spi_start_transfer_one(struct spi_device *spi,
 876                 struct spi_transfer *t, u32 command1)
 877 {
 878         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 879         unsigned total_fifo_words;
 880         int ret;
 881
 882         total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
 883
 884         if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL)
 885                 command1 |= SPI_BOTH_EN_BIT;
 886         else
 887                 command1 &= ~SPI_BOTH_EN_BIT;
 888
 889         if (tspi->is_packed)
 890                 command1 |= SPI_PACKED;
 891         else
 892                 command1 &= ~SPI_PACKED;
 893
 894         command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
 895         tspi->cur_direction = 0;
 896         if (t->rx_buf) {
 897                 command1 |= SPI_RX_EN;
 898                 tspi->cur_direction |= DATA_DIR_RX;
 899         }
 900         if (t->tx_buf) {
 901                 command1 |= SPI_TX_EN;
 902                 tspi->cur_direction |= DATA_DIR_TX;
 903         }
 904         command1 |= SPI_CS_SEL(spi->chip_select);
 905         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 906         tspi->command1_reg = command1;
 907
 908         dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
 909                 tspi->def_command1_reg, (unsigned)command1);
 910
 911         ret = tegra_spi_flush_fifos(tspi);
 912         if (ret < 0)
 913                 return ret;
 914         if (total_fifo_words > SPI_FIFO_DEPTH)
 915                 ret = tegra_spi_start_dma_based_transfer(tspi, t);
 916         else
 917                 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
 918         return ret;
 919 }
 920
 921 static struct tegra_spi_client_data
 922         *tegra_spi_parse_cdata_dt(struct spi_device *spi)
 923 {
 924         struct tegra_spi_client_data *cdata;
 925         struct device_node *slave_np;
 926
 927         slave_np = spi->dev.of_node;
 928         if (!slave_np) {
 929                 dev_dbg(&spi->dev, "device node not found\n");
 930                 return NULL;
 931         }
 932
 933         cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
 934         if (!cdata)
 935                 return NULL;
 936
 937         of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
 938                              &cdata->tx_clk_tap_delay);
 939         of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
 940                              &cdata->rx_clk_tap_delay);
 941         return cdata;
 942 }
 943
 944 static void tegra_spi_cleanup(struct spi_device *spi)
 945 {
 946         struct tegra_spi_client_data *cdata = spi->controller_data;
 947
 948         spi->controller_data = NULL;
 949         if (spi->dev.of_node)
 950                 kfree(cdata);
 951 }
 952
 953 static int tegra_spi_setup(struct spi_device *spi)
 954 {
 955         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 956         struct tegra_spi_client_data *cdata = spi->controller_data;
 957         u32 val;
 958         unsigned long flags;
 959         int ret;
 960
 961         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
 962                 spi->bits_per_word,
 963                 spi->mode & SPI_CPOL ? "" : "~",
 964                 spi->mode & SPI_CPHA ? "" : "~",
 965                 spi->max_speed_hz);
 966
 967         if (!cdata) {
 968                 cdata = tegra_spi_parse_cdata_dt(spi);
 969                 spi->controller_data = cdata;
 970         }
 971
 972         ret = pm_runtime_get_sync(tspi->dev);
 973         if (ret < 0) {
 974                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
 975                 if (cdata)
 976                         tegra_spi_cleanup(spi);
 977                 return ret;
 978         }
 979
 980         if (tspi->soc_data->has_intr_mask_reg) {
 981                 val = tegra_spi_readl(tspi, SPI_INTR_MASK);
 982                 val &= ~SPI_INTR_ALL_MASK;
 983                 tegra_spi_writel(tspi, val, SPI_INTR_MASK);
 984         }
 985
 986         spin_lock_irqsave(&tspi->lock, flags);
 987         /* GPIO based chip select control */
 988         if (spi->cs_gpiod)
 989                 gpiod_set_value(spi->cs_gpiod, 0);
 990
 991         val = tspi->def_command1_reg;
 992         if (spi->mode & SPI_CS_HIGH)
 993                 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
 994         else
 995                 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
 996         tspi->def_command1_reg = val;
 997         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 998         spin_unlock_irqrestore(&tspi->lock, flags);
 999
1000         pm_runtime_put(tspi->dev);
1001         return 0;
1002 }
1003
1004 static void tegra_spi_transfer_end(struct spi_device *spi)
1005 {
1006         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
1007         int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
1008
1009         /* GPIO based chip select control */
1010         if (spi->cs_gpiod)
1011                 gpiod_set_value(spi->cs_gpiod, 0);
1012
1013         if (!tspi->use_hw_based_cs) {
1014                 if (cs_val)
1015                         tspi->command1_reg |= SPI_CS_SW_VAL;
1016                 else
1017                         tspi->command1_reg &= ~SPI_CS_SW_VAL;
1018                 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1019         }
1020
1021         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1022 }
1023
1024 static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
1025 {
1026         dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
1027         dev_dbg(tspi->dev, "Command1:    0x%08x | Command2:    0x%08x\n",
1028                 tegra_spi_readl(tspi, SPI_COMMAND1),
1029                 tegra_spi_readl(tspi, SPI_COMMAND2));
1030         dev_dbg(tspi->dev, "DMA_CTL:     0x%08x | DMA_BLK:     0x%08x\n",
1031                 tegra_spi_readl(tspi, SPI_DMA_CTL),
1032                 tegra_spi_readl(tspi, SPI_DMA_BLK));
1033         dev_dbg(tspi->dev, "TRANS_STAT:  0x%08x | FIFO_STATUS: 0x%08x\n",
1034                 tegra_spi_readl(tspi, SPI_TRANS_STATUS),
1035                 tegra_spi_readl(tspi, SPI_FIFO_STATUS));
1036 }
1037
1038 static int tegra_spi_transfer_one_message(struct spi_master *master,
1039                         struct spi_message *msg)
1040 {
1041         bool is_first_msg = true;
1042         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1043         struct spi_transfer *xfer;
1044         struct spi_device *spi = msg->spi;
1045         int ret;
1046         bool skip = false;
1047         int single_xfer;
1048
1049         msg->status = 0;
1050         msg->actual_length = 0;
1051
1052         single_xfer = list_is_singular(&msg->transfers);
1053         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1054                 u32 cmd1;
1055
1056                 reinit_completion(&tspi->xfer_completion);
1057
1058                 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
1059                                                     single_xfer);
1060
1061                 if (!xfer->len) {
1062                         ret = 0;
1063                         skip = true;
1064                         goto complete_xfer;
1065                 }
1066
1067                 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
1068                 if (ret < 0) {
1069                         dev_err(tspi->dev,
1070                                 "spi can not start transfer, err %d\n", ret);
1071                         goto complete_xfer;
1072                 }
1073
1074                 is_first_msg = false;
1075                 ret = wait_for_completion_timeout(&tspi->xfer_completion,
1076                                                 SPI_DMA_TIMEOUT);
1077                 if (WARN_ON(ret == 0)) {
1078                         dev_err(tspi->dev,
1079                                 "spi transfer timeout, err %d\n", ret);
1080                         if (tspi->is_curr_dma_xfer &&
1081                             (tspi->cur_direction & DATA_DIR_TX))
1082                                 dmaengine_terminate_all(tspi->tx_dma_chan);
1083                         if (tspi->is_curr_dma_xfer &&
1084                             (tspi->cur_direction & DATA_DIR_RX))
1085                                 dmaengine_terminate_all(tspi->rx_dma_chan);
1086                         ret = -EIO;
1087                         tegra_spi_dump_regs(tspi);
1088                         tegra_spi_flush_fifos(tspi);
1089                         reset_control_assert(tspi->rst);
1090                         udelay(2);
1091                         reset_control_deassert(tspi->rst);
1092                         tspi->last_used_cs = master->num_chipselect + 1;
1093                         goto complete_xfer;
1094                 }
1095
1096                 if (tspi->tx_status ||  tspi->rx_status) {
1097                         dev_err(tspi->dev, "Error in Transfer\n");
1098                         ret = -EIO;
1099                         tegra_spi_dump_regs(tspi);
1100                         goto complete_xfer;
1101                 }
1102                 msg->actual_length += xfer->len;
1103
1104 complete_xfer:
1105                 if (ret < 0 || skip) {
1106                         tegra_spi_transfer_end(spi);
1107                         spi_transfer_delay_exec(xfer);
1108                         goto exit;
1109                 } else if (list_is_last(&xfer->transfer_list,
1110                                         &msg->transfers)) {
1111                         if (xfer->cs_change)
1112                                 tspi->cs_control = spi;
1113                         else {
1114                                 tegra_spi_transfer_end(spi);
1115                                 spi_transfer_delay_exec(xfer);
1116                         }
1117                 } else if (xfer->cs_change) {
1118                         tegra_spi_transfer_end(spi);
1119                         spi_transfer_delay_exec(xfer);
1120                 }
1121
1122         }
1123         ret = 0;
1124 exit:
1125         msg->status = ret;
1126         spi_finalize_current_message(master);
1127         return ret;
1128 }
1129
1130 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
1131 {
1132         struct spi_transfer *t = tspi->curr_xfer;
1133         unsigned long flags;
1134
1135         spin_lock_irqsave(&tspi->lock, flags);
1136         if (tspi->tx_status ||  tspi->rx_status) {
1137                 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
1138                         tspi->status_reg);
1139                 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
1140                         tspi->command1_reg, tspi->dma_control_reg);
1141                 tegra_spi_dump_regs(tspi);
1142                 tegra_spi_flush_fifos(tspi);
1143                 complete(&tspi->xfer_completion);
1144                 spin_unlock_irqrestore(&tspi->lock, flags);
1145                 reset_control_assert(tspi->rst);
1146                 udelay(2);
1147                 reset_control_deassert(tspi->rst);
1148                 return IRQ_HANDLED;
1149         }
1150
1151         if (tspi->cur_direction & DATA_DIR_RX)
1152                 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
1153
1154         if (tspi->cur_direction & DATA_DIR_TX)
1155                 tspi->cur_pos = tspi->cur_tx_pos;
1156         else
1157                 tspi->cur_pos = tspi->cur_rx_pos;
1158
1159         if (tspi->cur_pos == t->len) {
1160                 complete(&tspi->xfer_completion);
1161                 goto exit;
1162         }
1163
1164         tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
1165         tegra_spi_start_cpu_based_transfer(tspi, t);
1166 exit:
1167         spin_unlock_irqrestore(&tspi->lock, flags);
1168         return IRQ_HANDLED;
1169 }
1170
1171 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
1172 {
1173         struct spi_transfer *t = tspi->curr_xfer;
1174         long wait_status;
1175         int err = 0;
1176         unsigned total_fifo_words;
1177         unsigned long flags;
1178
1179         /* Abort dmas if any error */
1180         if (tspi->cur_direction & DATA_DIR_TX) {
1181                 if (tspi->tx_status) {
1182                         dmaengine_terminate_all(tspi->tx_dma_chan);
1183                         err += 1;
1184                 } else {
1185                         wait_status = wait_for_completion_interruptible_timeout(
1186                                 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
1187                         if (wait_status <= 0) {
1188                                 dmaengine_terminate_all(tspi->tx_dma_chan);
1189                                 dev_err(tspi->dev, "TxDma Xfer failed\n");
1190                                 err += 1;
1191                         }
1192                 }
1193         }
1194
1195         if (tspi->cur_direction & DATA_DIR_RX) {
1196                 if (tspi->rx_status) {
1197                         dmaengine_terminate_all(tspi->rx_dma_chan);
1198                         err += 2;
1199                 } else {
1200                         wait_status = wait_for_completion_interruptible_timeout(
1201                                 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1202                         if (wait_status <= 0) {
1203                                 dmaengine_terminate_all(tspi->rx_dma_chan);
1204                                 dev_err(tspi->dev, "RxDma Xfer failed\n");
1205                                 err += 2;
1206                         }
1207                 }
1208         }
1209
1210         spin_lock_irqsave(&tspi->lock, flags);
1211         if (err) {
1212                 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1213                         tspi->status_reg);
1214                 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1215                         tspi->command1_reg, tspi->dma_control_reg);
1216                 tegra_spi_dump_regs(tspi);
1217                 tegra_spi_flush_fifos(tspi);
1218                 complete(&tspi->xfer_completion);
1219                 spin_unlock_irqrestore(&tspi->lock, flags);
1220                 reset_control_assert(tspi->rst);
1221                 udelay(2);
1222                 reset_control_deassert(tspi->rst);
1223                 return IRQ_HANDLED;
1224         }
1225
1226         if (tspi->cur_direction & DATA_DIR_RX)
1227                 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1228
1229         if (tspi->cur_direction & DATA_DIR_TX)
1230                 tspi->cur_pos = tspi->cur_tx_pos;
1231         else
1232                 tspi->cur_pos = tspi->cur_rx_pos;
1233
1234         if (tspi->cur_pos == t->len) {
1235                 complete(&tspi->xfer_completion);
1236                 goto exit;
1237         }
1238
1239         /* Continue transfer in current message */
1240         total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1241                                                         tspi, t);
1242         if (total_fifo_words > SPI_FIFO_DEPTH)
1243                 err = tegra_spi_start_dma_based_transfer(tspi, t);
1244         else
1245                 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1246
1247 exit:
1248         spin_unlock_irqrestore(&tspi->lock, flags);
1249         return IRQ_HANDLED;
1250 }
1251
1252 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1253 {
1254         struct tegra_spi_data *tspi = context_data;
1255
1256         if (!tspi->is_curr_dma_xfer)
1257                 return handle_cpu_based_xfer(tspi);
1258         return handle_dma_based_xfer(tspi);
1259 }
1260
1261 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1262 {
1263         struct tegra_spi_data *tspi = context_data;
1264
1265         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1266         if (tspi->cur_direction & DATA_DIR_TX)
1267                 tspi->tx_status = tspi->status_reg &
1268                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1269
1270         if (tspi->cur_direction & DATA_DIR_RX)
1271                 tspi->rx_status = tspi->status_reg &
1272                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1273         tegra_spi_clear_status(tspi);
1274
1275         return IRQ_WAKE_THREAD;
1276 }
1277
1278 static struct tegra_spi_soc_data tegra114_spi_soc_data = {
1279         .has_intr_mask_reg = false,
1280 };
1281
1282 static struct tegra_spi_soc_data tegra124_spi_soc_data = {
1283         .has_intr_mask_reg = false,
1284 };
1285
1286 static struct tegra_spi_soc_data tegra210_spi_soc_data = {
1287         .has_intr_mask_reg = true,
1288 };
1289
1290 static const struct of_device_id tegra_spi_of_match[] = {
1291         {
1292                 .compatible = "nvidia,tegra114-spi",
1293                 .data       = &tegra114_spi_soc_data,
1294         }, {
1295                 .compatible = "nvidia,tegra124-spi",
1296                 .data       = &tegra124_spi_soc_data,
1297         }, {
1298                 .compatible = "nvidia,tegra210-spi",
1299                 .data       = &tegra210_spi_soc_data,
1300         },
1301         {}
1302 };
1303 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1304
1305 static int tegra_spi_probe(struct platform_device *pdev)
1306 {
1307         struct spi_master       *master;
1308         struct tegra_spi_data   *tspi;
1309         struct resource         *r;
1310         int ret, spi_irq;
1311         int bus_num;
1312
1313         master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1314         if (!master) {
1315                 dev_err(&pdev->dev, "master allocation failed\n");
1316                 return -ENOMEM;
1317         }
1318         platform_set_drvdata(pdev, master);
1319         tspi = spi_master_get_devdata(master);
1320
1321         if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1322                                  &master->max_speed_hz))
1323                 master->max_speed_hz = 25000000; /* 25MHz */
1324
1325         /* the spi->mode bits understood by this driver: */
1326         master->use_gpio_descriptors = true;
1327         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
1328                             SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
1329         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1330         master->setup = tegra_spi_setup;
1331         master->cleanup = tegra_spi_cleanup;
1332         master->transfer_one_message = tegra_spi_transfer_one_message;
1333         master->set_cs_timing = tegra_spi_set_hw_cs_timing;
1334         master->num_chipselect = MAX_CHIP_SELECT;
1335         master->auto_runtime_pm = true;
1336         bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1337         if (bus_num >= 0)
1338                 master->bus_num = bus_num;
1339
1340         tspi->master = master;
1341         tspi->dev = &pdev->dev;
1342         spin_lock_init(&tspi->lock);
1343
1344         tspi->soc_data = of_device_get_match_data(&pdev->dev);
1345         if (!tspi->soc_data) {
1346                 dev_err(&pdev->dev, "unsupported tegra\n");
1347                 ret = -ENODEV;
1348                 goto exit_free_master;
1349         }
1350
1351         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352         tspi->base = devm_ioremap_resource(&pdev->dev, r);
1353         if (IS_ERR(tspi->base)) {
1354                 ret = PTR_ERR(tspi->base);
1355                 goto exit_free_master;
1356         }
1357         tspi->phys = r->start;
1358
1359         spi_irq = platform_get_irq(pdev, 0);
1360         tspi->irq = spi_irq;
1361
1362         tspi->clk = devm_clk_get(&pdev->dev, "spi");
1363         if (IS_ERR(tspi->clk)) {
1364                 dev_err(&pdev->dev, "can not get clock\n");
1365                 ret = PTR_ERR(tspi->clk);
1366                 goto exit_free_master;
1367         }
1368
1369         tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1370         if (IS_ERR(tspi->rst)) {
1371                 dev_err(&pdev->dev, "can not get reset\n");
1372                 ret = PTR_ERR(tspi->rst);
1373                 goto exit_free_master;
1374         }
1375
1376         tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1377         tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1378
1379         ret = tegra_spi_init_dma_param(tspi, true);
1380         if (ret < 0)
1381                 goto exit_free_master;
1382         ret = tegra_spi_init_dma_param(tspi, false);
1383         if (ret < 0)
1384                 goto exit_rx_dma_free;
1385         tspi->max_buf_size = tspi->dma_buf_size;
1386         init_completion(&tspi->tx_dma_complete);
1387         init_completion(&tspi->rx_dma_complete);
1388
1389         init_completion(&tspi->xfer_completion);
1390
1391         pm_runtime_enable(&pdev->dev);
1392         if (!pm_runtime_enabled(&pdev->dev)) {
1393                 ret = tegra_spi_runtime_resume(&pdev->dev);
1394                 if (ret)
1395                         goto exit_pm_disable;
1396         }
1397
1398         ret = pm_runtime_get_sync(&pdev->dev);
1399         if (ret < 0) {
1400                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1401                 pm_runtime_put_noidle(&pdev->dev);
1402                 goto exit_pm_disable;
1403         }
1404
1405         reset_control_assert(tspi->rst);
1406         udelay(2);
1407         reset_control_deassert(tspi->rst);
1408         tspi->def_command1_reg  = SPI_M_S;
1409         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1410         tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
1411         tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
1412         tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
1413         tspi->last_used_cs = master->num_chipselect + 1;
1414         pm_runtime_put(&pdev->dev);
1415         ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1416                                    tegra_spi_isr_thread, IRQF_ONESHOT,
1417                                    dev_name(&pdev->dev), tspi);
1418         if (ret < 0) {
1419                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1420                         tspi->irq);
1421                 goto exit_pm_disable;
1422         }
1423
1424         master->dev.of_node = pdev->dev.of_node;
1425         ret = devm_spi_register_master(&pdev->dev, master);
1426         if (ret < 0) {
1427                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1428                 goto exit_free_irq;
1429         }
1430         return ret;
1431
1432 exit_free_irq:
1433         free_irq(spi_irq, tspi);
1434 exit_pm_disable:
1435         pm_runtime_disable(&pdev->dev);
1436         if (!pm_runtime_status_suspended(&pdev->dev))
1437                 tegra_spi_runtime_suspend(&pdev->dev);
1438         tegra_spi_deinit_dma_param(tspi, false);
1439 exit_rx_dma_free:
1440         tegra_spi_deinit_dma_param(tspi, true);
1441 exit_free_master:
1442         spi_master_put(master);
1443         return ret;
1444 }
1445
1446 static int tegra_spi_remove(struct platform_device *pdev)
1447 {
1448         struct spi_master *master = platform_get_drvdata(pdev);
1449         struct tegra_spi_data   *tspi = spi_master_get_devdata(master);
1450
1451         free_irq(tspi->irq, tspi);
1452
1453         if (tspi->tx_dma_chan)
1454                 tegra_spi_deinit_dma_param(tspi, false);
1455
1456         if (tspi->rx_dma_chan)
1457                 tegra_spi_deinit_dma_param(tspi, true);
1458
1459         pm_runtime_disable(&pdev->dev);
1460         if (!pm_runtime_status_suspended(&pdev->dev))
1461                 tegra_spi_runtime_suspend(&pdev->dev);
1462
1463         return 0;
1464 }
1465
1466 #ifdef CONFIG_PM_SLEEP
1467 static int tegra_spi_suspend(struct device *dev)
1468 {
1469         struct spi_master *master = dev_get_drvdata(dev);
1470
1471         return spi_master_suspend(master);
1472 }
1473
1474 static int tegra_spi_resume(struct device *dev)
1475 {
1476         struct spi_master *master = dev_get_drvdata(dev);
1477         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1478         int ret;
1479
1480         ret = pm_runtime_get_sync(dev);
1481         if (ret < 0) {
1482                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1483                 return ret;
1484         }
1485         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1486         tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
1487         tspi->last_used_cs = master->num_chipselect + 1;
1488         pm_runtime_put(dev);
1489
1490         return spi_master_resume(master);
1491 }
1492 #endif
1493
1494 static int tegra_spi_runtime_suspend(struct device *dev)
1495 {
1496         struct spi_master *master = dev_get_drvdata(dev);
1497         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1498
1499         /* Flush all write which are in PPSB queue by reading back */
1500         tegra_spi_readl(tspi, SPI_COMMAND1);
1501
1502         clk_disable_unprepare(tspi->clk);
1503         return 0;
1504 }
1505
1506 static int tegra_spi_runtime_resume(struct device *dev)
1507 {
1508         struct spi_master *master = dev_get_drvdata(dev);
1509         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1510         int ret;
1511
1512         ret = clk_prepare_enable(tspi->clk);
1513         if (ret < 0) {
1514                 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1515                 return ret;
1516         }
1517         return 0;
1518 }
1519
1520 static const struct dev_pm_ops tegra_spi_pm_ops = {
1521         SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1522                 tegra_spi_runtime_resume, NULL)
1523         SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1524 };
1525 static struct platform_driver tegra_spi_driver = {
1526         .driver = {
1527                 .name           = "spi-tegra114",
1528                 .pm             = &tegra_spi_pm_ops,
1529                 .of_match_table = tegra_spi_of_match,
1530         },
1531         .probe =        tegra_spi_probe,
1532         .remove =       tegra_spi_remove,
1533 };
1534 module_platform_driver(tegra_spi_driver);
1535
1536 MODULE_ALIAS("platform:spi-tegra114");
1537 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1538 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1539 MODULE_LICENSE("GPL v2");