1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21 #include <linux/dmaengine.h>
23 #include <linux/spi/spi.h>
25 #define SUN6I_AUTOSUSPEND_TIMEOUT 2000
27 #define SUN6I_FIFO_DEPTH 128
28 #define SUN8I_FIFO_DEPTH 64
30 #define SUN6I_GBL_CTL_REG 0x04
31 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
32 #define SUN6I_GBL_CTL_MASTER BIT(1)
33 #define SUN6I_GBL_CTL_TP BIT(7)
34 #define SUN6I_GBL_CTL_RST BIT(31)
36 #define SUN6I_TFR_CTL_REG 0x08
37 #define SUN6I_TFR_CTL_CPHA BIT(0)
38 #define SUN6I_TFR_CTL_CPOL BIT(1)
39 #define SUN6I_TFR_CTL_SPOL BIT(2)
40 #define SUN6I_TFR_CTL_CS_MASK 0x30
41 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
42 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
43 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
44 #define SUN6I_TFR_CTL_DHB BIT(8)
45 #define SUN6I_TFR_CTL_FBS BIT(12)
46 #define SUN6I_TFR_CTL_XCH BIT(31)
48 #define SUN6I_INT_CTL_REG 0x10
49 #define SUN6I_INT_CTL_RF_RDY BIT(0)
50 #define SUN6I_INT_CTL_TF_ERQ BIT(4)
51 #define SUN6I_INT_CTL_RF_OVF BIT(8)
52 #define SUN6I_INT_CTL_TC BIT(12)
54 #define SUN6I_INT_STA_REG 0x14
56 #define SUN6I_FIFO_CTL_REG 0x18
57 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
58 #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8)
59 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
60 #define SUN6I_FIFO_CTL_RF_RST BIT(15)
61 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
62 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
63 #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24)
64 #define SUN6I_FIFO_CTL_TF_RST BIT(31)
66 #define SUN6I_FIFO_STA_REG 0x1c
67 #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
68 #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
70 #define SUN6I_CLK_CTL_REG 0x24
71 #define SUN6I_CLK_CTL_CDR2_MASK 0xff
72 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
73 #define SUN6I_CLK_CTL_CDR1_MASK 0xf
74 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
75 #define SUN6I_CLK_CTL_DRS BIT(12)
77 #define SUN6I_MAX_XFER_SIZE 0xffffff
79 #define SUN6I_BURST_CNT_REG 0x30
81 #define SUN6I_XMIT_CNT_REG 0x34
83 #define SUN6I_BURST_CTL_CNT_REG 0x38
85 #define SUN6I_TXDATA_REG 0x200
86 #define SUN6I_RXDATA_REG 0x300
89 struct spi_master *master;
90 void __iomem *base_addr;
91 dma_addr_t dma_addr_rx;
92 dma_addr_t dma_addr_tx;
95 struct reset_control *rstc;
97 struct completion done;
102 unsigned long fifo_depth;
105 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
107 return readl(sspi->base_addr + reg);
110 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
112 writel(value, sspi->base_addr + reg);
115 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
117 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
119 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
122 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
124 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
126 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
129 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
131 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
134 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
137 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
142 /* See how much data is available */
143 len = sun6i_spi_get_rx_fifo_count(sspi);
146 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
148 *sspi->rx_buf++ = byte;
152 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
158 /* See how much data we can fit */
159 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
161 len = min((int)cnt, sspi->len);
164 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
165 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
170 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
172 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
175 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
176 reg &= ~SUN6I_TFR_CTL_CS_MASK;
177 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
180 reg |= SUN6I_TFR_CTL_CS_LEVEL;
182 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
184 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
187 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
189 return SUN6I_MAX_XFER_SIZE - 1;
192 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
193 struct spi_transfer *tfr)
195 struct dma_async_tx_descriptor *rxdesc, *txdesc;
196 struct spi_master *master = sspi->master;
200 struct dma_slave_config rxconf = {
201 .direction = DMA_DEV_TO_MEM,
202 .src_addr = sspi->dma_addr_rx,
203 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
207 dmaengine_slave_config(master->dma_rx, &rxconf);
209 rxdesc = dmaengine_prep_slave_sg(master->dma_rx,
220 struct dma_slave_config txconf = {
221 .direction = DMA_MEM_TO_DEV,
222 .dst_addr = sspi->dma_addr_tx,
223 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
227 dmaengine_slave_config(master->dma_tx, &txconf);
229 txdesc = dmaengine_prep_slave_sg(master->dma_tx,
236 dmaengine_terminate_sync(master->dma_rx);
242 dmaengine_submit(rxdesc);
243 dma_async_issue_pending(master->dma_rx);
247 dmaengine_submit(txdesc);
248 dma_async_issue_pending(master->dma_tx);
254 static int sun6i_spi_transfer_one(struct spi_master *master,
255 struct spi_device *spi,
256 struct spi_transfer *tfr)
258 struct sun6i_spi *sspi = spi_master_get_devdata(master);
259 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
260 unsigned int start, end, tx_time;
261 unsigned int trig_level;
262 unsigned int tx_len = 0, rx_len = 0;
267 if (tfr->len > SUN6I_MAX_XFER_SIZE)
270 reinit_completion(&sspi->done);
271 sspi->tx_buf = tfr->tx_buf;
272 sspi->rx_buf = tfr->rx_buf;
273 sspi->len = tfr->len;
274 use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false;
276 /* Clear pending interrupts */
277 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
280 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
281 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
287 * Setup FIFO interrupt trigger level
288 * Here we choose 3/4 of the full fifo depth, as it's
289 * the hardcoded value used in old generation of Allwinner
290 * SPI controller. (See spi-sun4i.c)
292 trig_level = sspi->fifo_depth / 4 * 3;
295 * Setup FIFO DMA request trigger level
296 * We choose 1/2 of the full fifo depth, that value will
297 * be used as DMA burst length.
299 trig_level = sspi->fifo_depth / 2;
302 reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
304 reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
307 reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
308 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
310 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
313 * Setup the transfer control register: Chip Select,
316 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
318 if (spi->mode & SPI_CPOL)
319 reg |= SUN6I_TFR_CTL_CPOL;
321 reg &= ~SUN6I_TFR_CTL_CPOL;
323 if (spi->mode & SPI_CPHA)
324 reg |= SUN6I_TFR_CTL_CPHA;
326 reg &= ~SUN6I_TFR_CTL_CPHA;
328 if (spi->mode & SPI_LSB_FIRST)
329 reg |= SUN6I_TFR_CTL_FBS;
331 reg &= ~SUN6I_TFR_CTL_FBS;
334 * If it's a TX only transfer, we don't want to fill the RX
335 * FIFO with bogus data
338 reg &= ~SUN6I_TFR_CTL_DHB;
341 reg |= SUN6I_TFR_CTL_DHB;
344 /* We want to control the chip select manually */
345 reg |= SUN6I_TFR_CTL_CS_MANUAL;
347 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
349 /* Ensure that we have a parent clock fast enough */
350 mclk_rate = clk_get_rate(sspi->mclk);
351 if (mclk_rate < (2 * tfr->speed_hz)) {
352 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
353 mclk_rate = clk_get_rate(sspi->mclk);
357 * Setup clock divider.
359 * We have two choices there. Either we can use the clock
360 * divide rate 1, which is calculated thanks to this formula:
361 * SPI_CLK = MOD_CLK / (2 ^ cdr)
362 * Or we can use CDR2, which is calculated with the formula:
363 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
364 * Wether we use the former or the latter is set through the
367 * First try CDR2, and if we can't reach the expected
368 * frequency, fall back to CDR1.
370 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
371 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
372 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
373 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
374 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
376 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
377 reg = SUN6I_CLK_CTL_CDR1(div);
378 tfr->effective_speed_hz = mclk_rate / (1 << div);
381 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
382 /* Finally enable the bus - doing so before might raise SCK to HIGH */
383 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
384 reg |= SUN6I_GBL_CTL_BUS_ENABLE;
385 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
387 /* Setup the transfer now... */
391 /* Setup the counters */
392 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
393 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
394 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
397 /* Fill the TX FIFO */
398 sun6i_spi_fill_fifo(sspi);
400 ret = sun6i_spi_prepare_dma(sspi, tfr);
402 dev_warn(&master->dev,
403 "%s: prepare DMA failed, ret=%d",
404 dev_name(&spi->dev), ret);
409 /* Enable the interrupts */
410 reg = SUN6I_INT_CTL_TC;
413 if (rx_len > sspi->fifo_depth)
414 reg |= SUN6I_INT_CTL_RF_RDY;
415 if (tx_len > sspi->fifo_depth)
416 reg |= SUN6I_INT_CTL_TF_ERQ;
419 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
421 /* Start the transfer */
422 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
423 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
425 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
427 timeout = wait_for_completion_timeout(&sspi->done,
428 msecs_to_jiffies(tx_time));
431 dev_warn(&master->dev,
432 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
433 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
434 jiffies_to_msecs(end - start), tx_time);
438 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
440 if (ret && use_dma) {
441 dmaengine_terminate_sync(master->dma_rx);
442 dmaengine_terminate_sync(master->dma_tx);
448 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
450 struct sun6i_spi *sspi = dev_id;
451 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
453 /* Transfer complete */
454 if (status & SUN6I_INT_CTL_TC) {
455 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
456 sun6i_spi_drain_fifo(sspi);
457 complete(&sspi->done);
461 /* Receive FIFO 3/4 full */
462 if (status & SUN6I_INT_CTL_RF_RDY) {
463 sun6i_spi_drain_fifo(sspi);
464 /* Only clear the interrupt _after_ draining the FIFO */
465 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
469 /* Transmit FIFO 3/4 empty */
470 if (status & SUN6I_INT_CTL_TF_ERQ) {
471 sun6i_spi_fill_fifo(sspi);
474 /* nothing left to transmit */
475 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
477 /* Only clear the interrupt _after_ re-seeding the FIFO */
478 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
486 static int sun6i_spi_runtime_resume(struct device *dev)
488 struct spi_master *master = dev_get_drvdata(dev);
489 struct sun6i_spi *sspi = spi_master_get_devdata(master);
492 ret = clk_prepare_enable(sspi->hclk);
494 dev_err(dev, "Couldn't enable AHB clock\n");
498 ret = clk_prepare_enable(sspi->mclk);
500 dev_err(dev, "Couldn't enable module clock\n");
504 ret = reset_control_deassert(sspi->rstc);
506 dev_err(dev, "Couldn't deassert the device from reset\n");
510 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
511 SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
516 clk_disable_unprepare(sspi->mclk);
518 clk_disable_unprepare(sspi->hclk);
523 static int sun6i_spi_runtime_suspend(struct device *dev)
525 struct spi_master *master = dev_get_drvdata(dev);
526 struct sun6i_spi *sspi = spi_master_get_devdata(master);
528 reset_control_assert(sspi->rstc);
529 clk_disable_unprepare(sspi->mclk);
530 clk_disable_unprepare(sspi->hclk);
535 static bool sun6i_spi_can_dma(struct spi_master *master,
536 struct spi_device *spi,
537 struct spi_transfer *xfer)
539 struct sun6i_spi *sspi = spi_master_get_devdata(master);
542 * If the number of spi words to transfer is less or equal than
543 * the fifo length we can just fill the fifo and wait for a single
544 * irq, so don't bother setting up dma
546 return xfer->len > sspi->fifo_depth;
549 static int sun6i_spi_probe(struct platform_device *pdev)
551 struct spi_master *master;
552 struct sun6i_spi *sspi;
553 struct resource *mem;
556 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
558 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
562 platform_set_drvdata(pdev, master);
563 sspi = spi_master_get_devdata(master);
565 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
566 if (IS_ERR(sspi->base_addr)) {
567 ret = PTR_ERR(sspi->base_addr);
568 goto err_free_master;
571 irq = platform_get_irq(pdev, 0);
574 goto err_free_master;
577 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
578 0, "sun6i-spi", sspi);
580 dev_err(&pdev->dev, "Cannot request IRQ\n");
581 goto err_free_master;
584 sspi->master = master;
585 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
587 master->max_speed_hz = 100 * 1000 * 1000;
588 master->min_speed_hz = 3 * 1000;
589 master->use_gpio_descriptors = true;
590 master->set_cs = sun6i_spi_set_cs;
591 master->transfer_one = sun6i_spi_transfer_one;
592 master->num_chipselect = 4;
593 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
594 master->bits_per_word_mask = SPI_BPW_MASK(8);
595 master->dev.of_node = pdev->dev.of_node;
596 master->auto_runtime_pm = true;
597 master->max_transfer_size = sun6i_spi_max_transfer_size;
599 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
600 if (IS_ERR(sspi->hclk)) {
601 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
602 ret = PTR_ERR(sspi->hclk);
603 goto err_free_master;
606 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
607 if (IS_ERR(sspi->mclk)) {
608 dev_err(&pdev->dev, "Unable to acquire module clock\n");
609 ret = PTR_ERR(sspi->mclk);
610 goto err_free_master;
613 init_completion(&sspi->done);
615 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
616 if (IS_ERR(sspi->rstc)) {
617 dev_err(&pdev->dev, "Couldn't get reset controller\n");
618 ret = PTR_ERR(sspi->rstc);
619 goto err_free_master;
622 master->dma_tx = dma_request_chan(&pdev->dev, "tx");
623 if (IS_ERR(master->dma_tx)) {
624 /* Check tx to see if we need defer probing driver */
625 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
627 goto err_free_master;
629 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
630 master->dma_tx = NULL;
633 master->dma_rx = dma_request_chan(&pdev->dev, "rx");
634 if (IS_ERR(master->dma_rx)) {
635 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
637 goto err_free_dma_tx;
639 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
640 master->dma_rx = NULL;
643 if (master->dma_tx && master->dma_rx) {
644 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
645 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
646 master->can_dma = sun6i_spi_can_dma;
650 * This wake-up/shutdown pattern is to be able to have the
651 * device woken up, even if runtime_pm is disabled
653 ret = sun6i_spi_runtime_resume(&pdev->dev);
655 dev_err(&pdev->dev, "Couldn't resume the device\n");
656 goto err_free_dma_rx;
659 pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
660 pm_runtime_use_autosuspend(&pdev->dev);
661 pm_runtime_set_active(&pdev->dev);
662 pm_runtime_enable(&pdev->dev);
664 ret = devm_spi_register_master(&pdev->dev, master);
666 dev_err(&pdev->dev, "cannot register SPI master\n");
673 pm_runtime_disable(&pdev->dev);
674 sun6i_spi_runtime_suspend(&pdev->dev);
677 dma_release_channel(master->dma_rx);
680 dma_release_channel(master->dma_tx);
682 spi_master_put(master);
686 static int sun6i_spi_remove(struct platform_device *pdev)
688 struct spi_master *master = platform_get_drvdata(pdev);
690 pm_runtime_force_suspend(&pdev->dev);
693 dma_release_channel(master->dma_tx);
695 dma_release_channel(master->dma_rx);
699 static const struct of_device_id sun6i_spi_match[] = {
700 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
701 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
704 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
706 static const struct dev_pm_ops sun6i_spi_pm_ops = {
707 .runtime_resume = sun6i_spi_runtime_resume,
708 .runtime_suspend = sun6i_spi_runtime_suspend,
711 static struct platform_driver sun6i_spi_driver = {
712 .probe = sun6i_spi_probe,
713 .remove = sun6i_spi_remove,
716 .of_match_table = sun6i_spi_match,
717 .pm = &sun6i_spi_pm_ops,
720 module_platform_driver(sun6i_spi_driver);
722 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
723 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
724 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
725 MODULE_LICENSE("GPL");