1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
8 #include <linux/bitfield.h>
9 #include <linux/debugfs.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/spi/spi.h>
22 #define DRIVER_NAME "spi_stm32"
24 /* STM32F4 SPI registers */
25 #define STM32F4_SPI_CR1 0x00
26 #define STM32F4_SPI_CR2 0x04
27 #define STM32F4_SPI_SR 0x08
28 #define STM32F4_SPI_DR 0x0C
29 #define STM32F4_SPI_I2SCFGR 0x1C
31 /* STM32F4_SPI_CR1 bit fields */
32 #define STM32F4_SPI_CR1_CPHA BIT(0)
33 #define STM32F4_SPI_CR1_CPOL BIT(1)
34 #define STM32F4_SPI_CR1_MSTR BIT(2)
35 #define STM32F4_SPI_CR1_BR_SHIFT 3
36 #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
37 #define STM32F4_SPI_CR1_SPE BIT(6)
38 #define STM32F4_SPI_CR1_LSBFRST BIT(7)
39 #define STM32F4_SPI_CR1_SSI BIT(8)
40 #define STM32F4_SPI_CR1_SSM BIT(9)
41 #define STM32F4_SPI_CR1_RXONLY BIT(10)
42 #define STM32F4_SPI_CR1_DFF BIT(11)
43 #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
44 #define STM32F4_SPI_CR1_CRCEN BIT(13)
45 #define STM32F4_SPI_CR1_BIDIOE BIT(14)
46 #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
47 #define STM32F4_SPI_CR1_BR_MIN 0
48 #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
50 /* STM32F4_SPI_CR2 bit fields */
51 #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
52 #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
53 #define STM32F4_SPI_CR2_SSOE BIT(2)
54 #define STM32F4_SPI_CR2_FRF BIT(4)
55 #define STM32F4_SPI_CR2_ERRIE BIT(5)
56 #define STM32F4_SPI_CR2_RXNEIE BIT(6)
57 #define STM32F4_SPI_CR2_TXEIE BIT(7)
59 /* STM32F4_SPI_SR bit fields */
60 #define STM32F4_SPI_SR_RXNE BIT(0)
61 #define STM32F4_SPI_SR_TXE BIT(1)
62 #define STM32F4_SPI_SR_CHSIDE BIT(2)
63 #define STM32F4_SPI_SR_UDR BIT(3)
64 #define STM32F4_SPI_SR_CRCERR BIT(4)
65 #define STM32F4_SPI_SR_MODF BIT(5)
66 #define STM32F4_SPI_SR_OVR BIT(6)
67 #define STM32F4_SPI_SR_BSY BIT(7)
68 #define STM32F4_SPI_SR_FRE BIT(8)
70 /* STM32F4_SPI_I2SCFGR bit fields */
71 #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
73 /* STM32F4 SPI Baud Rate min/max divisor */
74 #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
75 #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
77 /* STM32H7 SPI registers */
78 #define STM32H7_SPI_CR1 0x00
79 #define STM32H7_SPI_CR2 0x04
80 #define STM32H7_SPI_CFG1 0x08
81 #define STM32H7_SPI_CFG2 0x0C
82 #define STM32H7_SPI_IER 0x10
83 #define STM32H7_SPI_SR 0x14
84 #define STM32H7_SPI_IFCR 0x18
85 #define STM32H7_SPI_TXDR 0x20
86 #define STM32H7_SPI_RXDR 0x30
87 #define STM32H7_SPI_I2SCFGR 0x50
89 /* STM32H7_SPI_CR1 bit fields */
90 #define STM32H7_SPI_CR1_SPE BIT(0)
91 #define STM32H7_SPI_CR1_MASRX BIT(8)
92 #define STM32H7_SPI_CR1_CSTART BIT(9)
93 #define STM32H7_SPI_CR1_CSUSP BIT(10)
94 #define STM32H7_SPI_CR1_HDDIR BIT(11)
95 #define STM32H7_SPI_CR1_SSI BIT(12)
97 /* STM32H7_SPI_CR2 bit fields */
98 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
99 #define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
101 /* STM32H7_SPI_CFG1 bit fields */
102 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
104 #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
105 #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
106 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
107 #define STM32H7_SPI_CFG1_MBR_SHIFT 28
108 #define STM32H7_SPI_CFG1_MBR_MIN 0
109 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
111 /* STM32H7_SPI_CFG2 bit fields */
112 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
113 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
114 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
115 #define STM32H7_SPI_CFG2_MASTER BIT(22)
116 #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
117 #define STM32H7_SPI_CFG2_CPHA BIT(24)
118 #define STM32H7_SPI_CFG2_CPOL BIT(25)
119 #define STM32H7_SPI_CFG2_SSM BIT(26)
120 #define STM32H7_SPI_CFG2_SSIOP BIT(28)
121 #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
123 /* STM32H7_SPI_IER bit fields */
124 #define STM32H7_SPI_IER_RXPIE BIT(0)
125 #define STM32H7_SPI_IER_TXPIE BIT(1)
126 #define STM32H7_SPI_IER_DXPIE BIT(2)
127 #define STM32H7_SPI_IER_EOTIE BIT(3)
128 #define STM32H7_SPI_IER_TXTFIE BIT(4)
129 #define STM32H7_SPI_IER_OVRIE BIT(6)
130 #define STM32H7_SPI_IER_MODFIE BIT(9)
131 #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
133 /* STM32H7_SPI_SR bit fields */
134 #define STM32H7_SPI_SR_RXP BIT(0)
135 #define STM32H7_SPI_SR_TXP BIT(1)
136 #define STM32H7_SPI_SR_EOT BIT(3)
137 #define STM32H7_SPI_SR_OVR BIT(6)
138 #define STM32H7_SPI_SR_MODF BIT(9)
139 #define STM32H7_SPI_SR_SUSP BIT(11)
140 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
141 #define STM32H7_SPI_SR_RXWNE BIT(15)
143 /* STM32H7_SPI_IFCR bit fields */
144 #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
146 /* STM32H7_SPI_I2SCFGR bit fields */
147 #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
149 /* STM32H7 SPI Master Baud Rate min/max divisor */
150 #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
151 #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
153 /* STM32H7 SPI Communication mode */
154 #define STM32H7_SPI_FULL_DUPLEX 0
155 #define STM32H7_SPI_SIMPLEX_TX 1
156 #define STM32H7_SPI_SIMPLEX_RX 2
157 #define STM32H7_SPI_HALF_DUPLEX 3
159 /* SPI Communication type */
160 #define SPI_FULL_DUPLEX 0
161 #define SPI_SIMPLEX_TX 1
162 #define SPI_SIMPLEX_RX 2
163 #define SPI_3WIRE_TX 3
164 #define SPI_3WIRE_RX 4
166 #define STM32_SPI_AUTOSUSPEND_DELAY 1 /* 1 ms */
169 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
170 * without fifo buffers.
172 #define SPI_DMA_MIN_BYTES 16
174 /* STM32 SPI driver helpers */
175 #define STM32_SPI_MASTER_MODE(stm32_spi) (!(stm32_spi)->device_mode)
176 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
179 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
180 * @reg: register offset
181 * @mask: bitfield mask
184 struct stm32_spi_reg {
191 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
192 * @en: enable register and SPI enable bit
193 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
194 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
195 * @cpol: clock polarity register and polarity bit
196 * @cpha: clock phase register and phase bit
197 * @lsb_first: LSB transmitted first register and bit
198 * @cs_high: chips select active value
199 * @br: baud rate register and bitfields
200 * @rx: SPI RX data register
201 * @tx: SPI TX data register
203 struct stm32_spi_regspec {
204 const struct stm32_spi_reg en;
205 const struct stm32_spi_reg dma_rx_en;
206 const struct stm32_spi_reg dma_tx_en;
207 const struct stm32_spi_reg cpol;
208 const struct stm32_spi_reg cpha;
209 const struct stm32_spi_reg lsb_first;
210 const struct stm32_spi_reg cs_high;
211 const struct stm32_spi_reg br;
212 const struct stm32_spi_reg rx;
213 const struct stm32_spi_reg tx;
219 * struct stm32_spi_cfg - stm32 compatible configuration data
220 * @regs: registers descriptions
221 * @get_fifo_size: routine to get fifo size
222 * @get_bpw_mask: routine to get bits per word mask
223 * @disable: routine to disable controller
224 * @config: routine to configure controller as SPI Master
225 * @set_bpw: routine to configure registers to for bits per word
226 * @set_mode: routine to configure registers to desired mode
227 * @set_data_idleness: optional routine to configure registers to desired idle
228 * time between frames (if driver has this functionality)
229 * @set_number_of_data: optional routine to configure registers to desired
230 * number of data (if driver has this functionality)
231 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
233 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
234 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
235 * @transfer_one_irq: routine to configure interrupts for driver
236 * @irq_handler_event: Interrupt handler for SPI controller events
237 * @irq_handler_thread: thread of interrupt handler for SPI controller
238 * @baud_rate_div_min: minimum baud rate divisor
239 * @baud_rate_div_max: maximum baud rate divisor
240 * @has_fifo: boolean to know if fifo is used for driver
241 * @has_device_mode: is this compatible capable to switch on device mode
242 * @flags: compatible specific SPI controller flags used at registration time
244 struct stm32_spi_cfg {
245 const struct stm32_spi_regspec *regs;
246 int (*get_fifo_size)(struct stm32_spi *spi);
247 int (*get_bpw_mask)(struct stm32_spi *spi);
248 void (*disable)(struct stm32_spi *spi);
249 int (*config)(struct stm32_spi *spi);
250 void (*set_bpw)(struct stm32_spi *spi);
251 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
252 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
253 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
254 void (*transfer_one_dma_start)(struct stm32_spi *spi);
255 void (*dma_rx_cb)(void *data);
256 void (*dma_tx_cb)(void *data);
257 int (*transfer_one_irq)(struct stm32_spi *spi);
258 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
259 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
260 unsigned int baud_rate_div_min;
261 unsigned int baud_rate_div_max;
263 bool has_device_mode;
268 * struct stm32_spi - private data of the SPI controller
269 * @dev: driver model representation of the controller
270 * @ctrl: controller interface
271 * @cfg: compatible configuration data
272 * @base: virtual memory area
273 * @clk: hw kernel clock feeding the SPI clock generator
274 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
275 * @lock: prevent I/O concurrent access
276 * @irq: SPI controller interrupt line
277 * @fifo_size: size of the embedded fifo in bytes
278 * @cur_midi: master inter-data idleness in ns
279 * @cur_speed: speed configured in Hz
280 * @cur_bpw: number of bits in a single SPI data frame
281 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
282 * @cur_comm: SPI communication mode
283 * @cur_xferlen: current transfer length in bytes
284 * @cur_usedma: boolean to know if dma is used in current transfer
285 * @tx_buf: data to be written, or NULL
286 * @rx_buf: data to be read, or NULL
287 * @tx_len: number of data to be written in bytes
288 * @rx_len: number of data to be read in bytes
289 * @dma_tx: dma channel for TX transfer
290 * @dma_rx: dma channel for RX transfer
291 * @phys_addr: SPI registers physical base address
292 * @device_mode: the controller is configured as SPI device
296 struct spi_controller *ctrl;
297 const struct stm32_spi_cfg *cfg;
301 spinlock_t lock; /* prevent I/O concurrent access */
303 unsigned int fifo_size;
305 unsigned int cur_midi;
306 unsigned int cur_speed;
307 unsigned int cur_bpw;
308 unsigned int cur_fthlv;
309 unsigned int cur_comm;
310 unsigned int cur_xferlen;
317 struct dma_chan *dma_tx;
318 struct dma_chan *dma_rx;
319 dma_addr_t phys_addr;
324 static const struct stm32_spi_regspec stm32f4_spi_regspec = {
325 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
327 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
328 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
330 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
331 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
332 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
334 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
336 .rx = { STM32F4_SPI_DR },
337 .tx = { STM32F4_SPI_DR },
340 static const struct stm32_spi_regspec stm32h7_spi_regspec = {
341 /* SPI data transfer is enabled but spi_ker_ck is idle.
342 * CFG1 and CFG2 registers are write protected when SPE is enabled.
344 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
346 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
347 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
349 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
350 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
351 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
352 .cs_high = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_SSIOP },
353 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
354 STM32H7_SPI_CFG1_MBR_SHIFT },
356 .rx = { STM32H7_SPI_RXDR },
357 .tx = { STM32H7_SPI_TXDR },
360 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
361 u32 offset, u32 bits)
363 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
367 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
368 u32 offset, u32 bits)
370 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
375 * stm32h7_spi_get_fifo_size - Return fifo size
376 * @spi: pointer to the spi controller data structure
378 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
383 spin_lock_irqsave(&spi->lock, flags);
385 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
387 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
388 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
390 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
392 spin_unlock_irqrestore(&spi->lock, flags);
394 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
400 * stm32f4_spi_get_bpw_mask - Return bits per word mask
401 * @spi: pointer to the spi controller data structure
403 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
405 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
406 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
410 * stm32h7_spi_get_bpw_mask - Return bits per word mask
411 * @spi: pointer to the spi controller data structure
413 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
418 spin_lock_irqsave(&spi->lock, flags);
421 * The most significant bit at DSIZE bit field is reserved when the
422 * maximum data size of periperal instances is limited to 16-bit
424 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
426 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
427 max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
429 spin_unlock_irqrestore(&spi->lock, flags);
431 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
433 return SPI_BPW_RANGE_MASK(4, max_bpw);
437 * stm32_spi_prepare_mbr - Determine baud rate divisor value
438 * @spi: pointer to the spi controller data structure
439 * @speed_hz: requested speed
440 * @min_div: minimum baud rate divisor
441 * @max_div: maximum baud rate divisor
443 * Return baud rate divisor value in case of success or -EINVAL
445 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
446 u32 min_div, u32 max_div)
450 /* Ensure spi->clk_rate is even */
451 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
454 * SPI framework set xfer->speed_hz to ctrl->max_speed_hz if
455 * xfer->speed_hz is greater than ctrl->max_speed_hz, and it returns
456 * an error when xfer->speed_hz is lower than ctrl->min_speed_hz, so
457 * no need to check it there.
458 * However, we need to ensure the following calculations.
460 if ((div < min_div) || (div > max_div))
463 /* Determine the first power of 2 greater than or equal to div */
467 mbrdiv = fls(div) - 1;
469 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
475 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
476 * @spi: pointer to the spi controller data structure
477 * @xfer_len: length of the message to be transferred
479 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
483 /* data packet should not exceed 1/2 of fifo space */
484 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
486 /* align packet size with data registers access */
487 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
488 return DIV_ROUND_UP(packet, bpw);
492 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
493 * @spi: pointer to the spi controller data structure
495 * Read from tx_buf depends on remaining bytes to avoid to read beyond
498 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
500 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
501 STM32F4_SPI_SR_TXE)) {
502 u32 offs = spi->cur_xferlen - spi->tx_len;
504 if (spi->cur_bpw == 16) {
505 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
507 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
508 spi->tx_len -= sizeof(u16);
510 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
512 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
513 spi->tx_len -= sizeof(u8);
517 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
521 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
522 * @spi: pointer to the spi controller data structure
524 * Read from tx_buf depends on remaining bytes to avoid to read beyond
527 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
529 while ((spi->tx_len > 0) &&
530 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
531 STM32H7_SPI_SR_TXP)) {
532 u32 offs = spi->cur_xferlen - spi->tx_len;
534 if (spi->tx_len >= sizeof(u32)) {
535 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
537 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
538 spi->tx_len -= sizeof(u32);
539 } else if (spi->tx_len >= sizeof(u16)) {
540 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
542 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
543 spi->tx_len -= sizeof(u16);
545 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
547 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
548 spi->tx_len -= sizeof(u8);
552 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
556 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
557 * @spi: pointer to the spi controller data structure
559 * Write in rx_buf depends on remaining bytes to avoid to write beyond
562 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
564 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
565 STM32F4_SPI_SR_RXNE)) {
566 u32 offs = spi->cur_xferlen - spi->rx_len;
568 if (spi->cur_bpw == 16) {
569 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
571 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
572 spi->rx_len -= sizeof(u16);
574 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
576 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
577 spi->rx_len -= sizeof(u8);
581 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
585 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
586 * @spi: pointer to the spi controller data structure
588 * Write in rx_buf depends on remaining bytes to avoid to write beyond
591 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
593 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
594 u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
596 while ((spi->rx_len > 0) &&
597 ((sr & STM32H7_SPI_SR_RXP) ||
598 ((sr & STM32H7_SPI_SR_EOT) &&
599 ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
600 u32 offs = spi->cur_xferlen - spi->rx_len;
602 if ((spi->rx_len >= sizeof(u32)) ||
603 (sr & STM32H7_SPI_SR_RXWNE)) {
604 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
606 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
607 spi->rx_len -= sizeof(u32);
608 } else if ((spi->rx_len >= sizeof(u16)) ||
609 (!(sr & STM32H7_SPI_SR_RXWNE) &&
610 (rxplvl >= 2 || spi->cur_bpw > 8))) {
611 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
613 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
614 spi->rx_len -= sizeof(u16);
616 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
618 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
619 spi->rx_len -= sizeof(u8);
622 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
623 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
626 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
627 __func__, spi->rx_len, sr);
631 * stm32_spi_enable - Enable SPI controller
632 * @spi: pointer to the spi controller data structure
634 static void stm32_spi_enable(struct stm32_spi *spi)
636 dev_dbg(spi->dev, "enable controller\n");
638 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
639 spi->cfg->regs->en.mask);
643 * stm32f4_spi_disable - Disable SPI controller
644 * @spi: pointer to the spi controller data structure
646 static void stm32f4_spi_disable(struct stm32_spi *spi)
651 dev_dbg(spi->dev, "disable controller\n");
653 spin_lock_irqsave(&spi->lock, flags);
655 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
656 STM32F4_SPI_CR1_SPE)) {
657 spin_unlock_irqrestore(&spi->lock, flags);
661 /* Disable interrupts */
662 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
663 STM32F4_SPI_CR2_RXNEIE |
664 STM32F4_SPI_CR2_ERRIE);
666 /* Wait until BSY = 0 */
667 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
668 sr, !(sr & STM32F4_SPI_SR_BSY),
670 dev_warn(spi->dev, "disabling condition timeout\n");
673 if (spi->cur_usedma && spi->dma_tx)
674 dmaengine_terminate_async(spi->dma_tx);
675 if (spi->cur_usedma && spi->dma_rx)
676 dmaengine_terminate_async(spi->dma_rx);
678 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
680 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
681 STM32F4_SPI_CR2_RXDMAEN);
683 /* Sequence to clear OVR flag */
684 readl_relaxed(spi->base + STM32F4_SPI_DR);
685 readl_relaxed(spi->base + STM32F4_SPI_SR);
687 spin_unlock_irqrestore(&spi->lock, flags);
691 * stm32h7_spi_disable - Disable SPI controller
692 * @spi: pointer to the spi controller data structure
694 * RX-Fifo is flushed when SPI controller is disabled.
696 static void stm32h7_spi_disable(struct stm32_spi *spi)
701 dev_dbg(spi->dev, "disable controller\n");
703 spin_lock_irqsave(&spi->lock, flags);
705 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
707 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
708 spin_unlock_irqrestore(&spi->lock, flags);
712 if (spi->cur_usedma && spi->dma_tx)
713 dmaengine_terminate_async(spi->dma_tx);
714 if (spi->cur_usedma && spi->dma_rx)
715 dmaengine_terminate_async(spi->dma_rx);
717 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
719 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
720 STM32H7_SPI_CFG1_RXDMAEN);
722 /* Disable interrupts and clear status flags */
723 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
724 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
726 spin_unlock_irqrestore(&spi->lock, flags);
730 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
731 * @ctrl: controller interface
732 * @spi_dev: pointer to the spi device
733 * @transfer: pointer to spi transfer
735 * If driver has fifo and the current transfer size is greater than fifo size,
736 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
738 static bool stm32_spi_can_dma(struct spi_controller *ctrl,
739 struct spi_device *spi_dev,
740 struct spi_transfer *transfer)
742 unsigned int dma_size;
743 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
745 if (spi->cfg->has_fifo)
746 dma_size = spi->fifo_size;
748 dma_size = SPI_DMA_MIN_BYTES;
750 dev_dbg(spi->dev, "%s: %s\n", __func__,
751 (transfer->len > dma_size) ? "true" : "false");
753 return (transfer->len > dma_size);
757 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
758 * @irq: interrupt line
759 * @dev_id: SPI controller ctrl interface
761 static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
763 struct spi_controller *ctrl = dev_id;
764 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
768 spin_lock(&spi->lock);
770 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
772 * BSY flag is not handled in interrupt but it is normal behavior when
775 sr &= ~STM32F4_SPI_SR_BSY;
777 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
778 spi->cur_comm == SPI_3WIRE_TX)) {
779 /* OVR flag shouldn't be handled for TX only mode */
780 sr &= ~(STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE);
781 mask |= STM32F4_SPI_SR_TXE;
784 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
785 spi->cur_comm == SPI_SIMPLEX_RX ||
786 spi->cur_comm == SPI_3WIRE_RX)) {
787 /* TXE flag is set and is handled when RXNE flag occurs */
788 sr &= ~STM32F4_SPI_SR_TXE;
789 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
793 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
794 spin_unlock(&spi->lock);
798 if (sr & STM32F4_SPI_SR_OVR) {
799 dev_warn(spi->dev, "Overrun: received value discarded\n");
801 /* Sequence to clear OVR flag */
802 readl_relaxed(spi->base + STM32F4_SPI_DR);
803 readl_relaxed(spi->base + STM32F4_SPI_SR);
806 * If overrun is detected, it means that something went wrong,
807 * so stop the current transfer. Transfer can wait for next
808 * RXNE but DR is already read and end never happens.
814 if (sr & STM32F4_SPI_SR_TXE) {
816 stm32f4_spi_write_tx(spi);
817 if (spi->tx_len == 0)
821 if (sr & STM32F4_SPI_SR_RXNE) {
822 stm32f4_spi_read_rx(spi);
823 if (spi->rx_len == 0)
825 else if (spi->tx_buf)/* Load data for discontinuous mode */
826 stm32f4_spi_write_tx(spi);
831 /* Immediately disable interrupts to do not generate new one */
832 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
833 STM32F4_SPI_CR2_TXEIE |
834 STM32F4_SPI_CR2_RXNEIE |
835 STM32F4_SPI_CR2_ERRIE);
836 spin_unlock(&spi->lock);
837 return IRQ_WAKE_THREAD;
840 spin_unlock(&spi->lock);
845 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
846 * @irq: interrupt line
847 * @dev_id: SPI controller interface
849 static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
851 struct spi_controller *ctrl = dev_id;
852 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
854 spi_finalize_current_transfer(ctrl);
855 stm32f4_spi_disable(spi);
861 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
862 * @irq: interrupt line
863 * @dev_id: SPI controller interface
865 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
867 struct spi_controller *ctrl = dev_id;
868 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
873 spin_lock_irqsave(&spi->lock, flags);
875 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
876 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
880 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
881 * SUSP to acknowledge it later. TXC is automatically cleared
884 mask |= STM32H7_SPI_SR_SUSP;
886 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
887 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
889 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
890 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
893 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
895 spin_unlock_irqrestore(&spi->lock, flags);
899 if (sr & STM32H7_SPI_SR_SUSP) {
900 static DEFINE_RATELIMIT_STATE(rs,
901 DEFAULT_RATELIMIT_INTERVAL * 10,
903 ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
904 if (__ratelimit(&rs))
905 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
906 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
907 stm32h7_spi_read_rxfifo(spi);
909 * If communication is suspended while using DMA, it means
910 * that something went wrong, so stop the current transfer
916 if (sr & STM32H7_SPI_SR_MODF) {
917 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
921 if (sr & STM32H7_SPI_SR_OVR) {
922 dev_err(spi->dev, "Overrun: RX data lost\n");
926 if (sr & STM32H7_SPI_SR_EOT) {
927 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
928 stm32h7_spi_read_rxfifo(spi);
929 if (!spi->cur_usedma ||
930 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
934 if (sr & STM32H7_SPI_SR_TXP)
935 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
936 stm32h7_spi_write_txfifo(spi);
938 if (sr & STM32H7_SPI_SR_RXP)
939 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
940 stm32h7_spi_read_rxfifo(spi);
942 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
944 spin_unlock_irqrestore(&spi->lock, flags);
947 stm32h7_spi_disable(spi);
948 spi_finalize_current_transfer(ctrl);
955 * stm32_spi_prepare_msg - set up the controller to transfer a single message
956 * @ctrl: controller interface
957 * @msg: pointer to spi message
959 static int stm32_spi_prepare_msg(struct spi_controller *ctrl,
960 struct spi_message *msg)
962 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
963 struct spi_device *spi_dev = msg->spi;
964 struct device_node *np = spi_dev->dev.of_node;
966 u32 clrb = 0, setb = 0;
968 /* SPI slave device may need time between data frames */
970 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
971 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
973 if (spi_dev->mode & SPI_CPOL)
974 setb |= spi->cfg->regs->cpol.mask;
976 clrb |= spi->cfg->regs->cpol.mask;
978 if (spi_dev->mode & SPI_CPHA)
979 setb |= spi->cfg->regs->cpha.mask;
981 clrb |= spi->cfg->regs->cpha.mask;
983 if (spi_dev->mode & SPI_LSB_FIRST)
984 setb |= spi->cfg->regs->lsb_first.mask;
986 clrb |= spi->cfg->regs->lsb_first.mask;
988 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH)
989 setb |= spi->cfg->regs->cs_high.mask;
991 clrb |= spi->cfg->regs->cs_high.mask;
993 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
994 !!(spi_dev->mode & SPI_CPOL),
995 !!(spi_dev->mode & SPI_CPHA),
996 !!(spi_dev->mode & SPI_LSB_FIRST),
997 !!(spi_dev->mode & SPI_CS_HIGH));
999 /* On STM32H7, messages should not exceed a maximum size setted
1000 * afterward via the set_number_of_data function. In order to
1001 * ensure that, split large messages into several messages
1003 if (spi->cfg->set_number_of_data) {
1006 ret = spi_split_transfers_maxsize(ctrl, msg,
1007 STM32H7_SPI_TSIZE_MAX,
1008 GFP_KERNEL | GFP_DMA);
1013 spin_lock_irqsave(&spi->lock, flags);
1015 /* CPOL, CPHA and LSB FIRST bits have common register */
1018 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1020 spi->base + spi->cfg->regs->cpol.reg);
1022 spin_unlock_irqrestore(&spi->lock, flags);
1028 * stm32f4_spi_dma_tx_cb - dma callback
1029 * @data: pointer to the spi controller data structure
1031 * DMA callback is called when the transfer is complete for DMA TX channel.
1033 static void stm32f4_spi_dma_tx_cb(void *data)
1035 struct stm32_spi *spi = data;
1037 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1038 spi_finalize_current_transfer(spi->ctrl);
1039 stm32f4_spi_disable(spi);
1044 * stm32_spi_dma_rx_cb - dma callback
1045 * @data: pointer to the spi controller data structure
1047 * DMA callback is called when the transfer is complete for DMA RX channel.
1049 static void stm32_spi_dma_rx_cb(void *data)
1051 struct stm32_spi *spi = data;
1053 spi_finalize_current_transfer(spi->ctrl);
1054 spi->cfg->disable(spi);
1058 * stm32_spi_dma_config - configure dma slave channel depending on current
1059 * transfer bits_per_word.
1060 * @spi: pointer to the spi controller data structure
1061 * @dma_conf: pointer to the dma_slave_config structure
1062 * @dir: direction of the dma transfer
1064 static void stm32_spi_dma_config(struct stm32_spi *spi,
1065 struct dma_slave_config *dma_conf,
1066 enum dma_transfer_direction dir)
1068 enum dma_slave_buswidth buswidth;
1071 if (spi->cur_bpw <= 8)
1072 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1073 else if (spi->cur_bpw <= 16)
1074 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1076 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1078 if (spi->cfg->has_fifo) {
1079 /* Valid for DMA Half or Full Fifo threshold */
1080 if (spi->cur_fthlv == 2)
1083 maxburst = spi->cur_fthlv;
1088 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1089 dma_conf->direction = dir;
1090 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1091 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1092 dma_conf->src_addr_width = buswidth;
1093 dma_conf->src_maxburst = maxburst;
1095 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1096 buswidth, maxburst);
1097 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1098 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1099 dma_conf->dst_addr_width = buswidth;
1100 dma_conf->dst_maxburst = maxburst;
1102 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1103 buswidth, maxburst);
1108 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1110 * @spi: pointer to the spi controller data structure
1112 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1115 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1117 unsigned long flags;
1120 /* Enable the interrupts relative to the current communication mode */
1121 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1122 cr2 |= STM32F4_SPI_CR2_TXEIE;
1123 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1124 spi->cur_comm == SPI_SIMPLEX_RX ||
1125 spi->cur_comm == SPI_3WIRE_RX) {
1126 /* In transmit-only mode, the OVR flag is set in the SR register
1127 * since the received data are never read. Therefore set OVR
1128 * interrupt only when rx buffer is available.
1130 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1135 spin_lock_irqsave(&spi->lock, flags);
1137 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1139 stm32_spi_enable(spi);
1141 /* starting data transfer when buffer is loaded */
1143 stm32f4_spi_write_tx(spi);
1145 spin_unlock_irqrestore(&spi->lock, flags);
1151 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1153 * @spi: pointer to the spi controller data structure
1155 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1158 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1160 unsigned long flags;
1163 /* Enable the interrupts relative to the current communication mode */
1164 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1165 ier |= STM32H7_SPI_IER_DXPIE;
1166 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1167 ier |= STM32H7_SPI_IER_TXPIE;
1168 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1169 ier |= STM32H7_SPI_IER_RXPIE;
1171 /* Enable the interrupts relative to the end of transfer */
1172 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1173 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1175 spin_lock_irqsave(&spi->lock, flags);
1177 stm32_spi_enable(spi);
1179 /* Be sure to have data in fifo before starting data transfer */
1181 stm32h7_spi_write_txfifo(spi);
1183 if (STM32_SPI_MASTER_MODE(spi))
1184 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1186 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1188 spin_unlock_irqrestore(&spi->lock, flags);
1194 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1195 * transfer using DMA
1196 * @spi: pointer to the spi controller data structure
1198 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1200 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1201 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1202 spi->cur_comm == SPI_FULL_DUPLEX) {
1204 * In transmit-only mode, the OVR flag is set in the SR register
1205 * since the received data are never read. Therefore set OVR
1206 * interrupt only when rx buffer is available.
1208 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1211 stm32_spi_enable(spi);
1215 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1216 * transfer using DMA
1217 * @spi: pointer to the spi controller data structure
1219 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1221 uint32_t ier = STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1223 /* Enable the interrupts */
1224 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1225 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1227 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1229 stm32_spi_enable(spi);
1231 if (STM32_SPI_MASTER_MODE(spi))
1232 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1236 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1237 * @spi: pointer to the spi controller data structure
1238 * @xfer: pointer to the spi_transfer structure
1240 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1243 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1244 struct spi_transfer *xfer)
1246 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1247 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1248 unsigned long flags;
1250 spin_lock_irqsave(&spi->lock, flags);
1253 if (spi->rx_buf && spi->dma_rx) {
1254 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1255 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1257 /* Enable Rx DMA request */
1258 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1259 spi->cfg->regs->dma_rx_en.mask);
1261 rx_dma_desc = dmaengine_prep_slave_sg(
1262 spi->dma_rx, xfer->rx_sg.sgl,
1264 rx_dma_conf.direction,
1265 DMA_PREP_INTERRUPT);
1269 if (spi->tx_buf && spi->dma_tx) {
1270 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1271 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1273 tx_dma_desc = dmaengine_prep_slave_sg(
1274 spi->dma_tx, xfer->tx_sg.sgl,
1276 tx_dma_conf.direction,
1277 DMA_PREP_INTERRUPT);
1280 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1281 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1282 goto dma_desc_error;
1284 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1285 goto dma_desc_error;
1288 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1289 rx_dma_desc->callback_param = spi;
1291 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1292 dev_err(spi->dev, "Rx DMA submit failed\n");
1293 goto dma_desc_error;
1295 /* Enable Rx DMA channel */
1296 dma_async_issue_pending(spi->dma_rx);
1300 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1301 spi->cur_comm == SPI_3WIRE_TX) {
1302 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1303 tx_dma_desc->callback_param = spi;
1306 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1307 dev_err(spi->dev, "Tx DMA submit failed\n");
1308 goto dma_submit_error;
1310 /* Enable Tx DMA channel */
1311 dma_async_issue_pending(spi->dma_tx);
1313 /* Enable Tx DMA request */
1314 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1315 spi->cfg->regs->dma_tx_en.mask);
1318 spi->cfg->transfer_one_dma_start(spi);
1320 spin_unlock_irqrestore(&spi->lock, flags);
1326 dmaengine_terminate_sync(spi->dma_rx);
1329 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1330 spi->cfg->regs->dma_rx_en.mask);
1332 spin_unlock_irqrestore(&spi->lock, flags);
1334 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1336 spi->cur_usedma = false;
1337 return spi->cfg->transfer_one_irq(spi);
1341 * stm32f4_spi_set_bpw - Configure bits per word
1342 * @spi: pointer to the spi controller data structure
1344 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1346 if (spi->cur_bpw == 16)
1347 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1349 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1353 * stm32h7_spi_set_bpw - configure bits per word
1354 * @spi: pointer to the spi controller data structure
1356 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1359 u32 cfg1_clrb = 0, cfg1_setb = 0;
1361 bpw = spi->cur_bpw - 1;
1363 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1364 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1366 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1367 fthlv = spi->cur_fthlv - 1;
1369 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1370 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1373 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1374 ~cfg1_clrb) | cfg1_setb,
1375 spi->base + STM32H7_SPI_CFG1);
1379 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1380 * @spi: pointer to the spi controller data structure
1381 * @mbrdiv: baud rate divisor value
1383 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1385 u32 clrb = 0, setb = 0;
1387 clrb |= spi->cfg->regs->br.mask;
1388 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1390 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1392 spi->base + spi->cfg->regs->br.reg);
1396 * stm32_spi_communication_type - return transfer communication type
1397 * @spi_dev: pointer to the spi device
1398 * @transfer: pointer to spi transfer
1400 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1401 struct spi_transfer *transfer)
1403 unsigned int type = SPI_FULL_DUPLEX;
1405 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1407 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1408 * is forbidden and unvalidated by SPI subsystem so depending
1409 * on the valid buffer, we can determine the direction of the
1412 if (!transfer->tx_buf)
1413 type = SPI_3WIRE_RX;
1415 type = SPI_3WIRE_TX;
1417 if (!transfer->tx_buf)
1418 type = SPI_SIMPLEX_RX;
1419 else if (!transfer->rx_buf)
1420 type = SPI_SIMPLEX_TX;
1427 * stm32f4_spi_set_mode - configure communication mode
1428 * @spi: pointer to the spi controller data structure
1429 * @comm_type: type of communication to configure
1431 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1433 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1434 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1435 STM32F4_SPI_CR1_BIDIMODE |
1436 STM32F4_SPI_CR1_BIDIOE);
1437 } else if (comm_type == SPI_FULL_DUPLEX ||
1438 comm_type == SPI_SIMPLEX_RX) {
1439 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1440 STM32F4_SPI_CR1_BIDIMODE |
1441 STM32F4_SPI_CR1_BIDIOE);
1442 } else if (comm_type == SPI_3WIRE_RX) {
1443 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1444 STM32F4_SPI_CR1_BIDIMODE);
1445 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1446 STM32F4_SPI_CR1_BIDIOE);
1455 * stm32h7_spi_set_mode - configure communication mode
1456 * @spi: pointer to the spi controller data structure
1457 * @comm_type: type of communication to configure
1459 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1462 u32 cfg2_clrb = 0, cfg2_setb = 0;
1464 if (comm_type == SPI_3WIRE_RX) {
1465 mode = STM32H7_SPI_HALF_DUPLEX;
1466 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1467 } else if (comm_type == SPI_3WIRE_TX) {
1468 mode = STM32H7_SPI_HALF_DUPLEX;
1469 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1470 } else if (comm_type == SPI_SIMPLEX_RX) {
1471 mode = STM32H7_SPI_SIMPLEX_RX;
1472 } else if (comm_type == SPI_SIMPLEX_TX) {
1473 mode = STM32H7_SPI_SIMPLEX_TX;
1475 mode = STM32H7_SPI_FULL_DUPLEX;
1478 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1479 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1482 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1483 ~cfg2_clrb) | cfg2_setb,
1484 spi->base + STM32H7_SPI_CFG2);
1490 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1491 * consecutive data frames in master mode
1492 * @spi: pointer to the spi controller data structure
1493 * @len: transfer len
1495 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1497 u32 cfg2_clrb = 0, cfg2_setb = 0;
1499 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1500 if ((len > 1) && (spi->cur_midi > 0)) {
1501 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1502 u32 midi = min_t(u32,
1503 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1504 FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1505 STM32H7_SPI_CFG2_MIDI));
1508 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1509 sck_period_ns, midi, midi * sck_period_ns);
1510 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1513 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1514 ~cfg2_clrb) | cfg2_setb,
1515 spi->base + STM32H7_SPI_CFG2);
1519 * stm32h7_spi_number_of_data - configure number of data at current transfer
1520 * @spi: pointer to the spi controller data structure
1521 * @nb_words: transfer length (in words)
1523 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1525 if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
1526 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1527 spi->base + STM32H7_SPI_CR2);
1536 * stm32_spi_transfer_one_setup - common setup to transfer a single
1537 * spi_transfer either using DMA or
1539 * @spi: pointer to the spi controller data structure
1540 * @spi_dev: pointer to the spi device
1541 * @transfer: pointer to spi transfer
1543 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1544 struct spi_device *spi_dev,
1545 struct spi_transfer *transfer)
1547 unsigned long flags;
1548 unsigned int comm_type;
1549 int nb_words, ret = 0;
1552 spin_lock_irqsave(&spi->lock, flags);
1554 spi->cur_xferlen = transfer->len;
1556 spi->cur_bpw = transfer->bits_per_word;
1557 spi->cfg->set_bpw(spi);
1559 /* Update spi->cur_speed with real clock speed */
1560 if (STM32_SPI_MASTER_MODE(spi)) {
1561 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1562 spi->cfg->baud_rate_div_min,
1563 spi->cfg->baud_rate_div_max);
1569 transfer->speed_hz = spi->cur_speed;
1570 stm32_spi_set_mbr(spi, mbr);
1573 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1574 ret = spi->cfg->set_mode(spi, comm_type);
1578 spi->cur_comm = comm_type;
1580 if (STM32_SPI_MASTER_MODE(spi) && spi->cfg->set_data_idleness)
1581 spi->cfg->set_data_idleness(spi, transfer->len);
1583 if (spi->cur_bpw <= 8)
1584 nb_words = transfer->len;
1585 else if (spi->cur_bpw <= 16)
1586 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1588 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1590 if (spi->cfg->set_number_of_data) {
1591 ret = spi->cfg->set_number_of_data(spi, nb_words);
1596 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1599 "data frame of %d-bit, data packet of %d data frames\n",
1600 spi->cur_bpw, spi->cur_fthlv);
1601 if (STM32_SPI_MASTER_MODE(spi))
1602 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1603 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1604 spi->cur_xferlen, nb_words);
1605 dev_dbg(spi->dev, "dma %s\n",
1606 (spi->cur_usedma) ? "enabled" : "disabled");
1609 spin_unlock_irqrestore(&spi->lock, flags);
1615 * stm32_spi_transfer_one - transfer a single spi_transfer
1616 * @ctrl: controller interface
1617 * @spi_dev: pointer to the spi device
1618 * @transfer: pointer to spi transfer
1620 * It must return 0 if the transfer is finished or 1 if the transfer is still
1623 static int stm32_spi_transfer_one(struct spi_controller *ctrl,
1624 struct spi_device *spi_dev,
1625 struct spi_transfer *transfer)
1627 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1630 spi->tx_buf = transfer->tx_buf;
1631 spi->rx_buf = transfer->rx_buf;
1632 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1633 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1635 spi->cur_usedma = (ctrl->can_dma &&
1636 ctrl->can_dma(ctrl, spi_dev, transfer));
1638 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1640 dev_err(spi->dev, "SPI transfer setup failed\n");
1644 if (spi->cur_usedma)
1645 return stm32_spi_transfer_one_dma(spi, transfer);
1647 return spi->cfg->transfer_one_irq(spi);
1651 * stm32_spi_unprepare_msg - relax the hardware
1652 * @ctrl: controller interface
1653 * @msg: pointer to the spi message
1655 static int stm32_spi_unprepare_msg(struct spi_controller *ctrl,
1656 struct spi_message *msg)
1658 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1660 spi->cfg->disable(spi);
1666 * stm32f4_spi_config - Configure SPI controller as SPI master
1667 * @spi: pointer to the spi controller data structure
1669 static int stm32f4_spi_config(struct stm32_spi *spi)
1671 unsigned long flags;
1673 spin_lock_irqsave(&spi->lock, flags);
1675 /* Ensure I2SMOD bit is kept cleared */
1676 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1677 STM32F4_SPI_I2SCFGR_I2SMOD);
1680 * - SS input value high
1681 * - transmitter half duplex direction
1682 * - Set the master mode (default Motorola mode)
1683 * - Consider 1 master/n slaves configuration and
1684 * SS input value is determined by the SSI bit
1686 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1687 STM32F4_SPI_CR1_BIDIOE |
1688 STM32F4_SPI_CR1_MSTR |
1689 STM32F4_SPI_CR1_SSM);
1691 spin_unlock_irqrestore(&spi->lock, flags);
1697 * stm32h7_spi_config - Configure SPI controller
1698 * @spi: pointer to the spi controller data structure
1700 static int stm32h7_spi_config(struct stm32_spi *spi)
1702 unsigned long flags;
1703 u32 cr1 = 0, cfg2 = 0;
1705 spin_lock_irqsave(&spi->lock, flags);
1707 /* Ensure I2SMOD bit is kept cleared */
1708 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1709 STM32H7_SPI_I2SCFGR_I2SMOD);
1711 if (STM32_SPI_DEVICE_MODE(spi)) {
1712 /* Use native device select */
1713 cfg2 &= ~STM32H7_SPI_CFG2_SSM;
1716 * - Transmitter half duplex direction
1717 * - Automatic communication suspend when RX-Fifo is full
1718 * - SS input value high
1720 cr1 |= STM32H7_SPI_CR1_HDDIR | STM32H7_SPI_CR1_MASRX | STM32H7_SPI_CR1_SSI;
1723 * - Set the master mode (default Motorola mode)
1724 * - Consider 1 master/n devices configuration and
1725 * SS input value is determined by the SSI bit
1726 * - keep control of all associated GPIOs
1728 cfg2 |= STM32H7_SPI_CFG2_MASTER | STM32H7_SPI_CFG2_SSM | STM32H7_SPI_CFG2_AFCNTR;
1731 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1);
1732 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, cfg2);
1734 spin_unlock_irqrestore(&spi->lock, flags);
1739 static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1740 .regs = &stm32f4_spi_regspec,
1741 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1742 .disable = stm32f4_spi_disable,
1743 .config = stm32f4_spi_config,
1744 .set_bpw = stm32f4_spi_set_bpw,
1745 .set_mode = stm32f4_spi_set_mode,
1746 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1747 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1748 .dma_rx_cb = stm32_spi_dma_rx_cb,
1749 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1750 .irq_handler_event = stm32f4_spi_irq_event,
1751 .irq_handler_thread = stm32f4_spi_irq_thread,
1752 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1753 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1755 .has_device_mode = false,
1756 .flags = SPI_CONTROLLER_MUST_TX,
1759 static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1760 .regs = &stm32h7_spi_regspec,
1761 .get_fifo_size = stm32h7_spi_get_fifo_size,
1762 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1763 .disable = stm32h7_spi_disable,
1764 .config = stm32h7_spi_config,
1765 .set_bpw = stm32h7_spi_set_bpw,
1766 .set_mode = stm32h7_spi_set_mode,
1767 .set_data_idleness = stm32h7_spi_data_idleness,
1768 .set_number_of_data = stm32h7_spi_number_of_data,
1769 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1770 .dma_rx_cb = stm32_spi_dma_rx_cb,
1772 * dma_tx_cb is not necessary since in case of TX, dma is followed by
1773 * SPI access hence handling is performed within the SPI interrupt
1775 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1776 .irq_handler_thread = stm32h7_spi_irq_thread,
1777 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1778 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1780 .has_device_mode = true,
1783 static const struct of_device_id stm32_spi_of_match[] = {
1784 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1785 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1788 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1790 static int stm32h7_spi_device_abort(struct spi_controller *ctrl)
1792 spi_finalize_current_transfer(ctrl);
1796 static int stm32_spi_probe(struct platform_device *pdev)
1798 struct spi_controller *ctrl;
1799 struct stm32_spi *spi;
1800 struct resource *res;
1801 struct reset_control *rst;
1802 struct device_node *np = pdev->dev.of_node;
1805 const struct stm32_spi_cfg *cfg = of_device_get_match_data(&pdev->dev);
1807 device_mode = of_property_read_bool(np, "spi-slave");
1808 if (!cfg->has_device_mode && device_mode) {
1809 dev_err(&pdev->dev, "spi-slave not supported\n");
1814 ctrl = devm_spi_alloc_slave(&pdev->dev, sizeof(struct stm32_spi));
1816 ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1818 dev_err(&pdev->dev, "spi controller allocation failed\n");
1821 platform_set_drvdata(pdev, ctrl);
1823 spi = spi_controller_get_devdata(ctrl);
1824 spi->dev = &pdev->dev;
1826 spi->device_mode = device_mode;
1827 spin_lock_init(&spi->lock);
1831 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1832 if (IS_ERR(spi->base))
1833 return PTR_ERR(spi->base);
1835 spi->phys_addr = (dma_addr_t)res->start;
1837 spi->irq = platform_get_irq(pdev, 0);
1839 return dev_err_probe(&pdev->dev, spi->irq,
1840 "failed to get irq\n");
1842 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1843 spi->cfg->irq_handler_event,
1844 spi->cfg->irq_handler_thread,
1845 IRQF_ONESHOT, pdev->name, ctrl);
1847 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1852 spi->clk = devm_clk_get(&pdev->dev, NULL);
1853 if (IS_ERR(spi->clk)) {
1854 ret = PTR_ERR(spi->clk);
1855 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1859 ret = clk_prepare_enable(spi->clk);
1861 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1864 spi->clk_rate = clk_get_rate(spi->clk);
1865 if (!spi->clk_rate) {
1866 dev_err(&pdev->dev, "clk rate = 0\n");
1868 goto err_clk_disable;
1871 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1874 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
1875 "failed to get reset\n");
1876 goto err_clk_disable;
1879 reset_control_assert(rst);
1881 reset_control_deassert(rst);
1884 if (spi->cfg->has_fifo)
1885 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1887 ret = spi->cfg->config(spi);
1889 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1891 goto err_clk_disable;
1894 ctrl->dev.of_node = pdev->dev.of_node;
1895 ctrl->auto_runtime_pm = true;
1896 ctrl->bus_num = pdev->id;
1897 ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1899 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1900 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1901 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1902 ctrl->use_gpio_descriptors = true;
1903 ctrl->prepare_message = stm32_spi_prepare_msg;
1904 ctrl->transfer_one = stm32_spi_transfer_one;
1905 ctrl->unprepare_message = stm32_spi_unprepare_msg;
1906 ctrl->flags = spi->cfg->flags;
1907 if (STM32_SPI_DEVICE_MODE(spi))
1908 ctrl->slave_abort = stm32h7_spi_device_abort;
1910 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1911 if (IS_ERR(spi->dma_tx)) {
1912 ret = PTR_ERR(spi->dma_tx);
1914 if (ret == -EPROBE_DEFER)
1915 goto err_clk_disable;
1917 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1919 ctrl->dma_tx = spi->dma_tx;
1922 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1923 if (IS_ERR(spi->dma_rx)) {
1924 ret = PTR_ERR(spi->dma_rx);
1926 if (ret == -EPROBE_DEFER)
1927 goto err_dma_release;
1929 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1931 ctrl->dma_rx = spi->dma_rx;
1934 if (spi->dma_tx || spi->dma_rx)
1935 ctrl->can_dma = stm32_spi_can_dma;
1937 pm_runtime_set_autosuspend_delay(&pdev->dev,
1938 STM32_SPI_AUTOSUSPEND_DELAY);
1939 pm_runtime_use_autosuspend(&pdev->dev);
1940 pm_runtime_set_active(&pdev->dev);
1941 pm_runtime_get_noresume(&pdev->dev);
1942 pm_runtime_enable(&pdev->dev);
1944 ret = spi_register_controller(ctrl);
1946 dev_err(&pdev->dev, "spi controller registration failed: %d\n",
1948 goto err_pm_disable;
1951 pm_runtime_mark_last_busy(&pdev->dev);
1952 pm_runtime_put_autosuspend(&pdev->dev);
1954 dev_info(&pdev->dev, "driver initialized (%s mode)\n",
1955 STM32_SPI_MASTER_MODE(spi) ? "master" : "device");
1960 pm_runtime_disable(&pdev->dev);
1961 pm_runtime_put_noidle(&pdev->dev);
1962 pm_runtime_set_suspended(&pdev->dev);
1963 pm_runtime_dont_use_autosuspend(&pdev->dev);
1966 dma_release_channel(spi->dma_tx);
1968 dma_release_channel(spi->dma_rx);
1970 clk_disable_unprepare(spi->clk);
1975 static void stm32_spi_remove(struct platform_device *pdev)
1977 struct spi_controller *ctrl = platform_get_drvdata(pdev);
1978 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1980 pm_runtime_get_sync(&pdev->dev);
1982 spi_unregister_controller(ctrl);
1983 spi->cfg->disable(spi);
1985 pm_runtime_disable(&pdev->dev);
1986 pm_runtime_put_noidle(&pdev->dev);
1987 pm_runtime_set_suspended(&pdev->dev);
1988 pm_runtime_dont_use_autosuspend(&pdev->dev);
1991 dma_release_channel(ctrl->dma_tx);
1993 dma_release_channel(ctrl->dma_rx);
1995 clk_disable_unprepare(spi->clk);
1998 pinctrl_pm_select_sleep_state(&pdev->dev);
2001 static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
2003 struct spi_controller *ctrl = dev_get_drvdata(dev);
2004 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2006 clk_disable_unprepare(spi->clk);
2008 return pinctrl_pm_select_sleep_state(dev);
2011 static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
2013 struct spi_controller *ctrl = dev_get_drvdata(dev);
2014 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2017 ret = pinctrl_pm_select_default_state(dev);
2021 return clk_prepare_enable(spi->clk);
2024 static int __maybe_unused stm32_spi_suspend(struct device *dev)
2026 struct spi_controller *ctrl = dev_get_drvdata(dev);
2029 ret = spi_controller_suspend(ctrl);
2033 return pm_runtime_force_suspend(dev);
2036 static int __maybe_unused stm32_spi_resume(struct device *dev)
2038 struct spi_controller *ctrl = dev_get_drvdata(dev);
2039 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2042 ret = pm_runtime_force_resume(dev);
2046 ret = spi_controller_resume(ctrl);
2048 clk_disable_unprepare(spi->clk);
2052 ret = pm_runtime_resume_and_get(dev);
2054 dev_err(dev, "Unable to power device:%d\n", ret);
2058 spi->cfg->config(spi);
2060 pm_runtime_mark_last_busy(dev);
2061 pm_runtime_put_autosuspend(dev);
2066 static const struct dev_pm_ops stm32_spi_pm_ops = {
2067 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2068 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2069 stm32_spi_runtime_resume, NULL)
2072 static struct platform_driver stm32_spi_driver = {
2073 .probe = stm32_spi_probe,
2074 .remove_new = stm32_spi_remove,
2076 .name = DRIVER_NAME,
2077 .pm = &stm32_spi_pm_ops,
2078 .of_match_table = stm32_spi_of_match,
2082 module_platform_driver(stm32_spi_driver);
2084 MODULE_ALIAS("platform:" DRIVER_NAME);
2085 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2086 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2087 MODULE_LICENSE("GPL v2");