1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
8 #include <linux/bitfield.h>
9 #include <linux/debugfs.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/spi/spi.h>
22 #define DRIVER_NAME "spi_stm32"
24 /* STM32F4 SPI registers */
25 #define STM32F4_SPI_CR1 0x00
26 #define STM32F4_SPI_CR2 0x04
27 #define STM32F4_SPI_SR 0x08
28 #define STM32F4_SPI_DR 0x0C
29 #define STM32F4_SPI_I2SCFGR 0x1C
31 /* STM32F4_SPI_CR1 bit fields */
32 #define STM32F4_SPI_CR1_CPHA BIT(0)
33 #define STM32F4_SPI_CR1_CPOL BIT(1)
34 #define STM32F4_SPI_CR1_MSTR BIT(2)
35 #define STM32F4_SPI_CR1_BR_SHIFT 3
36 #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
37 #define STM32F4_SPI_CR1_SPE BIT(6)
38 #define STM32F4_SPI_CR1_LSBFRST BIT(7)
39 #define STM32F4_SPI_CR1_SSI BIT(8)
40 #define STM32F4_SPI_CR1_SSM BIT(9)
41 #define STM32F4_SPI_CR1_RXONLY BIT(10)
42 #define STM32F4_SPI_CR1_DFF BIT(11)
43 #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
44 #define STM32F4_SPI_CR1_CRCEN BIT(13)
45 #define STM32F4_SPI_CR1_BIDIOE BIT(14)
46 #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
47 #define STM32F4_SPI_CR1_BR_MIN 0
48 #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
50 /* STM32F4_SPI_CR2 bit fields */
51 #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
52 #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
53 #define STM32F4_SPI_CR2_SSOE BIT(2)
54 #define STM32F4_SPI_CR2_FRF BIT(4)
55 #define STM32F4_SPI_CR2_ERRIE BIT(5)
56 #define STM32F4_SPI_CR2_RXNEIE BIT(6)
57 #define STM32F4_SPI_CR2_TXEIE BIT(7)
59 /* STM32F4_SPI_SR bit fields */
60 #define STM32F4_SPI_SR_RXNE BIT(0)
61 #define STM32F4_SPI_SR_TXE BIT(1)
62 #define STM32F4_SPI_SR_CHSIDE BIT(2)
63 #define STM32F4_SPI_SR_UDR BIT(3)
64 #define STM32F4_SPI_SR_CRCERR BIT(4)
65 #define STM32F4_SPI_SR_MODF BIT(5)
66 #define STM32F4_SPI_SR_OVR BIT(6)
67 #define STM32F4_SPI_SR_BSY BIT(7)
68 #define STM32F4_SPI_SR_FRE BIT(8)
70 /* STM32F4_SPI_I2SCFGR bit fields */
71 #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
73 /* STM32F4 SPI Baud Rate min/max divisor */
74 #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
75 #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
77 /* STM32H7 SPI registers */
78 #define STM32H7_SPI_CR1 0x00
79 #define STM32H7_SPI_CR2 0x04
80 #define STM32H7_SPI_CFG1 0x08
81 #define STM32H7_SPI_CFG2 0x0C
82 #define STM32H7_SPI_IER 0x10
83 #define STM32H7_SPI_SR 0x14
84 #define STM32H7_SPI_IFCR 0x18
85 #define STM32H7_SPI_TXDR 0x20
86 #define STM32H7_SPI_RXDR 0x30
87 #define STM32H7_SPI_I2SCFGR 0x50
89 /* STM32H7_SPI_CR1 bit fields */
90 #define STM32H7_SPI_CR1_SPE BIT(0)
91 #define STM32H7_SPI_CR1_MASRX BIT(8)
92 #define STM32H7_SPI_CR1_CSTART BIT(9)
93 #define STM32H7_SPI_CR1_CSUSP BIT(10)
94 #define STM32H7_SPI_CR1_HDDIR BIT(11)
95 #define STM32H7_SPI_CR1_SSI BIT(12)
97 /* STM32H7_SPI_CR2 bit fields */
98 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
99 #define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
101 /* STM32H7_SPI_CFG1 bit fields */
102 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
104 #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
105 #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
106 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
107 #define STM32H7_SPI_CFG1_MBR_SHIFT 28
108 #define STM32H7_SPI_CFG1_MBR_MIN 0
109 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
111 /* STM32H7_SPI_CFG2 bit fields */
112 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
113 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
114 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
115 #define STM32H7_SPI_CFG2_MASTER BIT(22)
116 #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
117 #define STM32H7_SPI_CFG2_CPHA BIT(24)
118 #define STM32H7_SPI_CFG2_CPOL BIT(25)
119 #define STM32H7_SPI_CFG2_SSM BIT(26)
120 #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
122 /* STM32H7_SPI_IER bit fields */
123 #define STM32H7_SPI_IER_RXPIE BIT(0)
124 #define STM32H7_SPI_IER_TXPIE BIT(1)
125 #define STM32H7_SPI_IER_DXPIE BIT(2)
126 #define STM32H7_SPI_IER_EOTIE BIT(3)
127 #define STM32H7_SPI_IER_TXTFIE BIT(4)
128 #define STM32H7_SPI_IER_OVRIE BIT(6)
129 #define STM32H7_SPI_IER_MODFIE BIT(9)
130 #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
132 /* STM32H7_SPI_SR bit fields */
133 #define STM32H7_SPI_SR_RXP BIT(0)
134 #define STM32H7_SPI_SR_TXP BIT(1)
135 #define STM32H7_SPI_SR_EOT BIT(3)
136 #define STM32H7_SPI_SR_OVR BIT(6)
137 #define STM32H7_SPI_SR_MODF BIT(9)
138 #define STM32H7_SPI_SR_SUSP BIT(11)
139 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
140 #define STM32H7_SPI_SR_RXWNE BIT(15)
142 /* STM32H7_SPI_IFCR bit fields */
143 #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
145 /* STM32H7_SPI_I2SCFGR bit fields */
146 #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
148 /* STM32H7 SPI Master Baud Rate min/max divisor */
149 #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
150 #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
152 /* STM32H7 SPI Communication mode */
153 #define STM32H7_SPI_FULL_DUPLEX 0
154 #define STM32H7_SPI_SIMPLEX_TX 1
155 #define STM32H7_SPI_SIMPLEX_RX 2
156 #define STM32H7_SPI_HALF_DUPLEX 3
158 /* SPI Communication type */
159 #define SPI_FULL_DUPLEX 0
160 #define SPI_SIMPLEX_TX 1
161 #define SPI_SIMPLEX_RX 2
162 #define SPI_3WIRE_TX 3
163 #define SPI_3WIRE_RX 4
166 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
167 * without fifo buffers.
169 #define SPI_DMA_MIN_BYTES 16
172 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
173 * @reg: register offset
174 * @mask: bitfield mask
177 struct stm32_spi_reg {
184 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
185 * @en: enable register and SPI enable bit
186 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
187 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
188 * @cpol: clock polarity register and polarity bit
189 * @cpha: clock phase register and phase bit
190 * @lsb_first: LSB transmitted first register and bit
191 * @br: baud rate register and bitfields
192 * @rx: SPI RX data register
193 * @tx: SPI TX data register
195 struct stm32_spi_regspec {
196 const struct stm32_spi_reg en;
197 const struct stm32_spi_reg dma_rx_en;
198 const struct stm32_spi_reg dma_tx_en;
199 const struct stm32_spi_reg cpol;
200 const struct stm32_spi_reg cpha;
201 const struct stm32_spi_reg lsb_first;
202 const struct stm32_spi_reg br;
203 const struct stm32_spi_reg rx;
204 const struct stm32_spi_reg tx;
210 * struct stm32_spi_cfg - stm32 compatible configuration data
211 * @regs: registers descriptions
212 * @get_fifo_size: routine to get fifo size
213 * @get_bpw_mask: routine to get bits per word mask
214 * @disable: routine to disable controller
215 * @config: routine to configure controller as SPI Master
216 * @set_bpw: routine to configure registers to for bits per word
217 * @set_mode: routine to configure registers to desired mode
218 * @set_data_idleness: optional routine to configure registers to desired idle
219 * time between frames (if driver has this functionality)
220 * @set_number_of_data: optional routine to configure registers to desired
221 * number of data (if driver has this functionality)
222 * @can_dma: routine to determine if the transfer is eligible for DMA use
223 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
225 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
226 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
227 * @transfer_one_irq: routine to configure interrupts for driver
228 * @irq_handler_event: Interrupt handler for SPI controller events
229 * @irq_handler_thread: thread of interrupt handler for SPI controller
230 * @baud_rate_div_min: minimum baud rate divisor
231 * @baud_rate_div_max: maximum baud rate divisor
232 * @has_fifo: boolean to know if fifo is used for driver
233 * @has_startbit: boolean to know if start bit is used to start transfer
235 struct stm32_spi_cfg {
236 const struct stm32_spi_regspec *regs;
237 int (*get_fifo_size)(struct stm32_spi *spi);
238 int (*get_bpw_mask)(struct stm32_spi *spi);
239 void (*disable)(struct stm32_spi *spi);
240 int (*config)(struct stm32_spi *spi);
241 void (*set_bpw)(struct stm32_spi *spi);
242 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
243 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
244 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
245 void (*transfer_one_dma_start)(struct stm32_spi *spi);
246 void (*dma_rx_cb)(void *data);
247 void (*dma_tx_cb)(void *data);
248 int (*transfer_one_irq)(struct stm32_spi *spi);
249 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
250 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
251 unsigned int baud_rate_div_min;
252 unsigned int baud_rate_div_max;
257 * struct stm32_spi - private data of the SPI controller
258 * @dev: driver model representation of the controller
259 * @master: controller master interface
260 * @cfg: compatible configuration data
261 * @base: virtual memory area
262 * @clk: hw kernel clock feeding the SPI clock generator
263 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
264 * @lock: prevent I/O concurrent access
265 * @irq: SPI controller interrupt line
266 * @fifo_size: size of the embedded fifo in bytes
267 * @cur_midi: master inter-data idleness in ns
268 * @cur_speed: speed configured in Hz
269 * @cur_bpw: number of bits in a single SPI data frame
270 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
271 * @cur_comm: SPI communication mode
272 * @cur_xferlen: current transfer length in bytes
273 * @cur_usedma: boolean to know if dma is used in current transfer
274 * @tx_buf: data to be written, or NULL
275 * @rx_buf: data to be read, or NULL
276 * @tx_len: number of data to be written in bytes
277 * @rx_len: number of data to be read in bytes
278 * @dma_tx: dma channel for TX transfer
279 * @dma_rx: dma channel for RX transfer
280 * @phys_addr: SPI registers physical base address
284 struct spi_master *master;
285 const struct stm32_spi_cfg *cfg;
289 spinlock_t lock; /* prevent I/O concurrent access */
291 unsigned int fifo_size;
293 unsigned int cur_midi;
294 unsigned int cur_speed;
295 unsigned int cur_bpw;
296 unsigned int cur_fthlv;
297 unsigned int cur_comm;
298 unsigned int cur_xferlen;
305 struct dma_chan *dma_tx;
306 struct dma_chan *dma_rx;
307 dma_addr_t phys_addr;
310 static const struct stm32_spi_regspec stm32f4_spi_regspec = {
311 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
313 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
314 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
316 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
317 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
318 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
319 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
321 .rx = { STM32F4_SPI_DR },
322 .tx = { STM32F4_SPI_DR },
325 static const struct stm32_spi_regspec stm32h7_spi_regspec = {
326 /* SPI data transfer is enabled but spi_ker_ck is idle.
327 * CFG1 and CFG2 registers are write protected when SPE is enabled.
329 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
331 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
332 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
334 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
335 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
336 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
337 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
338 STM32H7_SPI_CFG1_MBR_SHIFT },
340 .rx = { STM32H7_SPI_RXDR },
341 .tx = { STM32H7_SPI_TXDR },
344 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
345 u32 offset, u32 bits)
347 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
351 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
352 u32 offset, u32 bits)
354 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
359 * stm32h7_spi_get_fifo_size - Return fifo size
360 * @spi: pointer to the spi controller data structure
362 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
367 spin_lock_irqsave(&spi->lock, flags);
369 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
371 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
372 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
374 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
376 spin_unlock_irqrestore(&spi->lock, flags);
378 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
384 * stm32f4_spi_get_bpw_mask - Return bits per word mask
385 * @spi: pointer to the spi controller data structure
387 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
389 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
390 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
394 * stm32h7_spi_get_bpw_mask - Return bits per word mask
395 * @spi: pointer to the spi controller data structure
397 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
402 spin_lock_irqsave(&spi->lock, flags);
405 * The most significant bit at DSIZE bit field is reserved when the
406 * maximum data size of periperal instances is limited to 16-bit
408 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
410 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
411 max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
413 spin_unlock_irqrestore(&spi->lock, flags);
415 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
417 return SPI_BPW_RANGE_MASK(4, max_bpw);
421 * stm32_spi_prepare_mbr - Determine baud rate divisor value
422 * @spi: pointer to the spi controller data structure
423 * @speed_hz: requested speed
424 * @min_div: minimum baud rate divisor
425 * @max_div: maximum baud rate divisor
427 * Return baud rate divisor value in case of success or -EINVAL
429 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
430 u32 min_div, u32 max_div)
434 /* Ensure spi->clk_rate is even */
435 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
438 * SPI framework set xfer->speed_hz to master->max_speed_hz if
439 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
440 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
441 * no need to check it there.
442 * However, we need to ensure the following calculations.
444 if ((div < min_div) || (div > max_div))
447 /* Determine the first power of 2 greater than or equal to div */
451 mbrdiv = fls(div) - 1;
453 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
459 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
460 * @spi: pointer to the spi controller data structure
461 * @xfer_len: length of the message to be transferred
463 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
467 /* data packet should not exceed 1/2 of fifo space */
468 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
470 /* align packet size with data registers access */
471 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
472 return DIV_ROUND_UP(packet, bpw);
476 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
477 * @spi: pointer to the spi controller data structure
479 * Read from tx_buf depends on remaining bytes to avoid to read beyond
482 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
484 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
485 STM32F4_SPI_SR_TXE)) {
486 u32 offs = spi->cur_xferlen - spi->tx_len;
488 if (spi->cur_bpw == 16) {
489 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
491 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
492 spi->tx_len -= sizeof(u16);
494 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
496 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
497 spi->tx_len -= sizeof(u8);
501 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
505 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
506 * @spi: pointer to the spi controller data structure
508 * Read from tx_buf depends on remaining bytes to avoid to read beyond
511 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
513 while ((spi->tx_len > 0) &&
514 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
515 STM32H7_SPI_SR_TXP)) {
516 u32 offs = spi->cur_xferlen - spi->tx_len;
518 if (spi->tx_len >= sizeof(u32)) {
519 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
521 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
522 spi->tx_len -= sizeof(u32);
523 } else if (spi->tx_len >= sizeof(u16)) {
524 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
526 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
527 spi->tx_len -= sizeof(u16);
529 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
531 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
532 spi->tx_len -= sizeof(u8);
536 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
540 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
541 * @spi: pointer to the spi controller data structure
543 * Write in rx_buf depends on remaining bytes to avoid to write beyond
546 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
548 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
549 STM32F4_SPI_SR_RXNE)) {
550 u32 offs = spi->cur_xferlen - spi->rx_len;
552 if (spi->cur_bpw == 16) {
553 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
555 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
556 spi->rx_len -= sizeof(u16);
558 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
560 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
561 spi->rx_len -= sizeof(u8);
565 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
569 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
570 * @spi: pointer to the spi controller data structure
571 * @flush: boolean indicating that FIFO should be flushed
573 * Write in rx_buf depends on remaining bytes to avoid to write beyond
576 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
578 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
579 u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
581 while ((spi->rx_len > 0) &&
582 ((sr & STM32H7_SPI_SR_RXP) ||
583 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
584 u32 offs = spi->cur_xferlen - spi->rx_len;
586 if ((spi->rx_len >= sizeof(u32)) ||
587 (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
588 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
590 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
591 spi->rx_len -= sizeof(u32);
592 } else if ((spi->rx_len >= sizeof(u16)) ||
593 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
594 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
596 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
597 spi->rx_len -= sizeof(u16);
599 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
601 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
602 spi->rx_len -= sizeof(u8);
605 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
606 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
609 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
610 flush ? "(flush)" : "", spi->rx_len);
614 * stm32_spi_enable - Enable SPI controller
615 * @spi: pointer to the spi controller data structure
617 static void stm32_spi_enable(struct stm32_spi *spi)
619 dev_dbg(spi->dev, "enable controller\n");
621 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
622 spi->cfg->regs->en.mask);
626 * stm32f4_spi_disable - Disable SPI controller
627 * @spi: pointer to the spi controller data structure
629 static void stm32f4_spi_disable(struct stm32_spi *spi)
634 dev_dbg(spi->dev, "disable controller\n");
636 spin_lock_irqsave(&spi->lock, flags);
638 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
639 STM32F4_SPI_CR1_SPE)) {
640 spin_unlock_irqrestore(&spi->lock, flags);
644 /* Disable interrupts */
645 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
646 STM32F4_SPI_CR2_RXNEIE |
647 STM32F4_SPI_CR2_ERRIE);
649 /* Wait until BSY = 0 */
650 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
651 sr, !(sr & STM32F4_SPI_SR_BSY),
653 dev_warn(spi->dev, "disabling condition timeout\n");
656 if (spi->cur_usedma && spi->dma_tx)
657 dmaengine_terminate_all(spi->dma_tx);
658 if (spi->cur_usedma && spi->dma_rx)
659 dmaengine_terminate_all(spi->dma_rx);
661 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
663 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
664 STM32F4_SPI_CR2_RXDMAEN);
666 /* Sequence to clear OVR flag */
667 readl_relaxed(spi->base + STM32F4_SPI_DR);
668 readl_relaxed(spi->base + STM32F4_SPI_SR);
670 spin_unlock_irqrestore(&spi->lock, flags);
674 * stm32h7_spi_disable - Disable SPI controller
675 * @spi: pointer to the spi controller data structure
677 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
678 * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
680 * Normally, if TSIZE has been configured, we should relax the hardware at the
681 * reception of the EOT interrupt. But in case of error, EOT will not be
682 * raised. So the subsystem unprepare_message call allows us to properly
683 * complete the transfer from an hardware point of view.
685 static void stm32h7_spi_disable(struct stm32_spi *spi)
690 dev_dbg(spi->dev, "disable controller\n");
692 spin_lock_irqsave(&spi->lock, flags);
694 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
696 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
697 spin_unlock_irqrestore(&spi->lock, flags);
701 /* Wait on EOT or suspend the flow */
702 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
703 sr, !(sr & STM32H7_SPI_SR_EOT),
705 if (cr1 & STM32H7_SPI_CR1_CSTART) {
706 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
707 spi->base + STM32H7_SPI_CR1);
708 if (readl_relaxed_poll_timeout_atomic(
709 spi->base + STM32H7_SPI_SR,
710 sr, !(sr & STM32H7_SPI_SR_SUSP),
713 "Suspend request timeout\n");
717 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
718 stm32h7_spi_read_rxfifo(spi, true);
720 if (spi->cur_usedma && spi->dma_tx)
721 dmaengine_terminate_all(spi->dma_tx);
722 if (spi->cur_usedma && spi->dma_rx)
723 dmaengine_terminate_all(spi->dma_rx);
725 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
727 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
728 STM32H7_SPI_CFG1_RXDMAEN);
730 /* Disable interrupts and clear status flags */
731 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
732 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
734 spin_unlock_irqrestore(&spi->lock, flags);
738 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
739 * @master: controller master interface
740 * @spi_dev: pointer to the spi device
741 * @transfer: pointer to spi transfer
743 * If driver has fifo and the current transfer size is greater than fifo size,
744 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
746 static bool stm32_spi_can_dma(struct spi_master *master,
747 struct spi_device *spi_dev,
748 struct spi_transfer *transfer)
750 unsigned int dma_size;
751 struct stm32_spi *spi = spi_master_get_devdata(master);
753 if (spi->cfg->has_fifo)
754 dma_size = spi->fifo_size;
756 dma_size = SPI_DMA_MIN_BYTES;
758 dev_dbg(spi->dev, "%s: %s\n", __func__,
759 (transfer->len > dma_size) ? "true" : "false");
761 return (transfer->len > dma_size);
765 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
766 * @irq: interrupt line
767 * @dev_id: SPI controller master interface
769 static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
771 struct spi_master *master = dev_id;
772 struct stm32_spi *spi = spi_master_get_devdata(master);
776 spin_lock(&spi->lock);
778 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
780 * BSY flag is not handled in interrupt but it is normal behavior when
783 sr &= ~STM32F4_SPI_SR_BSY;
785 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
786 spi->cur_comm == SPI_3WIRE_TX)) {
787 /* OVR flag shouldn't be handled for TX only mode */
788 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
789 mask |= STM32F4_SPI_SR_TXE;
792 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
793 spi->cur_comm == SPI_SIMPLEX_RX ||
794 spi->cur_comm == SPI_3WIRE_RX)) {
795 /* TXE flag is set and is handled when RXNE flag occurs */
796 sr &= ~STM32F4_SPI_SR_TXE;
797 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
801 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
802 spin_unlock(&spi->lock);
806 if (sr & STM32F4_SPI_SR_OVR) {
807 dev_warn(spi->dev, "Overrun: received value discarded\n");
809 /* Sequence to clear OVR flag */
810 readl_relaxed(spi->base + STM32F4_SPI_DR);
811 readl_relaxed(spi->base + STM32F4_SPI_SR);
814 * If overrun is detected, it means that something went wrong,
815 * so stop the current transfer. Transfer can wait for next
816 * RXNE but DR is already read and end never happens.
822 if (sr & STM32F4_SPI_SR_TXE) {
824 stm32f4_spi_write_tx(spi);
825 if (spi->tx_len == 0)
829 if (sr & STM32F4_SPI_SR_RXNE) {
830 stm32f4_spi_read_rx(spi);
831 if (spi->rx_len == 0)
833 else if (spi->tx_buf)/* Load data for discontinuous mode */
834 stm32f4_spi_write_tx(spi);
839 /* Immediately disable interrupts to do not generate new one */
840 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
841 STM32F4_SPI_CR2_TXEIE |
842 STM32F4_SPI_CR2_RXNEIE |
843 STM32F4_SPI_CR2_ERRIE);
844 spin_unlock(&spi->lock);
845 return IRQ_WAKE_THREAD;
848 spin_unlock(&spi->lock);
853 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
854 * @irq: interrupt line
855 * @dev_id: SPI controller master interface
857 static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
859 struct spi_master *master = dev_id;
860 struct stm32_spi *spi = spi_master_get_devdata(master);
862 spi_finalize_current_transfer(master);
863 stm32f4_spi_disable(spi);
869 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
870 * @irq: interrupt line
871 * @dev_id: SPI controller master interface
873 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
875 struct spi_master *master = dev_id;
876 struct stm32_spi *spi = spi_master_get_devdata(master);
881 spin_lock_irqsave(&spi->lock, flags);
883 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
884 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
888 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
889 * SUSP to acknowledge it later. TXC is automatically cleared
892 mask |= STM32H7_SPI_SR_SUSP;
894 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
895 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
897 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
898 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
901 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
903 spin_unlock_irqrestore(&spi->lock, flags);
907 if (sr & STM32H7_SPI_SR_SUSP) {
908 static DEFINE_RATELIMIT_STATE(rs,
909 DEFAULT_RATELIMIT_INTERVAL * 10,
911 if (__ratelimit(&rs))
912 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
913 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
914 stm32h7_spi_read_rxfifo(spi, false);
916 * If communication is suspended while using DMA, it means
917 * that something went wrong, so stop the current transfer
923 if (sr & STM32H7_SPI_SR_MODF) {
924 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
928 if (sr & STM32H7_SPI_SR_OVR) {
929 dev_err(spi->dev, "Overrun: RX data lost\n");
933 if (sr & STM32H7_SPI_SR_EOT) {
934 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
935 stm32h7_spi_read_rxfifo(spi, true);
939 if (sr & STM32H7_SPI_SR_TXP)
940 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
941 stm32h7_spi_write_txfifo(spi);
943 if (sr & STM32H7_SPI_SR_RXP)
944 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
945 stm32h7_spi_read_rxfifo(spi, false);
947 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
949 spin_unlock_irqrestore(&spi->lock, flags);
952 stm32h7_spi_disable(spi);
953 spi_finalize_current_transfer(master);
960 * stm32_spi_prepare_msg - set up the controller to transfer a single message
961 * @master: controller master interface
962 * @msg: pointer to spi message
964 static int stm32_spi_prepare_msg(struct spi_master *master,
965 struct spi_message *msg)
967 struct stm32_spi *spi = spi_master_get_devdata(master);
968 struct spi_device *spi_dev = msg->spi;
969 struct device_node *np = spi_dev->dev.of_node;
971 u32 clrb = 0, setb = 0;
973 /* SPI slave device may need time between data frames */
975 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
976 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
978 if (spi_dev->mode & SPI_CPOL)
979 setb |= spi->cfg->regs->cpol.mask;
981 clrb |= spi->cfg->regs->cpol.mask;
983 if (spi_dev->mode & SPI_CPHA)
984 setb |= spi->cfg->regs->cpha.mask;
986 clrb |= spi->cfg->regs->cpha.mask;
988 if (spi_dev->mode & SPI_LSB_FIRST)
989 setb |= spi->cfg->regs->lsb_first.mask;
991 clrb |= spi->cfg->regs->lsb_first.mask;
993 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
994 !!(spi_dev->mode & SPI_CPOL),
995 !!(spi_dev->mode & SPI_CPHA),
996 !!(spi_dev->mode & SPI_LSB_FIRST),
997 !!(spi_dev->mode & SPI_CS_HIGH));
999 /* On STM32H7, messages should not exceed a maximum size setted
1000 * afterward via the set_number_of_data function. In order to
1001 * ensure that, split large messages into several messages
1003 if (spi->cfg->set_number_of_data) {
1006 ret = spi_split_transfers_maxsize(master, msg,
1007 STM32H7_SPI_TSIZE_MAX,
1008 GFP_KERNEL | GFP_DMA);
1013 spin_lock_irqsave(&spi->lock, flags);
1015 /* CPOL, CPHA and LSB FIRST bits have common register */
1018 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1020 spi->base + spi->cfg->regs->cpol.reg);
1022 spin_unlock_irqrestore(&spi->lock, flags);
1028 * stm32f4_spi_dma_tx_cb - dma callback
1029 * @data: pointer to the spi controller data structure
1031 * DMA callback is called when the transfer is complete for DMA TX channel.
1033 static void stm32f4_spi_dma_tx_cb(void *data)
1035 struct stm32_spi *spi = data;
1037 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1038 spi_finalize_current_transfer(spi->master);
1039 stm32f4_spi_disable(spi);
1044 * stm32f4_spi_dma_rx_cb - dma callback
1045 * @data: pointer to the spi controller data structure
1047 * DMA callback is called when the transfer is complete for DMA RX channel.
1049 static void stm32f4_spi_dma_rx_cb(void *data)
1051 struct stm32_spi *spi = data;
1053 spi_finalize_current_transfer(spi->master);
1054 stm32f4_spi_disable(spi);
1058 * stm32h7_spi_dma_cb - dma callback
1059 * @data: pointer to the spi controller data structure
1061 * DMA callback is called when the transfer is complete or when an error
1062 * occurs. If the transfer is complete, EOT flag is raised.
1064 static void stm32h7_spi_dma_cb(void *data)
1066 struct stm32_spi *spi = data;
1067 unsigned long flags;
1070 spin_lock_irqsave(&spi->lock, flags);
1072 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1074 spin_unlock_irqrestore(&spi->lock, flags);
1076 if (!(sr & STM32H7_SPI_SR_EOT))
1077 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
1079 /* Now wait for EOT, or SUSP or OVR in case of error */
1083 * stm32_spi_dma_config - configure dma slave channel depending on current
1084 * transfer bits_per_word.
1085 * @spi: pointer to the spi controller data structure
1086 * @dma_conf: pointer to the dma_slave_config structure
1087 * @dir: direction of the dma transfer
1089 static void stm32_spi_dma_config(struct stm32_spi *spi,
1090 struct dma_slave_config *dma_conf,
1091 enum dma_transfer_direction dir)
1093 enum dma_slave_buswidth buswidth;
1096 if (spi->cur_bpw <= 8)
1097 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1098 else if (spi->cur_bpw <= 16)
1099 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1101 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1103 if (spi->cfg->has_fifo) {
1104 /* Valid for DMA Half or Full Fifo threshold */
1105 if (spi->cur_fthlv == 2)
1108 maxburst = spi->cur_fthlv;
1113 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1114 dma_conf->direction = dir;
1115 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1116 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1117 dma_conf->src_addr_width = buswidth;
1118 dma_conf->src_maxburst = maxburst;
1120 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1121 buswidth, maxburst);
1122 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1123 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1124 dma_conf->dst_addr_width = buswidth;
1125 dma_conf->dst_maxburst = maxburst;
1127 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1128 buswidth, maxburst);
1133 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1135 * @spi: pointer to the spi controller data structure
1137 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1140 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1142 unsigned long flags;
1145 /* Enable the interrupts relative to the current communication mode */
1146 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1147 cr2 |= STM32F4_SPI_CR2_TXEIE;
1148 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1149 spi->cur_comm == SPI_SIMPLEX_RX ||
1150 spi->cur_comm == SPI_3WIRE_RX) {
1151 /* In transmit-only mode, the OVR flag is set in the SR register
1152 * since the received data are never read. Therefore set OVR
1153 * interrupt only when rx buffer is available.
1155 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1160 spin_lock_irqsave(&spi->lock, flags);
1162 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1164 stm32_spi_enable(spi);
1166 /* starting data transfer when buffer is loaded */
1168 stm32f4_spi_write_tx(spi);
1170 spin_unlock_irqrestore(&spi->lock, flags);
1176 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1178 * @spi: pointer to the spi controller data structure
1180 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1183 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1185 unsigned long flags;
1188 /* Enable the interrupts relative to the current communication mode */
1189 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1190 ier |= STM32H7_SPI_IER_DXPIE;
1191 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1192 ier |= STM32H7_SPI_IER_TXPIE;
1193 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1194 ier |= STM32H7_SPI_IER_RXPIE;
1196 /* Enable the interrupts relative to the end of transfer */
1197 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1198 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1200 spin_lock_irqsave(&spi->lock, flags);
1202 stm32_spi_enable(spi);
1204 /* Be sure to have data in fifo before starting data transfer */
1206 stm32h7_spi_write_txfifo(spi);
1208 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1210 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1212 spin_unlock_irqrestore(&spi->lock, flags);
1218 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1219 * transfer using DMA
1220 * @spi: pointer to the spi controller data structure
1222 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1224 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1225 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1226 spi->cur_comm == SPI_FULL_DUPLEX) {
1228 * In transmit-only mode, the OVR flag is set in the SR register
1229 * since the received data are never read. Therefore set OVR
1230 * interrupt only when rx buffer is available.
1232 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1235 stm32_spi_enable(spi);
1239 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1240 * transfer using DMA
1241 * @spi: pointer to the spi controller data structure
1243 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1245 /* Enable the interrupts relative to the end of transfer */
1246 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1247 STM32H7_SPI_IER_TXTFIE |
1248 STM32H7_SPI_IER_OVRIE |
1249 STM32H7_SPI_IER_MODFIE);
1251 stm32_spi_enable(spi);
1253 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1257 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1258 * @spi: pointer to the spi controller data structure
1259 * @xfer: pointer to the spi_transfer structure
1261 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1264 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1265 struct spi_transfer *xfer)
1267 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1268 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1269 unsigned long flags;
1271 spin_lock_irqsave(&spi->lock, flags);
1274 if (spi->rx_buf && spi->dma_rx) {
1275 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1276 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1278 /* Enable Rx DMA request */
1279 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1280 spi->cfg->regs->dma_rx_en.mask);
1282 rx_dma_desc = dmaengine_prep_slave_sg(
1283 spi->dma_rx, xfer->rx_sg.sgl,
1285 rx_dma_conf.direction,
1286 DMA_PREP_INTERRUPT);
1290 if (spi->tx_buf && spi->dma_tx) {
1291 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1292 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1294 tx_dma_desc = dmaengine_prep_slave_sg(
1295 spi->dma_tx, xfer->tx_sg.sgl,
1297 tx_dma_conf.direction,
1298 DMA_PREP_INTERRUPT);
1301 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1302 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1303 goto dma_desc_error;
1305 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1306 goto dma_desc_error;
1309 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1310 rx_dma_desc->callback_param = spi;
1312 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1313 dev_err(spi->dev, "Rx DMA submit failed\n");
1314 goto dma_desc_error;
1316 /* Enable Rx DMA channel */
1317 dma_async_issue_pending(spi->dma_rx);
1321 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1322 spi->cur_comm == SPI_3WIRE_TX) {
1323 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1324 tx_dma_desc->callback_param = spi;
1327 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1328 dev_err(spi->dev, "Tx DMA submit failed\n");
1329 goto dma_submit_error;
1331 /* Enable Tx DMA channel */
1332 dma_async_issue_pending(spi->dma_tx);
1334 /* Enable Tx DMA request */
1335 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1336 spi->cfg->regs->dma_tx_en.mask);
1339 spi->cfg->transfer_one_dma_start(spi);
1341 spin_unlock_irqrestore(&spi->lock, flags);
1347 dmaengine_terminate_all(spi->dma_rx);
1350 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1351 spi->cfg->regs->dma_rx_en.mask);
1353 spin_unlock_irqrestore(&spi->lock, flags);
1355 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1357 spi->cur_usedma = false;
1358 return spi->cfg->transfer_one_irq(spi);
1362 * stm32f4_spi_set_bpw - Configure bits per word
1363 * @spi: pointer to the spi controller data structure
1365 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1367 if (spi->cur_bpw == 16)
1368 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1370 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1374 * stm32h7_spi_set_bpw - configure bits per word
1375 * @spi: pointer to the spi controller data structure
1377 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1380 u32 cfg1_clrb = 0, cfg1_setb = 0;
1382 bpw = spi->cur_bpw - 1;
1384 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1385 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1387 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1388 fthlv = spi->cur_fthlv - 1;
1390 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1391 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1394 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1395 ~cfg1_clrb) | cfg1_setb,
1396 spi->base + STM32H7_SPI_CFG1);
1400 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1401 * @spi: pointer to the spi controller data structure
1402 * @mbrdiv: baud rate divisor value
1404 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1406 u32 clrb = 0, setb = 0;
1408 clrb |= spi->cfg->regs->br.mask;
1409 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1411 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1413 spi->base + spi->cfg->regs->br.reg);
1417 * stm32_spi_communication_type - return transfer communication type
1418 * @spi_dev: pointer to the spi device
1419 * @transfer: pointer to spi transfer
1421 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1422 struct spi_transfer *transfer)
1424 unsigned int type = SPI_FULL_DUPLEX;
1426 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1428 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1429 * is forbidden and unvalidated by SPI subsystem so depending
1430 * on the valid buffer, we can determine the direction of the
1433 if (!transfer->tx_buf)
1434 type = SPI_3WIRE_RX;
1436 type = SPI_3WIRE_TX;
1438 if (!transfer->tx_buf)
1439 type = SPI_SIMPLEX_RX;
1440 else if (!transfer->rx_buf)
1441 type = SPI_SIMPLEX_TX;
1448 * stm32f4_spi_set_mode - configure communication mode
1449 * @spi: pointer to the spi controller data structure
1450 * @comm_type: type of communication to configure
1452 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1454 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1455 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1456 STM32F4_SPI_CR1_BIDIMODE |
1457 STM32F4_SPI_CR1_BIDIOE);
1458 } else if (comm_type == SPI_FULL_DUPLEX ||
1459 comm_type == SPI_SIMPLEX_RX) {
1460 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1461 STM32F4_SPI_CR1_BIDIMODE |
1462 STM32F4_SPI_CR1_BIDIOE);
1463 } else if (comm_type == SPI_3WIRE_RX) {
1464 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1465 STM32F4_SPI_CR1_BIDIMODE);
1466 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1467 STM32F4_SPI_CR1_BIDIOE);
1476 * stm32h7_spi_set_mode - configure communication mode
1477 * @spi: pointer to the spi controller data structure
1478 * @comm_type: type of communication to configure
1480 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1483 u32 cfg2_clrb = 0, cfg2_setb = 0;
1485 if (comm_type == SPI_3WIRE_RX) {
1486 mode = STM32H7_SPI_HALF_DUPLEX;
1487 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1488 } else if (comm_type == SPI_3WIRE_TX) {
1489 mode = STM32H7_SPI_HALF_DUPLEX;
1490 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1491 } else if (comm_type == SPI_SIMPLEX_RX) {
1492 mode = STM32H7_SPI_SIMPLEX_RX;
1493 } else if (comm_type == SPI_SIMPLEX_TX) {
1494 mode = STM32H7_SPI_SIMPLEX_TX;
1496 mode = STM32H7_SPI_FULL_DUPLEX;
1499 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1500 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1503 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1504 ~cfg2_clrb) | cfg2_setb,
1505 spi->base + STM32H7_SPI_CFG2);
1511 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1512 * consecutive data frames in master mode
1513 * @spi: pointer to the spi controller data structure
1514 * @len: transfer len
1516 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1518 u32 cfg2_clrb = 0, cfg2_setb = 0;
1520 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1521 if ((len > 1) && (spi->cur_midi > 0)) {
1522 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1523 u32 midi = min_t(u32,
1524 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1525 FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1526 STM32H7_SPI_CFG2_MIDI));
1529 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1530 sck_period_ns, midi, midi * sck_period_ns);
1531 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1534 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1535 ~cfg2_clrb) | cfg2_setb,
1536 spi->base + STM32H7_SPI_CFG2);
1540 * stm32h7_spi_number_of_data - configure number of data at current transfer
1541 * @spi: pointer to the spi controller data structure
1542 * @nb_words: transfer length (in words)
1544 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1546 if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
1547 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1548 spi->base + STM32H7_SPI_CR2);
1557 * stm32_spi_transfer_one_setup - common setup to transfer a single
1558 * spi_transfer either using DMA or
1560 * @spi: pointer to the spi controller data structure
1561 * @spi_dev: pointer to the spi device
1562 * @transfer: pointer to spi transfer
1564 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1565 struct spi_device *spi_dev,
1566 struct spi_transfer *transfer)
1568 unsigned long flags;
1569 unsigned int comm_type;
1570 int nb_words, ret = 0;
1573 spin_lock_irqsave(&spi->lock, flags);
1575 spi->cur_xferlen = transfer->len;
1577 spi->cur_bpw = transfer->bits_per_word;
1578 spi->cfg->set_bpw(spi);
1580 /* Update spi->cur_speed with real clock speed */
1581 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1582 spi->cfg->baud_rate_div_min,
1583 spi->cfg->baud_rate_div_max);
1589 transfer->speed_hz = spi->cur_speed;
1590 stm32_spi_set_mbr(spi, mbr);
1592 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1593 ret = spi->cfg->set_mode(spi, comm_type);
1597 spi->cur_comm = comm_type;
1599 if (spi->cfg->set_data_idleness)
1600 spi->cfg->set_data_idleness(spi, transfer->len);
1602 if (spi->cur_bpw <= 8)
1603 nb_words = transfer->len;
1604 else if (spi->cur_bpw <= 16)
1605 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1607 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1609 if (spi->cfg->set_number_of_data) {
1610 ret = spi->cfg->set_number_of_data(spi, nb_words);
1615 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1618 "data frame of %d-bit, data packet of %d data frames\n",
1619 spi->cur_bpw, spi->cur_fthlv);
1620 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1621 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1622 spi->cur_xferlen, nb_words);
1623 dev_dbg(spi->dev, "dma %s\n",
1624 (spi->cur_usedma) ? "enabled" : "disabled");
1627 spin_unlock_irqrestore(&spi->lock, flags);
1633 * stm32_spi_transfer_one - transfer a single spi_transfer
1634 * @master: controller master interface
1635 * @spi_dev: pointer to the spi device
1636 * @transfer: pointer to spi transfer
1638 * It must return 0 if the transfer is finished or 1 if the transfer is still
1641 static int stm32_spi_transfer_one(struct spi_master *master,
1642 struct spi_device *spi_dev,
1643 struct spi_transfer *transfer)
1645 struct stm32_spi *spi = spi_master_get_devdata(master);
1648 /* Don't do anything on 0 bytes transfers */
1649 if (transfer->len == 0)
1652 spi->tx_buf = transfer->tx_buf;
1653 spi->rx_buf = transfer->rx_buf;
1654 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1655 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1657 spi->cur_usedma = (master->can_dma &&
1658 master->can_dma(master, spi_dev, transfer));
1660 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1662 dev_err(spi->dev, "SPI transfer setup failed\n");
1666 if (spi->cur_usedma)
1667 return stm32_spi_transfer_one_dma(spi, transfer);
1669 return spi->cfg->transfer_one_irq(spi);
1673 * stm32_spi_unprepare_msg - relax the hardware
1674 * @master: controller master interface
1675 * @msg: pointer to the spi message
1677 static int stm32_spi_unprepare_msg(struct spi_master *master,
1678 struct spi_message *msg)
1680 struct stm32_spi *spi = spi_master_get_devdata(master);
1682 spi->cfg->disable(spi);
1688 * stm32f4_spi_config - Configure SPI controller as SPI master
1689 * @spi: pointer to the spi controller data structure
1691 static int stm32f4_spi_config(struct stm32_spi *spi)
1693 unsigned long flags;
1695 spin_lock_irqsave(&spi->lock, flags);
1697 /* Ensure I2SMOD bit is kept cleared */
1698 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1699 STM32F4_SPI_I2SCFGR_I2SMOD);
1702 * - SS input value high
1703 * - transmitter half duplex direction
1704 * - Set the master mode (default Motorola mode)
1705 * - Consider 1 master/n slaves configuration and
1706 * SS input value is determined by the SSI bit
1708 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1709 STM32F4_SPI_CR1_BIDIOE |
1710 STM32F4_SPI_CR1_MSTR |
1711 STM32F4_SPI_CR1_SSM);
1713 spin_unlock_irqrestore(&spi->lock, flags);
1719 * stm32h7_spi_config - Configure SPI controller as SPI master
1720 * @spi: pointer to the spi controller data structure
1722 static int stm32h7_spi_config(struct stm32_spi *spi)
1724 unsigned long flags;
1726 spin_lock_irqsave(&spi->lock, flags);
1728 /* Ensure I2SMOD bit is kept cleared */
1729 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1730 STM32H7_SPI_I2SCFGR_I2SMOD);
1733 * - SS input value high
1734 * - transmitter half duplex direction
1735 * - automatic communication suspend when RX-Fifo is full
1737 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1738 STM32H7_SPI_CR1_HDDIR |
1739 STM32H7_SPI_CR1_MASRX);
1742 * - Set the master mode (default Motorola mode)
1743 * - Consider 1 master/n slaves configuration and
1744 * SS input value is determined by the SSI bit
1745 * - keep control of all associated GPIOs
1747 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1748 STM32H7_SPI_CFG2_SSM |
1749 STM32H7_SPI_CFG2_AFCNTR);
1751 spin_unlock_irqrestore(&spi->lock, flags);
1756 static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1757 .regs = &stm32f4_spi_regspec,
1758 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1759 .disable = stm32f4_spi_disable,
1760 .config = stm32f4_spi_config,
1761 .set_bpw = stm32f4_spi_set_bpw,
1762 .set_mode = stm32f4_spi_set_mode,
1763 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1764 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1765 .dma_rx_cb = stm32f4_spi_dma_rx_cb,
1766 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1767 .irq_handler_event = stm32f4_spi_irq_event,
1768 .irq_handler_thread = stm32f4_spi_irq_thread,
1769 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1770 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1774 static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1775 .regs = &stm32h7_spi_regspec,
1776 .get_fifo_size = stm32h7_spi_get_fifo_size,
1777 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1778 .disable = stm32h7_spi_disable,
1779 .config = stm32h7_spi_config,
1780 .set_bpw = stm32h7_spi_set_bpw,
1781 .set_mode = stm32h7_spi_set_mode,
1782 .set_data_idleness = stm32h7_spi_data_idleness,
1783 .set_number_of_data = stm32h7_spi_number_of_data,
1784 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1785 .dma_rx_cb = stm32h7_spi_dma_cb,
1786 .dma_tx_cb = stm32h7_spi_dma_cb,
1787 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1788 .irq_handler_thread = stm32h7_spi_irq_thread,
1789 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1790 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1794 static const struct of_device_id stm32_spi_of_match[] = {
1795 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1796 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1799 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1801 static int stm32_spi_probe(struct platform_device *pdev)
1803 struct spi_master *master;
1804 struct stm32_spi *spi;
1805 struct resource *res;
1806 struct reset_control *rst;
1809 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1811 dev_err(&pdev->dev, "spi master allocation failed\n");
1814 platform_set_drvdata(pdev, master);
1816 spi = spi_master_get_devdata(master);
1817 spi->dev = &pdev->dev;
1818 spi->master = master;
1819 spin_lock_init(&spi->lock);
1821 spi->cfg = (const struct stm32_spi_cfg *)
1822 of_match_device(pdev->dev.driver->of_match_table,
1825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1826 spi->base = devm_ioremap_resource(&pdev->dev, res);
1827 if (IS_ERR(spi->base))
1828 return PTR_ERR(spi->base);
1830 spi->phys_addr = (dma_addr_t)res->start;
1832 spi->irq = platform_get_irq(pdev, 0);
1834 return dev_err_probe(&pdev->dev, spi->irq,
1835 "failed to get irq\n");
1837 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1838 spi->cfg->irq_handler_event,
1839 spi->cfg->irq_handler_thread,
1840 IRQF_ONESHOT, pdev->name, master);
1842 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1847 spi->clk = devm_clk_get(&pdev->dev, NULL);
1848 if (IS_ERR(spi->clk)) {
1849 ret = PTR_ERR(spi->clk);
1850 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1854 ret = clk_prepare_enable(spi->clk);
1856 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1859 spi->clk_rate = clk_get_rate(spi->clk);
1860 if (!spi->clk_rate) {
1861 dev_err(&pdev->dev, "clk rate = 0\n");
1863 goto err_clk_disable;
1866 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1869 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
1870 "failed to get reset\n");
1871 goto err_clk_disable;
1874 reset_control_assert(rst);
1876 reset_control_deassert(rst);
1879 if (spi->cfg->has_fifo)
1880 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1882 ret = spi->cfg->config(spi);
1884 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1886 goto err_clk_disable;
1889 master->dev.of_node = pdev->dev.of_node;
1890 master->auto_runtime_pm = true;
1891 master->bus_num = pdev->id;
1892 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1894 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1895 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1896 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1897 master->use_gpio_descriptors = true;
1898 master->prepare_message = stm32_spi_prepare_msg;
1899 master->transfer_one = stm32_spi_transfer_one;
1900 master->unprepare_message = stm32_spi_unprepare_msg;
1901 master->flags = SPI_MASTER_MUST_TX;
1903 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1904 if (IS_ERR(spi->dma_tx)) {
1905 ret = PTR_ERR(spi->dma_tx);
1907 if (ret == -EPROBE_DEFER)
1908 goto err_clk_disable;
1910 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1912 master->dma_tx = spi->dma_tx;
1915 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1916 if (IS_ERR(spi->dma_rx)) {
1917 ret = PTR_ERR(spi->dma_rx);
1919 if (ret == -EPROBE_DEFER)
1920 goto err_dma_release;
1922 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1924 master->dma_rx = spi->dma_rx;
1927 if (spi->dma_tx || spi->dma_rx)
1928 master->can_dma = stm32_spi_can_dma;
1930 pm_runtime_set_active(&pdev->dev);
1931 pm_runtime_get_noresume(&pdev->dev);
1932 pm_runtime_enable(&pdev->dev);
1934 ret = spi_register_master(master);
1936 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1938 goto err_pm_disable;
1941 dev_info(&pdev->dev, "driver initialized\n");
1946 pm_runtime_disable(&pdev->dev);
1947 pm_runtime_put_noidle(&pdev->dev);
1948 pm_runtime_set_suspended(&pdev->dev);
1951 dma_release_channel(spi->dma_tx);
1953 dma_release_channel(spi->dma_rx);
1955 clk_disable_unprepare(spi->clk);
1960 static int stm32_spi_remove(struct platform_device *pdev)
1962 struct spi_master *master = platform_get_drvdata(pdev);
1963 struct stm32_spi *spi = spi_master_get_devdata(master);
1965 pm_runtime_get_sync(&pdev->dev);
1967 spi_unregister_master(master);
1968 spi->cfg->disable(spi);
1970 pm_runtime_disable(&pdev->dev);
1971 pm_runtime_put_noidle(&pdev->dev);
1972 pm_runtime_set_suspended(&pdev->dev);
1974 dma_release_channel(master->dma_tx);
1976 dma_release_channel(master->dma_rx);
1978 clk_disable_unprepare(spi->clk);
1981 pinctrl_pm_select_sleep_state(&pdev->dev);
1986 static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
1988 struct spi_master *master = dev_get_drvdata(dev);
1989 struct stm32_spi *spi = spi_master_get_devdata(master);
1991 clk_disable_unprepare(spi->clk);
1993 return pinctrl_pm_select_sleep_state(dev);
1996 static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
1998 struct spi_master *master = dev_get_drvdata(dev);
1999 struct stm32_spi *spi = spi_master_get_devdata(master);
2002 ret = pinctrl_pm_select_default_state(dev);
2006 return clk_prepare_enable(spi->clk);
2009 static int __maybe_unused stm32_spi_suspend(struct device *dev)
2011 struct spi_master *master = dev_get_drvdata(dev);
2014 ret = spi_master_suspend(master);
2018 return pm_runtime_force_suspend(dev);
2021 static int __maybe_unused stm32_spi_resume(struct device *dev)
2023 struct spi_master *master = dev_get_drvdata(dev);
2024 struct stm32_spi *spi = spi_master_get_devdata(master);
2027 ret = pm_runtime_force_resume(dev);
2031 ret = spi_master_resume(master);
2033 clk_disable_unprepare(spi->clk);
2037 ret = pm_runtime_get_sync(dev);
2039 pm_runtime_put_noidle(dev);
2040 dev_err(dev, "Unable to power device:%d\n", ret);
2044 spi->cfg->config(spi);
2046 pm_runtime_mark_last_busy(dev);
2047 pm_runtime_put_autosuspend(dev);
2052 static const struct dev_pm_ops stm32_spi_pm_ops = {
2053 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2054 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2055 stm32_spi_runtime_resume, NULL)
2058 static struct platform_driver stm32_spi_driver = {
2059 .probe = stm32_spi_probe,
2060 .remove = stm32_spi_remove,
2062 .name = DRIVER_NAME,
2063 .pm = &stm32_spi_pm_ops,
2064 .of_match_table = stm32_spi_of_match,
2068 module_platform_driver(stm32_spi_driver);
2070 MODULE_ALIAS("platform:" DRIVER_NAME);
2071 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2072 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2073 MODULE_LICENSE("GPL v2");