1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH MSIOF SPI Controller Interface
5 * Copyright (c) 2009 Magnus Damm
6 * Copyright (C) 2014 Renesas Electronics Corporation
7 * Copyright (C) 2014-2017 Glider bvba
10 #include <linux/bitmap.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/sh_dma.h>
29 #include <linux/spi/sh_msiof.h>
30 #include <linux/spi/spi.h>
32 #include <asm/unaligned.h>
34 struct sh_msiof_chipdata {
41 struct sh_msiof_spi_priv {
42 struct spi_controller *ctlr;
43 void __iomem *mapbase;
45 struct platform_device *pdev;
46 struct sh_msiof_spi_info *info;
47 struct completion done;
48 struct completion done_txdma;
49 unsigned int tx_fifo_size;
50 unsigned int rx_fifo_size;
51 unsigned int min_div_pow;
54 dma_addr_t tx_dma_addr;
55 dma_addr_t rx_dma_addr;
56 unsigned short unused_ss;
57 bool native_cs_inited;
62 #define MAX_SS 3 /* Maximum number of native chip selects */
64 #define TMDR1 0x00 /* Transmit Mode Register 1 */
65 #define TMDR2 0x04 /* Transmit Mode Register 2 */
66 #define TMDR3 0x08 /* Transmit Mode Register 3 */
67 #define RMDR1 0x10 /* Receive Mode Register 1 */
68 #define RMDR2 0x14 /* Receive Mode Register 2 */
69 #define RMDR3 0x18 /* Receive Mode Register 3 */
70 #define TSCR 0x20 /* Transmit Clock Select Register */
71 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
72 #define CTR 0x28 /* Control Register */
73 #define FCTR 0x30 /* FIFO Control Register */
74 #define STR 0x40 /* Status Register */
75 #define IER 0x44 /* Interrupt Enable Register */
76 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
77 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
78 #define TFDR 0x50 /* Transmit FIFO Data Register */
79 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
80 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
81 #define RFDR 0x60 /* Receive FIFO Data Register */
84 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
85 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
86 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
87 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
88 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
89 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
90 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
91 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
92 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
93 #define MDR1_FLD_SHIFT 2
94 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
96 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
97 #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
98 #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
100 /* TMDR2 and RMDR2 */
101 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
102 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
103 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
106 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
107 #define SCR_BRPS(i) (((i) - 1) << 8)
108 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
109 #define SCR_BRDV_DIV_2 0x0000
110 #define SCR_BRDV_DIV_4 0x0001
111 #define SCR_BRDV_DIV_8 0x0002
112 #define SCR_BRDV_DIV_16 0x0003
113 #define SCR_BRDV_DIV_32 0x0004
114 #define SCR_BRDV_DIV_1 0x0007
117 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
118 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
119 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
120 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
121 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
122 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
123 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
124 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
125 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
126 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
127 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
128 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
129 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
130 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
131 #define CTR_TXE 0x00000200 /* Transmit Enable */
132 #define CTR_RXE 0x00000100 /* Receive Enable */
135 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
136 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
137 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
138 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
139 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
140 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
141 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
142 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
143 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
144 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
145 #define FCTR_TFUA_SHIFT 20
146 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
147 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
148 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
149 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
150 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
151 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
152 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
153 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
154 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
155 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
156 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
157 #define FCTR_RFUA_SHIFT 4
158 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
161 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
162 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
163 #define STR_TEOF 0x00800000 /* Frame Transmission End */
164 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
165 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
166 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
167 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
168 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
169 #define STR_REOF 0x00000080 /* Frame Reception End */
170 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
171 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
172 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
175 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
176 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
177 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
178 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
179 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
180 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
181 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
182 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
183 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
184 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
185 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
186 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
187 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
188 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
191 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
196 return ioread16(p->mapbase + reg_offs);
198 return ioread32(p->mapbase + reg_offs);
202 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
208 iowrite16(value, p->mapbase + reg_offs);
211 iowrite32(value, p->mapbase + reg_offs);
216 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
219 u32 mask = clr | set;
223 data = sh_msiof_read(p, CTR);
226 sh_msiof_write(p, CTR, data);
228 for (k = 100; k > 0; k--) {
229 if ((sh_msiof_read(p, CTR) & mask) == set)
235 return k > 0 ? 0 : -ETIMEDOUT;
238 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
240 struct sh_msiof_spi_priv *p = data;
242 /* just disable the interrupt and wake up */
243 sh_msiof_write(p, IER, 0);
249 static const u32 sh_msiof_spi_div_array[] = {
250 SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
251 SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
254 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
255 unsigned long parent_rate, u32 spi_hz)
259 unsigned int div_pow = p->min_div_pow;
261 if (!spi_hz || !parent_rate) {
262 WARN(1, "Invalid clock rate parameters %lu and %u\n",
263 parent_rate, spi_hz);
267 div = DIV_ROUND_UP(parent_rate, spi_hz);
269 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
270 if (!div_pow && div <= 32 && div > 2)
274 brps = (div + 1) >> div_pow;
278 for (; brps > 32; div_pow++)
279 brps = (brps + 1) >> 1;
281 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
282 dev_err(&p->pdev->dev,
283 "Requested SPI transfer rate %d is too low\n", spi_hz);
288 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
289 sh_msiof_write(p, TSCR, scr);
290 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
291 sh_msiof_write(p, RSCR, scr);
294 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
297 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
301 * b'011 (SYNCDL only) : 300
305 if (dtdl_or_syncdl % 100)
306 return dtdl_or_syncdl / 100 + 5;
308 return dtdl_or_syncdl / 100;
311 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
318 /* check if DTDL and SYNCDL is allowed value */
319 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
320 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
324 /* check if the sum of DTDL and SYNCDL becomes an integer value */
325 if ((p->info->dtdl + p->info->syncdl) % 100) {
326 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
330 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
331 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
336 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
338 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
344 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
350 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
351 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
352 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
353 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
354 if (spi_controller_is_slave(p->ctlr)) {
355 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
357 sh_msiof_write(p, TMDR1,
358 tmp | MDR1_TRMD | TMDR1_PCON |
359 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
361 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
362 /* These bits are reserved if RX needs TX */
365 sh_msiof_write(p, RMDR1, tmp);
368 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
369 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
373 tmp |= edge << CTR_TEDG_SHIFT;
374 tmp |= edge << CTR_REDG_SHIFT;
375 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
376 sh_msiof_write(p, CTR, tmp);
379 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
380 const void *tx_buf, void *rx_buf,
383 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
385 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
386 sh_msiof_write(p, TMDR2, dr2);
388 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
391 sh_msiof_write(p, RMDR2, dr2);
394 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
396 sh_msiof_write(p, STR,
397 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
400 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
401 const void *tx_buf, int words, int fs)
403 const u8 *buf_8 = tx_buf;
406 for (k = 0; k < words; k++)
407 sh_msiof_write(p, TFDR, buf_8[k] << fs);
410 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
411 const void *tx_buf, int words, int fs)
413 const u16 *buf_16 = tx_buf;
416 for (k = 0; k < words; k++)
417 sh_msiof_write(p, TFDR, buf_16[k] << fs);
420 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
421 const void *tx_buf, int words, int fs)
423 const u16 *buf_16 = tx_buf;
426 for (k = 0; k < words; k++)
427 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
430 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
431 const void *tx_buf, int words, int fs)
433 const u32 *buf_32 = tx_buf;
436 for (k = 0; k < words; k++)
437 sh_msiof_write(p, TFDR, buf_32[k] << fs);
440 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
441 const void *tx_buf, int words, int fs)
443 const u32 *buf_32 = tx_buf;
446 for (k = 0; k < words; k++)
447 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
450 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
451 const void *tx_buf, int words, int fs)
453 const u32 *buf_32 = tx_buf;
456 for (k = 0; k < words; k++)
457 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
460 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
461 const void *tx_buf, int words, int fs)
463 const u32 *buf_32 = tx_buf;
466 for (k = 0; k < words; k++)
467 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
470 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
471 void *rx_buf, int words, int fs)
476 for (k = 0; k < words; k++)
477 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
480 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
481 void *rx_buf, int words, int fs)
483 u16 *buf_16 = rx_buf;
486 for (k = 0; k < words; k++)
487 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
490 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
491 void *rx_buf, int words, int fs)
493 u16 *buf_16 = rx_buf;
496 for (k = 0; k < words; k++)
497 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
500 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
501 void *rx_buf, int words, int fs)
503 u32 *buf_32 = rx_buf;
506 for (k = 0; k < words; k++)
507 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
510 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
511 void *rx_buf, int words, int fs)
513 u32 *buf_32 = rx_buf;
516 for (k = 0; k < words; k++)
517 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
520 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
521 void *rx_buf, int words, int fs)
523 u32 *buf_32 = rx_buf;
526 for (k = 0; k < words; k++)
527 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
530 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
531 void *rx_buf, int words, int fs)
533 u32 *buf_32 = rx_buf;
536 for (k = 0; k < words; k++)
537 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
540 static int sh_msiof_spi_setup(struct spi_device *spi)
542 struct device_node *np = spi->controller->dev.of_node;
543 struct sh_msiof_spi_priv *p =
544 spi_controller_get_devdata(spi->controller);
549 * Use spi->controller_data for CS (same strategy as spi_gpio),
550 * if any. otherwise let HW control CS
552 spi->cs_gpio = (uintptr_t)spi->controller_data;
555 if (gpio_is_valid(spi->cs_gpio)) {
556 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
560 if (spi_controller_is_slave(p->ctlr))
563 if (p->native_cs_inited &&
564 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
567 /* Configure native chip select mode/polarity early */
568 clr = MDR1_SYNCMD_MASK;
569 set = MDR1_SYNCMD_SPI;
570 if (spi->mode & SPI_CS_HIGH)
571 clr |= BIT(MDR1_SYNCAC_SHIFT);
573 set |= BIT(MDR1_SYNCAC_SHIFT);
574 pm_runtime_get_sync(&p->pdev->dev);
575 tmp = sh_msiof_read(p, TMDR1) & ~clr;
576 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
577 tmp = sh_msiof_read(p, RMDR1) & ~clr;
578 sh_msiof_write(p, RMDR1, tmp | set);
579 pm_runtime_put(&p->pdev->dev);
580 p->native_cs_high = spi->mode & SPI_CS_HIGH;
581 p->native_cs_inited = true;
585 static int sh_msiof_prepare_message(struct spi_controller *ctlr,
586 struct spi_message *msg)
588 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
589 const struct spi_device *spi = msg->spi;
592 /* Configure pins before asserting CS */
593 if (gpio_is_valid(spi->cs_gpio)) {
595 cs_high = p->native_cs_high;
597 ss = spi->chip_select;
598 cs_high = !!(spi->mode & SPI_CS_HIGH);
600 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
601 !!(spi->mode & SPI_CPHA),
602 !!(spi->mode & SPI_3WIRE),
603 !!(spi->mode & SPI_LSB_FIRST), cs_high);
607 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
609 bool slave = spi_controller_is_slave(p->ctlr);
612 /* setup clock and rx/tx signals */
614 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
616 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
618 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
620 /* start by setting frame bit */
622 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
627 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
629 bool slave = spi_controller_is_slave(p->ctlr);
632 /* shut down frame, rx/tx and clock signals */
634 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
636 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
638 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
640 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
645 static int sh_msiof_slave_abort(struct spi_controller *ctlr)
647 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
649 p->slave_aborted = true;
651 complete(&p->done_txdma);
655 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
656 struct completion *x)
658 if (spi_controller_is_slave(p->ctlr)) {
659 if (wait_for_completion_interruptible(x) ||
661 dev_dbg(&p->pdev->dev, "interrupted\n");
665 if (!wait_for_completion_timeout(x, HZ)) {
666 dev_err(&p->pdev->dev, "timeout\n");
674 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
675 void (*tx_fifo)(struct sh_msiof_spi_priv *,
676 const void *, int, int),
677 void (*rx_fifo)(struct sh_msiof_spi_priv *,
679 const void *tx_buf, void *rx_buf,
685 /* limit maximum word transfer to rx/tx fifo size */
687 words = min_t(int, words, p->tx_fifo_size);
689 words = min_t(int, words, p->rx_fifo_size);
691 /* the fifo contents need shifting */
692 fifo_shift = 32 - bits;
694 /* default FIFO watermarks for PIO */
695 sh_msiof_write(p, FCTR, 0);
697 /* setup msiof transfer mode registers */
698 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
699 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
703 tx_fifo(p, tx_buf, words, fifo_shift);
705 reinit_completion(&p->done);
706 p->slave_aborted = false;
708 ret = sh_msiof_spi_start(p, rx_buf);
710 dev_err(&p->pdev->dev, "failed to start hardware\n");
714 /* wait for tx fifo to be emptied / rx fifo to be filled */
715 ret = sh_msiof_wait_for_completion(p, &p->done);
721 rx_fifo(p, rx_buf, words, fifo_shift);
723 /* clear status bits */
724 sh_msiof_reset_str(p);
726 ret = sh_msiof_spi_stop(p, rx_buf);
728 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
735 sh_msiof_reset_str(p);
736 sh_msiof_spi_stop(p, rx_buf);
738 sh_msiof_write(p, IER, 0);
742 static void sh_msiof_dma_complete(void *arg)
747 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
748 void *rx, unsigned int len)
751 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
755 /* First prepare and submit the DMA request(s), as this may fail */
757 ier_bits |= IER_RDREQE | IER_RDMAE;
758 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
759 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
760 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
764 desc_rx->callback = sh_msiof_dma_complete;
765 desc_rx->callback_param = &p->done;
766 cookie = dmaengine_submit(desc_rx);
767 if (dma_submit_error(cookie))
772 ier_bits |= IER_TDREQE | IER_TDMAE;
773 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
774 p->tx_dma_addr, len, DMA_TO_DEVICE);
775 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
776 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
777 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
783 desc_tx->callback = sh_msiof_dma_complete;
784 desc_tx->callback_param = &p->done_txdma;
785 cookie = dmaengine_submit(desc_tx);
786 if (dma_submit_error(cookie)) {
792 /* 1 stage FIFO watermarks for DMA */
793 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
795 /* setup msiof transfer mode registers (32-bit words) */
796 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
798 sh_msiof_write(p, IER, ier_bits);
800 reinit_completion(&p->done);
802 reinit_completion(&p->done_txdma);
803 p->slave_aborted = false;
807 dma_async_issue_pending(p->ctlr->dma_rx);
809 dma_async_issue_pending(p->ctlr->dma_tx);
811 ret = sh_msiof_spi_start(p, rx);
813 dev_err(&p->pdev->dev, "failed to start hardware\n");
818 /* wait for tx DMA completion */
819 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
825 /* wait for rx DMA completion */
826 ret = sh_msiof_wait_for_completion(p, &p->done);
830 sh_msiof_write(p, IER, 0);
832 /* wait for tx fifo to be emptied */
833 sh_msiof_write(p, IER, IER_TEOFE);
834 ret = sh_msiof_wait_for_completion(p, &p->done);
839 /* clear status bits */
840 sh_msiof_reset_str(p);
842 ret = sh_msiof_spi_stop(p, rx);
844 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
849 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
850 p->rx_dma_addr, len, DMA_FROM_DEVICE);
855 sh_msiof_reset_str(p);
856 sh_msiof_spi_stop(p, rx);
859 dmaengine_terminate_all(p->ctlr->dma_tx);
862 dmaengine_terminate_all(p->ctlr->dma_rx);
863 sh_msiof_write(p, IER, 0);
867 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
869 /* src or dst can be unaligned, but not both */
870 if ((unsigned long)src & 3) {
872 *dst++ = swab32(get_unaligned(src));
875 } else if ((unsigned long)dst & 3) {
877 put_unaligned(swab32(*src++), dst);
882 *dst++ = swab32(*src++);
886 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
888 /* src or dst can be unaligned, but not both */
889 if ((unsigned long)src & 3) {
891 *dst++ = swahw32(get_unaligned(src));
894 } else if ((unsigned long)dst & 3) {
896 put_unaligned(swahw32(*src++), dst);
901 *dst++ = swahw32(*src++);
905 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
907 memcpy(dst, src, words * 4);
910 static int sh_msiof_transfer_one(struct spi_controller *ctlr,
911 struct spi_device *spi,
912 struct spi_transfer *t)
914 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
915 void (*copy32)(u32 *, const u32 *, unsigned int);
916 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
917 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
918 const void *tx_buf = t->tx_buf;
919 void *rx_buf = t->rx_buf;
920 unsigned int len = t->len;
921 unsigned int bits = t->bits_per_word;
922 unsigned int bytes_per_word;
928 /* setup clocks (clock already enabled in chipselect()) */
929 if (!spi_controller_is_slave(p->ctlr))
930 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
932 while (ctlr->dma_tx && len > 15) {
934 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
935 * words, with byte resp. word swapping.
940 l = min(round_down(len, 4), p->tx_fifo_size * 4);
942 l = min(round_down(len, 4), p->rx_fifo_size * 4);
945 copy32 = copy_bswap32;
946 } else if (bits <= 16) {
947 copy32 = copy_wswap32;
949 copy32 = copy_plain32;
953 copy32(p->tx_dma_page, tx_buf, l / 4);
955 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
956 if (ret == -EAGAIN) {
957 dev_warn_once(&p->pdev->dev,
958 "DMA not available, falling back to PIO\n");
965 copy32(rx_buf, p->rx_dma_page, l / 4);
976 if (bits <= 8 && len > 15) {
983 /* setup bytes per word and fifo read/write functions */
986 tx_fifo = sh_msiof_spi_write_fifo_8;
987 rx_fifo = sh_msiof_spi_read_fifo_8;
988 } else if (bits <= 16) {
990 if ((unsigned long)tx_buf & 0x01)
991 tx_fifo = sh_msiof_spi_write_fifo_16u;
993 tx_fifo = sh_msiof_spi_write_fifo_16;
995 if ((unsigned long)rx_buf & 0x01)
996 rx_fifo = sh_msiof_spi_read_fifo_16u;
998 rx_fifo = sh_msiof_spi_read_fifo_16;
1001 if ((unsigned long)tx_buf & 0x03)
1002 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1004 tx_fifo = sh_msiof_spi_write_fifo_s32;
1006 if ((unsigned long)rx_buf & 0x03)
1007 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1009 rx_fifo = sh_msiof_spi_read_fifo_s32;
1012 if ((unsigned long)tx_buf & 0x03)
1013 tx_fifo = sh_msiof_spi_write_fifo_32u;
1015 tx_fifo = sh_msiof_spi_write_fifo_32;
1017 if ((unsigned long)rx_buf & 0x03)
1018 rx_fifo = sh_msiof_spi_read_fifo_32u;
1020 rx_fifo = sh_msiof_spi_read_fifo_32;
1023 /* transfer in fifo sized chunks */
1024 words = len / bytes_per_word;
1027 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1033 tx_buf += n * bytes_per_word;
1035 rx_buf += n * bytes_per_word;
1038 if (words == 0 && (len % bytes_per_word)) {
1039 words = len % bytes_per_word;
1040 bits = t->bits_per_word;
1042 tx_fifo = sh_msiof_spi_write_fifo_8;
1043 rx_fifo = sh_msiof_spi_read_fifo_8;
1050 static const struct sh_msiof_chipdata sh_data = {
1057 static const struct sh_msiof_chipdata rcar_gen2_data = {
1060 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1064 static const struct sh_msiof_chipdata rcar_gen3_data = {
1067 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1071 static const struct of_device_id sh_msiof_match[] = {
1072 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1073 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1074 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1075 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1076 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1077 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1078 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1079 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1080 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1081 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1082 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1083 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1086 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1089 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1091 struct sh_msiof_spi_info *info;
1092 struct device_node *np = dev->of_node;
1095 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1099 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1102 /* Parse the MSIOF properties */
1103 if (info->mode == MSIOF_SPI_MASTER)
1104 of_property_read_u32(np, "num-cs", &num_cs);
1105 of_property_read_u32(np, "renesas,tx-fifo-size",
1106 &info->tx_fifo_override);
1107 of_property_read_u32(np, "renesas,rx-fifo-size",
1108 &info->rx_fifo_override);
1109 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1110 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1112 info->num_chipselect = num_cs;
1117 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1123 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1125 struct device *dev = &p->pdev->dev;
1126 unsigned int used_ss_mask = 0;
1127 unsigned int cs_gpios = 0;
1128 unsigned int num_cs, i;
1131 ret = gpiod_count(dev, "cs");
1135 num_cs = max_t(unsigned int, ret, p->ctlr->num_chipselect);
1136 for (i = 0; i < num_cs; i++) {
1137 struct gpio_desc *gpiod;
1139 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1140 if (!IS_ERR(gpiod)) {
1145 if (PTR_ERR(gpiod) != -ENOENT)
1146 return PTR_ERR(gpiod);
1149 dev_err(dev, "Invalid native chip select %d\n", i);
1152 used_ss_mask |= BIT(i);
1154 p->unused_ss = ffz(used_ss_mask);
1155 if (cs_gpios && p->unused_ss >= MAX_SS) {
1156 dev_err(dev, "No unused native chip select available\n");
1162 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1163 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1165 dma_cap_mask_t mask;
1166 struct dma_chan *chan;
1167 struct dma_slave_config cfg;
1171 dma_cap_set(DMA_SLAVE, mask);
1173 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1174 (void *)(unsigned long)id, dev,
1175 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1177 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1181 memset(&cfg, 0, sizeof(cfg));
1182 cfg.direction = dir;
1183 if (dir == DMA_MEM_TO_DEV) {
1184 cfg.dst_addr = port_addr;
1185 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1187 cfg.src_addr = port_addr;
1188 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1191 ret = dmaengine_slave_config(chan, &cfg);
1193 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1194 dma_release_channel(chan);
1201 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1203 struct platform_device *pdev = p->pdev;
1204 struct device *dev = &pdev->dev;
1205 const struct sh_msiof_spi_info *info = p->info;
1206 unsigned int dma_tx_id, dma_rx_id;
1207 const struct resource *res;
1208 struct spi_controller *ctlr;
1209 struct device *tx_dev, *rx_dev;
1212 /* In the OF case we will get the slave IDs from the DT */
1215 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1216 dma_tx_id = info->dma_tx_id;
1217 dma_rx_id = info->dma_rx_id;
1219 /* The driver assumes no error */
1223 /* The DMA engine uses the second register set, if present */
1224 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1229 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1230 dma_tx_id, res->start + TFDR);
1234 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1235 dma_rx_id, res->start + RFDR);
1239 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1240 if (!p->tx_dma_page)
1243 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1244 if (!p->rx_dma_page)
1247 tx_dev = ctlr->dma_tx->device->dev;
1248 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1250 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1253 rx_dev = ctlr->dma_rx->device->dev;
1254 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1256 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1259 dev_info(dev, "DMA available");
1263 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1265 free_page((unsigned long)p->rx_dma_page);
1267 free_page((unsigned long)p->tx_dma_page);
1269 dma_release_channel(ctlr->dma_rx);
1271 dma_release_channel(ctlr->dma_tx);
1272 ctlr->dma_tx = NULL;
1276 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1278 struct spi_controller *ctlr = p->ctlr;
1283 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1285 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1287 free_page((unsigned long)p->rx_dma_page);
1288 free_page((unsigned long)p->tx_dma_page);
1289 dma_release_channel(ctlr->dma_rx);
1290 dma_release_channel(ctlr->dma_tx);
1293 static int sh_msiof_spi_probe(struct platform_device *pdev)
1296 struct spi_controller *ctlr;
1297 const struct sh_msiof_chipdata *chipdata;
1298 struct sh_msiof_spi_info *info;
1299 struct sh_msiof_spi_priv *p;
1303 chipdata = of_device_get_match_data(&pdev->dev);
1305 info = sh_msiof_spi_parse_dt(&pdev->dev);
1307 chipdata = (const void *)pdev->id_entry->driver_data;
1308 info = dev_get_platdata(&pdev->dev);
1312 dev_err(&pdev->dev, "failed to obtain device info\n");
1316 if (info->mode == MSIOF_SPI_SLAVE)
1317 ctlr = spi_alloc_slave(&pdev->dev,
1318 sizeof(struct sh_msiof_spi_priv));
1320 ctlr = spi_alloc_master(&pdev->dev,
1321 sizeof(struct sh_msiof_spi_priv));
1325 p = spi_controller_get_devdata(ctlr);
1327 platform_set_drvdata(pdev, p);
1330 p->min_div_pow = chipdata->min_div_pow;
1332 init_completion(&p->done);
1333 init_completion(&p->done_txdma);
1335 p->clk = devm_clk_get(&pdev->dev, NULL);
1336 if (IS_ERR(p->clk)) {
1337 dev_err(&pdev->dev, "cannot get clock\n");
1338 ret = PTR_ERR(p->clk);
1342 i = platform_get_irq(pdev, 0);
1344 dev_err(&pdev->dev, "cannot get IRQ\n");
1349 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1350 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1351 if (IS_ERR(p->mapbase)) {
1352 ret = PTR_ERR(p->mapbase);
1356 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1357 dev_name(&pdev->dev), p);
1359 dev_err(&pdev->dev, "unable to request irq\n");
1364 pm_runtime_enable(&pdev->dev);
1366 /* Platform data may override FIFO sizes */
1367 p->tx_fifo_size = chipdata->tx_fifo_size;
1368 p->rx_fifo_size = chipdata->rx_fifo_size;
1369 if (p->info->tx_fifo_override)
1370 p->tx_fifo_size = p->info->tx_fifo_override;
1371 if (p->info->rx_fifo_override)
1372 p->rx_fifo_size = p->info->rx_fifo_override;
1374 /* Setup GPIO chip selects */
1375 ctlr->num_chipselect = p->info->num_chipselect;
1376 ret = sh_msiof_get_cs_gpios(p);
1380 /* init controller code */
1381 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1382 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1383 ctlr->flags = chipdata->ctlr_flags;
1384 ctlr->bus_num = pdev->id;
1385 ctlr->dev.of_node = pdev->dev.of_node;
1386 ctlr->setup = sh_msiof_spi_setup;
1387 ctlr->prepare_message = sh_msiof_prepare_message;
1388 ctlr->slave_abort = sh_msiof_slave_abort;
1389 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1390 ctlr->auto_runtime_pm = true;
1391 ctlr->transfer_one = sh_msiof_transfer_one;
1393 ret = sh_msiof_request_dma(p);
1395 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1397 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1399 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1406 sh_msiof_release_dma(p);
1407 pm_runtime_disable(&pdev->dev);
1409 spi_controller_put(ctlr);
1413 static int sh_msiof_spi_remove(struct platform_device *pdev)
1415 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1417 sh_msiof_release_dma(p);
1418 pm_runtime_disable(&pdev->dev);
1422 static const struct platform_device_id spi_driver_ids[] = {
1423 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1426 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1428 #ifdef CONFIG_PM_SLEEP
1429 static int sh_msiof_spi_suspend(struct device *dev)
1431 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1433 return spi_controller_suspend(p->ctlr);
1436 static int sh_msiof_spi_resume(struct device *dev)
1438 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1440 return spi_controller_resume(p->ctlr);
1443 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1444 sh_msiof_spi_resume);
1445 #define DEV_PM_OPS &sh_msiof_spi_pm_ops
1447 #define DEV_PM_OPS NULL
1448 #endif /* CONFIG_PM_SLEEP */
1450 static struct platform_driver sh_msiof_spi_drv = {
1451 .probe = sh_msiof_spi_probe,
1452 .remove = sh_msiof_spi_remove,
1453 .id_table = spi_driver_ids,
1455 .name = "spi_sh_msiof",
1457 .of_match_table = of_match_ptr(sh_msiof_match),
1460 module_platform_driver(sh_msiof_spi_drv);
1462 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
1463 MODULE_AUTHOR("Magnus Damm");
1464 MODULE_LICENSE("GPL v2");
1465 MODULE_ALIAS("platform:spi_sh_msiof");