drivers/spi/spi-s3c64xx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
   4 //      Jaswinder Singh <jassi.brar@samsung.com>
   5
   6 #include <linux/init.h>
   7 #include <linux/module.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/delay.h>
  10 #include <linux/clk.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/gpio.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19
  20 #include <linux/platform_data/spi-s3c64xx.h>
  21
  22 #define MAX_SPI_PORTS           6
  23 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  24 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
  25 #define AUTOSUSPEND_TIMEOUT     2000
  26
  27 /* Registers and bit-fields */
  28
  29 #define S3C64XX_SPI_CH_CFG              0x00
  30 #define S3C64XX_SPI_CLK_CFG             0x04
  31 #define S3C64XX_SPI_MODE_CFG    0x08
  32 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  33 #define S3C64XX_SPI_INT_EN              0x10
  34 #define S3C64XX_SPI_STATUS              0x14
  35 #define S3C64XX_SPI_TX_DATA             0x18
  36 #define S3C64XX_SPI_RX_DATA             0x1C
  37 #define S3C64XX_SPI_PACKET_CNT  0x20
  38 #define S3C64XX_SPI_PENDING_CLR 0x24
  39 #define S3C64XX_SPI_SWAP_CFG    0x28
  40 #define S3C64XX_SPI_FB_CLK              0x2C
  41
  42 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  43 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  44 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  45 #define S3C64XX_SPI_CPOL_L              (1<<3)
  46 #define S3C64XX_SPI_CPHA_B              (1<<2)
  47 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  48 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  49
  50 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  51 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  52 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  53 #define S3C64XX_SPI_PSR_MASK            0xff
  54
  55 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  56 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  57 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  58 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  59 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  60 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  61 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  62 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  63 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  64 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  65 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  66
  67 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  68 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  69 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
  70
  71 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  72 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  73 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  74 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  75 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  76 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  77 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  78
  79 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  80 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  81 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  82 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  83 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  84 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  85
  86 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  87
  88 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  89 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
  90 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
  91 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
  92 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
  93
  94 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
  95 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
  96 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
  97 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
  98 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
  99 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 100 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 101 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 102
 103 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 104
 105 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 106 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 107                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 108 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 109 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 110                                         FIFO_LVL_MASK(i))
 111
 112 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 113 #define S3C64XX_SPI_TRAILCNT_OFF        19
 114
 115 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 116
 117 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 118 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 119
 120 #define RXBUSY    (1<<2)
 121 #define TXBUSY    (1<<3)
 122
 123 struct s3c64xx_spi_dma_data {
 124         struct dma_chan *ch;
 125         enum dma_transfer_direction direction;
 126 };
 127
 128 /**
 129  * struct s3c64xx_spi_info - SPI Controller hardware info
 130  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 131  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 132  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 133  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 134  * @clk_from_cmu: True, if the controller does not include a clock mux and
 135  *      prescaler unit.
 136  *
 137  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 138  * differ in some aspects such as the size of the fifo and spi bus clock
 139  * setup. Such differences are specified to the driver using this structure
 140  * which is provided as driver data to the driver.
 141  */
 142 struct s3c64xx_spi_port_config {
 143         int     fifo_lvl_mask[MAX_SPI_PORTS];
 144         int     rx_lvl_offset;
 145         int     tx_st_done;
 146         int     quirks;
 147         bool    high_speed;
 148         bool    clk_from_cmu;
 149         bool    clk_ioclk;
 150 };
 151
 152 /**
 153  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 154  * @clk: Pointer to the spi clock.
 155  * @src_clk: Pointer to the clock used to generate SPI signals.
 156  * @ioclk: Pointer to the i/o clock between master and slave
 157  * @master: Pointer to the SPI Protocol master.
 158  * @cntrlr_info: Platform specific data for the controller this driver manages.
 159  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 160  * @lock: Controller specific lock.
 161  * @state: Set of FLAGS to indicate status.
 162  * @rx_dmach: Controller's DMA channel for Rx.
 163  * @tx_dmach: Controller's DMA channel for Tx.
 164  * @sfr_start: BUS address of SPI controller regs.
 165  * @regs: Pointer to ioremap'ed controller registers.
 166  * @irq: interrupt
 167  * @xfer_completion: To indicate completion of xfer task.
 168  * @cur_mode: Stores the active configuration of the controller.
 169  * @cur_bpw: Stores the active bits per word settings.
 170  * @cur_speed: Stores the active xfer clock speed.
 171  */
 172 struct s3c64xx_spi_driver_data {
 173         void __iomem                    *regs;
 174         struct clk                      *clk;
 175         struct clk                      *src_clk;
 176         struct clk                      *ioclk;
 177         struct platform_device          *pdev;
 178         struct spi_master               *master;
 179         struct s3c64xx_spi_info  *cntrlr_info;
 180         struct spi_device               *tgl_spi;
 181         spinlock_t                      lock;
 182         unsigned long                   sfr_start;
 183         struct completion               xfer_completion;
 184         unsigned                        state;
 185         unsigned                        cur_mode, cur_bpw;
 186         unsigned                        cur_speed;
 187         struct s3c64xx_spi_dma_data     rx_dma;
 188         struct s3c64xx_spi_dma_data     tx_dma;
 189         struct s3c64xx_spi_port_config  *port_conf;
 190         unsigned int                    port_id;
 191 };
 192
 193 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 194 {
 195         void __iomem *regs = sdd->regs;
 196         unsigned long loops;
 197         u32 val;
 198
 199         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 200
 201         val = readl(regs + S3C64XX_SPI_CH_CFG);
 202         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 203         writel(val, regs + S3C64XX_SPI_CH_CFG);
 204
 205         val = readl(regs + S3C64XX_SPI_CH_CFG);
 206         val |= S3C64XX_SPI_CH_SW_RST;
 207         val &= ~S3C64XX_SPI_CH_HS_EN;
 208         writel(val, regs + S3C64XX_SPI_CH_CFG);
 209
 210         /* Flush TxFIFO*/
 211         loops = msecs_to_loops(1);
 212         do {
 213                 val = readl(regs + S3C64XX_SPI_STATUS);
 214         } while (TX_FIFO_LVL(val, sdd) && loops--);
 215
 216         if (loops == 0)
 217                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 218
 219         /* Flush RxFIFO*/
 220         loops = msecs_to_loops(1);
 221         do {
 222                 val = readl(regs + S3C64XX_SPI_STATUS);
 223                 if (RX_FIFO_LVL(val, sdd))
 224                         readl(regs + S3C64XX_SPI_RX_DATA);
 225                 else
 226                         break;
 227         } while (loops--);
 228
 229         if (loops == 0)
 230                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 231
 232         val = readl(regs + S3C64XX_SPI_CH_CFG);
 233         val &= ~S3C64XX_SPI_CH_SW_RST;
 234         writel(val, regs + S3C64XX_SPI_CH_CFG);
 235
 236         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 237         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 238         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 239 }
 240
 241 static void s3c64xx_spi_dmacb(void *data)
 242 {
 243         struct s3c64xx_spi_driver_data *sdd;
 244         struct s3c64xx_spi_dma_data *dma = data;
 245         unsigned long flags;
 246
 247         if (dma->direction == DMA_DEV_TO_MEM)
 248                 sdd = container_of(data,
 249                         struct s3c64xx_spi_driver_data, rx_dma);
 250         else
 251                 sdd = container_of(data,
 252                         struct s3c64xx_spi_driver_data, tx_dma);
 253
 254         spin_lock_irqsave(&sdd->lock, flags);
 255
 256         if (dma->direction == DMA_DEV_TO_MEM) {
 257                 sdd->state &= ~RXBUSY;
 258                 if (!(sdd->state & TXBUSY))
 259                         complete(&sdd->xfer_completion);
 260         } else {
 261                 sdd->state &= ~TXBUSY;
 262                 if (!(sdd->state & RXBUSY))
 263                         complete(&sdd->xfer_completion);
 264         }
 265
 266         spin_unlock_irqrestore(&sdd->lock, flags);
 267 }
 268
 269 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 270                         struct sg_table *sgt)
 271 {
 272         struct s3c64xx_spi_driver_data *sdd;
 273         struct dma_slave_config config;
 274         struct dma_async_tx_descriptor *desc;
 275
 276         memset(&config, 0, sizeof(config));
 277
 278         if (dma->direction == DMA_DEV_TO_MEM) {
 279                 sdd = container_of((void *)dma,
 280                         struct s3c64xx_spi_driver_data, rx_dma);
 281                 config.direction = dma->direction;
 282                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 283                 config.src_addr_width = sdd->cur_bpw / 8;
 284                 config.src_maxburst = 1;
 285                 dmaengine_slave_config(dma->ch, &config);
 286         } else {
 287                 sdd = container_of((void *)dma,
 288                         struct s3c64xx_spi_driver_data, tx_dma);
 289                 config.direction = dma->direction;
 290                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 291                 config.dst_addr_width = sdd->cur_bpw / 8;
 292                 config.dst_maxburst = 1;
 293                 dmaengine_slave_config(dma->ch, &config);
 294         }
 295
 296         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 297                                        dma->direction, DMA_PREP_INTERRUPT);
 298
 299         desc->callback = s3c64xx_spi_dmacb;
 300         desc->callback_param = dma;
 301
 302         dmaengine_submit(desc);
 303         dma_async_issue_pending(dma->ch);
 304 }
 305
 306 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
 307 {
 308         struct s3c64xx_spi_driver_data *sdd =
 309                                         spi_master_get_devdata(spi->master);
 310
 311         if (sdd->cntrlr_info->no_cs)
 312                 return;
 313
 314         if (enable) {
 315                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
 316                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 317                 } else {
 318                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 319
 320                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
 321                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
 322                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 323                 }
 324         } else {
 325                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 326                         writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 327                                sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 328         }
 329 }
 330
 331 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 332 {
 333         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 334
 335         if (is_polling(sdd))
 336                 return 0;
 337
 338         spi->dma_rx = sdd->rx_dma.ch;
 339         spi->dma_tx = sdd->tx_dma.ch;
 340
 341         return 0;
 342 }
 343
 344 static bool s3c64xx_spi_can_dma(struct spi_master *master,
 345                                 struct spi_device *spi,
 346                                 struct spi_transfer *xfer)
 347 {
 348         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 349
 350         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
 351 }
 352
 353 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 354                                 struct spi_device *spi,
 355                                 struct spi_transfer *xfer, int dma_mode)
 356 {
 357         void __iomem *regs = sdd->regs;
 358         u32 modecfg, chcfg;
 359
 360         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 361         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 362
 363         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 364         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 365
 366         if (dma_mode) {
 367                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 368         } else {
 369                 /* Always shift in data in FIFO, even if xfer is Tx only,
 370                  * this helps setting PCKT_CNT value for generating clocks
 371                  * as exactly needed.
 372                  */
 373                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 374                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 375                                         | S3C64XX_SPI_PACKET_CNT_EN,
 376                                         regs + S3C64XX_SPI_PACKET_CNT);
 377         }
 378
 379         if (xfer->tx_buf != NULL) {
 380                 sdd->state |= TXBUSY;
 381                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 382                 if (dma_mode) {
 383                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 384                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 385                 } else {
 386                         switch (sdd->cur_bpw) {
 387                         case 32:
 388                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 389                                         xfer->tx_buf, xfer->len / 4);
 390                                 break;
 391                         case 16:
 392                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 393                                         xfer->tx_buf, xfer->len / 2);
 394                                 break;
 395                         default:
 396                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 397                                         xfer->tx_buf, xfer->len);
 398                                 break;
 399                         }
 400                 }
 401         }
 402
 403         if (xfer->rx_buf != NULL) {
 404                 sdd->state |= RXBUSY;
 405
 406                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 407                                         && !(sdd->cur_mode & SPI_CPHA))
 408                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 409
 410                 if (dma_mode) {
 411                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 412                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 413                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 414                                         | S3C64XX_SPI_PACKET_CNT_EN,
 415                                         regs + S3C64XX_SPI_PACKET_CNT);
 416                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 417                 }
 418         }
 419
 420         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 421         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 422 }
 423
 424 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 425                                         int timeout_ms)
 426 {
 427         void __iomem *regs = sdd->regs;
 428         unsigned long val = 1;
 429         u32 status;
 430
 431         /* max fifo depth available */
 432         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 433
 434         if (timeout_ms)
 435                 val = msecs_to_loops(timeout_ms);
 436
 437         do {
 438                 status = readl(regs + S3C64XX_SPI_STATUS);
 439         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 440
 441         /* return the actual received data length */
 442         return RX_FIFO_LVL(status, sdd);
 443 }
 444
 445 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
 446                         struct spi_transfer *xfer)
 447 {
 448         void __iomem *regs = sdd->regs;
 449         unsigned long val;
 450         u32 status;
 451         int ms;
 452
 453         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 454         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 455         ms += 10; /* some tolerance */
 456
 457         val = msecs_to_jiffies(ms) + 10;
 458         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 459
 460         /*
 461          * If the previous xfer was completed within timeout, then
 462          * proceed further else return -EIO.
 463          * DmaTx returns after simply writing data in the FIFO,
 464          * w/o waiting for real transmission on the bus to finish.
 465          * DmaRx returns only after Dma read data from FIFO which
 466          * needs bus transmission to finish, so we don't worry if
 467          * Xfer involved Rx(with or without Tx).
 468          */
 469         if (val && !xfer->rx_buf) {
 470                 val = msecs_to_loops(10);
 471                 status = readl(regs + S3C64XX_SPI_STATUS);
 472                 while ((TX_FIFO_LVL(status, sdd)
 473                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 474                        && --val) {
 475                         cpu_relax();
 476                         status = readl(regs + S3C64XX_SPI_STATUS);
 477                 }
 478
 479         }
 480
 481         /* If timed out while checking rx/tx status return error */
 482         if (!val)
 483                 return -EIO;
 484
 485         return 0;
 486 }
 487
 488 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
 489                         struct spi_transfer *xfer)
 490 {
 491         void __iomem *regs = sdd->regs;
 492         unsigned long val;
 493         u32 status;
 494         int loops;
 495         u32 cpy_len;
 496         u8 *buf;
 497         int ms;
 498
 499         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 500         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 501         ms += 10; /* some tolerance */
 502
 503         val = msecs_to_loops(ms);
 504         do {
 505                 status = readl(regs + S3C64XX_SPI_STATUS);
 506         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 507
 508
 509         /* If it was only Tx */
 510         if (!xfer->rx_buf) {
 511                 sdd->state &= ~TXBUSY;
 512                 return 0;
 513         }
 514
 515         /*
 516          * If the receive length is bigger than the controller fifo
 517          * size, calculate the loops and read the fifo as many times.
 518          * loops = length / max fifo size (calculated by using the
 519          * fifo mask).
 520          * For any size less than the fifo size the below code is
 521          * executed atleast once.
 522          */
 523         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 524         buf = xfer->rx_buf;
 525         do {
 526                 /* wait for data to be received in the fifo */
 527                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 528                                                        (loops ? ms : 0));
 529
 530                 switch (sdd->cur_bpw) {
 531                 case 32:
 532                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 533                                      buf, cpy_len / 4);
 534                         break;
 535                 case 16:
 536                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 537                                      buf, cpy_len / 2);
 538                         break;
 539                 default:
 540                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 541                                     buf, cpy_len);
 542                         break;
 543                 }
 544
 545                 buf = buf + cpy_len;
 546         } while (loops--);
 547         sdd->state &= ~RXBUSY;
 548
 549         return 0;
 550 }
 551
 552 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 553 {
 554         void __iomem *regs = sdd->regs;
 555         u32 val;
 556
 557         /* Disable Clock */
 558         if (!sdd->port_conf->clk_from_cmu) {
 559                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 560                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 561                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 562         }
 563
 564         /* Set Polarity and Phase */
 565         val = readl(regs + S3C64XX_SPI_CH_CFG);
 566         val &= ~(S3C64XX_SPI_CH_SLAVE |
 567                         S3C64XX_SPI_CPOL_L |
 568                         S3C64XX_SPI_CPHA_B);
 569
 570         if (sdd->cur_mode & SPI_CPOL)
 571                 val |= S3C64XX_SPI_CPOL_L;
 572
 573         if (sdd->cur_mode & SPI_CPHA)
 574                 val |= S3C64XX_SPI_CPHA_B;
 575
 576         writel(val, regs + S3C64XX_SPI_CH_CFG);
 577
 578         /* Set Channel & DMA Mode */
 579         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 580         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 581                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 582
 583         switch (sdd->cur_bpw) {
 584         case 32:
 585                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 586                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 587                 break;
 588         case 16:
 589                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 590                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 591                 break;
 592         default:
 593                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 594                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 595                 break;
 596         }
 597
 598         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 599
 600         if (sdd->port_conf->clk_from_cmu) {
 601                 /* The src_clk clock is divided internally by 2 */
 602                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 603         } else {
 604                 /* Configure Clock */
 605                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 606                 val &= ~S3C64XX_SPI_PSR_MASK;
 607                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 608                                 & S3C64XX_SPI_PSR_MASK);
 609                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 610
 611                 /* Enable Clock */
 612                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 613                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 614                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 615         }
 616 }
 617
 618 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 619
 620 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 621                                        struct spi_message *msg)
 622 {
 623         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 624         struct spi_device *spi = msg->spi;
 625         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 626
 627         /* Configure feedback delay */
 628         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 629
 630         return 0;
 631 }
 632
 633 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 634                                     struct spi_device *spi,
 635                                     struct spi_transfer *xfer)
 636 {
 637         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 638         int status;
 639         u32 speed;
 640         u8 bpw;
 641         unsigned long flags;
 642         int use_dma;
 643
 644         reinit_completion(&sdd->xfer_completion);
 645
 646         /* Only BPW and Speed may change across transfers */
 647         bpw = xfer->bits_per_word;
 648         speed = xfer->speed_hz;
 649
 650         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 651                 sdd->cur_bpw = bpw;
 652                 sdd->cur_speed = speed;
 653                 sdd->cur_mode = spi->mode;
 654                 s3c64xx_spi_config(sdd);
 655         }
 656
 657         /* Polling method for xfers not bigger than FIFO capacity */
 658         use_dma = 0;
 659         if (!is_polling(sdd) &&
 660             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 661              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 662                 use_dma = 1;
 663
 664         spin_lock_irqsave(&sdd->lock, flags);
 665
 666         /* Pending only which is to be done */
 667         sdd->state &= ~RXBUSY;
 668         sdd->state &= ~TXBUSY;
 669
 670         enable_datapath(sdd, spi, xfer, use_dma);
 671
 672         /* Start the signals */
 673         s3c64xx_spi_set_cs(spi, true);
 674
 675         spin_unlock_irqrestore(&sdd->lock, flags);
 676
 677         if (use_dma)
 678                 status = wait_for_dma(sdd, xfer);
 679         else
 680                 status = wait_for_pio(sdd, xfer);
 681
 682         if (status) {
 683                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 684                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 685                         (sdd->state & RXBUSY) ? 'f' : 'p',
 686                         (sdd->state & TXBUSY) ? 'f' : 'p',
 687                         xfer->len);
 688
 689                 if (use_dma) {
 690                         if (xfer->tx_buf != NULL
 691                             && (sdd->state & TXBUSY))
 692                                 dmaengine_terminate_all(sdd->tx_dma.ch);
 693                         if (xfer->rx_buf != NULL
 694                             && (sdd->state & RXBUSY))
 695                                 dmaengine_terminate_all(sdd->rx_dma.ch);
 696                 }
 697         } else {
 698                 flush_fifo(sdd);
 699         }
 700
 701         return status;
 702 }
 703
 704 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 705                                 struct spi_device *spi)
 706 {
 707         struct s3c64xx_spi_csinfo *cs;
 708         struct device_node *slave_np, *data_np = NULL;
 709         u32 fb_delay = 0;
 710
 711         slave_np = spi->dev.of_node;
 712         if (!slave_np) {
 713                 dev_err(&spi->dev, "device node not found\n");
 714                 return ERR_PTR(-EINVAL);
 715         }
 716
 717         data_np = of_get_child_by_name(slave_np, "controller-data");
 718         if (!data_np) {
 719                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 720                 return ERR_PTR(-EINVAL);
 721         }
 722
 723         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 724         if (!cs) {
 725                 of_node_put(data_np);
 726                 return ERR_PTR(-ENOMEM);
 727         }
 728
 729         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 730         cs->fb_delay = fb_delay;
 731         of_node_put(data_np);
 732         return cs;
 733 }
 734
 735 /*
 736  * Here we only check the validity of requested configuration
 737  * and save the configuration in a local data-structure.
 738  * The controller is actually configured only just before we
 739  * get a message to transfer.
 740  */
 741 static int s3c64xx_spi_setup(struct spi_device *spi)
 742 {
 743         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 744         struct s3c64xx_spi_driver_data *sdd;
 745         int err;
 746
 747         sdd = spi_master_get_devdata(spi->master);
 748         if (spi->dev.of_node) {
 749                 cs = s3c64xx_get_slave_ctrldata(spi);
 750                 spi->controller_data = cs;
 751         } else if (cs) {
 752                 /* On non-DT platforms the SPI core will set spi->cs_gpio
 753                  * to -ENOENT. The GPIO pin used to drive the chip select
 754                  * is defined by using platform data so spi->cs_gpio value
 755                  * has to be override to have the proper GPIO pin number.
 756                  */
 757                 spi->cs_gpio = cs->line;
 758         }
 759
 760         if (IS_ERR_OR_NULL(cs)) {
 761                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 762                 return -ENODEV;
 763         }
 764
 765         if (!spi_get_ctldata(spi)) {
 766                 if (gpio_is_valid(spi->cs_gpio)) {
 767                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
 768                                                dev_name(&spi->dev));
 769                         if (err) {
 770                                 dev_err(&spi->dev,
 771                                         "Failed to get /CS gpio [%d]: %d\n",
 772                                         spi->cs_gpio, err);
 773                                 goto err_gpio_req;
 774                         }
 775                 }
 776
 777                 spi_set_ctldata(spi, cs);
 778         }
 779
 780         pm_runtime_get_sync(&sdd->pdev->dev);
 781
 782         /* Check if we can provide the requested rate */
 783         if (!sdd->port_conf->clk_from_cmu) {
 784                 u32 psr, speed;
 785
 786                 /* Max possible */
 787                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 788
 789                 if (spi->max_speed_hz > speed)
 790                         spi->max_speed_hz = speed;
 791
 792                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 793                 psr &= S3C64XX_SPI_PSR_MASK;
 794                 if (psr == S3C64XX_SPI_PSR_MASK)
 795                         psr--;
 796
 797                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 798                 if (spi->max_speed_hz < speed) {
 799                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 800                                 psr++;
 801                         } else {
 802                                 err = -EINVAL;
 803                                 goto setup_exit;
 804                         }
 805                 }
 806
 807                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 808                 if (spi->max_speed_hz >= speed) {
 809                         spi->max_speed_hz = speed;
 810                 } else {
 811                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 812                                 spi->max_speed_hz);
 813                         err = -EINVAL;
 814                         goto setup_exit;
 815                 }
 816         }
 817
 818         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 819         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 820         s3c64xx_spi_set_cs(spi, false);
 821
 822         return 0;
 823
 824 setup_exit:
 825         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 826         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 827         /* setup() returns with device de-selected */
 828         s3c64xx_spi_set_cs(spi, false);
 829
 830         if (gpio_is_valid(spi->cs_gpio))
 831                 gpio_free(spi->cs_gpio);
 832         spi_set_ctldata(spi, NULL);
 833
 834 err_gpio_req:
 835         if (spi->dev.of_node)
 836                 kfree(cs);
 837
 838         return err;
 839 }
 840
 841 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 842 {
 843         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 844
 845         if (gpio_is_valid(spi->cs_gpio)) {
 846                 gpio_free(spi->cs_gpio);
 847                 if (spi->dev.of_node)
 848                         kfree(cs);
 849                 else {
 850                         /* On non-DT platforms, the SPI core sets
 851                          * spi->cs_gpio to -ENOENT and .setup()
 852                          * overrides it with the GPIO pin value
 853                          * passed using platform data.
 854                          */
 855                         spi->cs_gpio = -ENOENT;
 856                 }
 857         }
 858
 859         spi_set_ctldata(spi, NULL);
 860 }
 861
 862 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 863 {
 864         struct s3c64xx_spi_driver_data *sdd = data;
 865         struct spi_master *spi = sdd->master;
 866         unsigned int val, clr = 0;
 867
 868         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 869
 870         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
 871                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
 872                 dev_err(&spi->dev, "RX overrun\n");
 873         }
 874         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
 875                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
 876                 dev_err(&spi->dev, "RX underrun\n");
 877         }
 878         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
 879                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
 880                 dev_err(&spi->dev, "TX overrun\n");
 881         }
 882         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
 883                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 884                 dev_err(&spi->dev, "TX underrun\n");
 885         }
 886
 887         /* Clear the pending irq by setting and then clearing it */
 888         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 889         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 890
 891         return IRQ_HANDLED;
 892 }
 893
 894 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 895 {
 896         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 897         void __iomem *regs = sdd->regs;
 898         unsigned int val;
 899
 900         sdd->cur_speed = 0;
 901
 902         if (sci->no_cs)
 903                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 904         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 905                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 906
 907         /* Disable Interrupts - we use Polling if not DMA mode */
 908         writel(0, regs + S3C64XX_SPI_INT_EN);
 909
 910         if (!sdd->port_conf->clk_from_cmu)
 911                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 912                                 regs + S3C64XX_SPI_CLK_CFG);
 913         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 914         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 915
 916         /* Clear any irq pending bits, should set and clear the bits */
 917         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
 918                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
 919                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
 920                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 921         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
 922         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
 923
 924         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 925
 926         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 927         val &= ~S3C64XX_SPI_MODE_4BURST;
 928         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 929         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 930         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 931
 932         flush_fifo(sdd);
 933 }
 934
 935 #ifdef CONFIG_OF
 936 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
 937 {
 938         struct s3c64xx_spi_info *sci;
 939         u32 temp;
 940
 941         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
 942         if (!sci)
 943                 return ERR_PTR(-ENOMEM);
 944
 945         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
 946                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
 947                 sci->src_clk_nr = 0;
 948         } else {
 949                 sci->src_clk_nr = temp;
 950         }
 951
 952         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
 953                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
 954                 sci->num_cs = 1;
 955         } else {
 956                 sci->num_cs = temp;
 957         }
 958
 959         sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
 960
 961         return sci;
 962 }
 963 #else
 964 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
 965 {
 966         return dev_get_platdata(dev);
 967 }
 968 #endif
 969
 970 static const struct of_device_id s3c64xx_spi_dt_match[];
 971
 972 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
 973                                                 struct platform_device *pdev)
 974 {
 975 #ifdef CONFIG_OF
 976         if (pdev->dev.of_node) {
 977                 const struct of_device_id *match;
 978                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
 979                 return (struct s3c64xx_spi_port_config *)match->data;
 980         }
 981 #endif
 982         return (struct s3c64xx_spi_port_config *)
 983                          platform_get_device_id(pdev)->driver_data;
 984 }
 985
 986 static int s3c64xx_spi_probe(struct platform_device *pdev)
 987 {
 988         struct resource *mem_res;
 989         struct s3c64xx_spi_driver_data *sdd;
 990         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
 991         struct spi_master *master;
 992         int ret, irq;
 993         char clk_name[16];
 994
 995         if (!sci && pdev->dev.of_node) {
 996                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
 997                 if (IS_ERR(sci))
 998                         return PTR_ERR(sci);
 999         }
1000
1001         if (!sci) {
1002                 dev_err(&pdev->dev, "platform_data missing!\n");
1003                 return -ENODEV;
1004         }
1005
1006         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1007         if (mem_res == NULL) {
1008                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1009                 return -ENXIO;
1010         }
1011
1012         irq = platform_get_irq(pdev, 0);
1013         if (irq < 0) {
1014                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1015                 return irq;
1016         }
1017
1018         master = spi_alloc_master(&pdev->dev,
1019                                 sizeof(struct s3c64xx_spi_driver_data));
1020         if (master == NULL) {
1021                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1022                 return -ENOMEM;
1023         }
1024
1025         platform_set_drvdata(pdev, master);
1026
1027         sdd = spi_master_get_devdata(master);
1028         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1029         sdd->master = master;
1030         sdd->cntrlr_info = sci;
1031         sdd->pdev = pdev;
1032         sdd->sfr_start = mem_res->start;
1033         if (pdev->dev.of_node) {
1034                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1035                 if (ret < 0) {
1036                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1037                                 ret);
1038                         goto err_deref_master;
1039                 }
1040                 sdd->port_id = ret;
1041         } else {
1042                 sdd->port_id = pdev->id;
1043         }
1044
1045         sdd->cur_bpw = 8;
1046
1047         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1048         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1049
1050         master->dev.of_node = pdev->dev.of_node;
1051         master->bus_num = sdd->port_id;
1052         master->setup = s3c64xx_spi_setup;
1053         master->cleanup = s3c64xx_spi_cleanup;
1054         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1055         master->prepare_message = s3c64xx_spi_prepare_message;
1056         master->transfer_one = s3c64xx_spi_transfer_one;
1057         master->num_chipselect = sci->num_cs;
1058         master->dma_alignment = 8;
1059         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1060                                         SPI_BPW_MASK(8);
1061         /* the spi->mode bits understood by this driver: */
1062         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1063         master->auto_runtime_pm = true;
1064         if (!is_polling(sdd))
1065                 master->can_dma = s3c64xx_spi_can_dma;
1066
1067         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1068         if (IS_ERR(sdd->regs)) {
1069                 ret = PTR_ERR(sdd->regs);
1070                 goto err_deref_master;
1071         }
1072
1073         if (sci->cfg_gpio && sci->cfg_gpio()) {
1074                 dev_err(&pdev->dev, "Unable to config gpio\n");
1075                 ret = -EBUSY;
1076                 goto err_deref_master;
1077         }
1078
1079         /* Setup clocks */
1080         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1081         if (IS_ERR(sdd->clk)) {
1082                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1083                 ret = PTR_ERR(sdd->clk);
1084                 goto err_deref_master;
1085         }
1086
1087         ret = clk_prepare_enable(sdd->clk);
1088         if (ret) {
1089                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1090                 goto err_deref_master;
1091         }
1092
1093         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1094         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1095         if (IS_ERR(sdd->src_clk)) {
1096                 dev_err(&pdev->dev,
1097                         "Unable to acquire clock '%s'\n", clk_name);
1098                 ret = PTR_ERR(sdd->src_clk);
1099                 goto err_disable_clk;
1100         }
1101
1102         ret = clk_prepare_enable(sdd->src_clk);
1103         if (ret) {
1104                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1105                 goto err_disable_clk;
1106         }
1107
1108         if (sdd->port_conf->clk_ioclk) {
1109                 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1110                 if (IS_ERR(sdd->ioclk)) {
1111                         dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1112                         ret = PTR_ERR(sdd->ioclk);
1113                         goto err_disable_src_clk;
1114                 }
1115
1116                 ret = clk_prepare_enable(sdd->ioclk);
1117                 if (ret) {
1118                         dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1119                         goto err_disable_src_clk;
1120                 }
1121         }
1122
1123         if (!is_polling(sdd)) {
1124                 /* Acquire DMA channels */
1125                 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1126                                                                   "rx");
1127                 if (IS_ERR(sdd->rx_dma.ch)) {
1128                         dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1129                         ret = PTR_ERR(sdd->rx_dma.ch);
1130                         goto err_disable_io_clk;
1131                 }
1132                 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1133                                                                   "tx");
1134                 if (IS_ERR(sdd->tx_dma.ch)) {
1135                         dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1136                         ret = PTR_ERR(sdd->tx_dma.ch);
1137                         goto err_release_rx_dma;
1138                 }
1139         }
1140
1141         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1142         pm_runtime_use_autosuspend(&pdev->dev);
1143         pm_runtime_set_active(&pdev->dev);
1144         pm_runtime_enable(&pdev->dev);
1145         pm_runtime_get_sync(&pdev->dev);
1146
1147         /* Setup Deufult Mode */
1148         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1149
1150         spin_lock_init(&sdd->lock);
1151         init_completion(&sdd->xfer_completion);
1152
1153         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1154                                 "spi-s3c64xx", sdd);
1155         if (ret != 0) {
1156                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1157                         irq, ret);
1158                 goto err_pm_put;
1159         }
1160
1161         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1162                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1163                sdd->regs + S3C64XX_SPI_INT_EN);
1164
1165         ret = devm_spi_register_master(&pdev->dev, master);
1166         if (ret != 0) {
1167                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1168                 goto err_pm_put;
1169         }
1170
1171         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1172                                         sdd->port_id, master->num_chipselect);
1173         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1174                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1175
1176         pm_runtime_mark_last_busy(&pdev->dev);
1177         pm_runtime_put_autosuspend(&pdev->dev);
1178
1179         return 0;
1180
1181 err_pm_put:
1182         pm_runtime_put_noidle(&pdev->dev);
1183         pm_runtime_disable(&pdev->dev);
1184         pm_runtime_set_suspended(&pdev->dev);
1185
1186         if (!is_polling(sdd))
1187                 dma_release_channel(sdd->tx_dma.ch);
1188 err_release_rx_dma:
1189         if (!is_polling(sdd))
1190                 dma_release_channel(sdd->rx_dma.ch);
1191 err_disable_io_clk:
1192         clk_disable_unprepare(sdd->ioclk);
1193 err_disable_src_clk:
1194         clk_disable_unprepare(sdd->src_clk);
1195 err_disable_clk:
1196         clk_disable_unprepare(sdd->clk);
1197 err_deref_master:
1198         spi_master_put(master);
1199
1200         return ret;
1201 }
1202
1203 static int s3c64xx_spi_remove(struct platform_device *pdev)
1204 {
1205         struct spi_master *master = platform_get_drvdata(pdev);
1206         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1207
1208         pm_runtime_get_sync(&pdev->dev);
1209
1210         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1211
1212         if (!is_polling(sdd)) {
1213                 dma_release_channel(sdd->rx_dma.ch);
1214                 dma_release_channel(sdd->tx_dma.ch);
1215         }
1216
1217         clk_disable_unprepare(sdd->ioclk);
1218
1219         clk_disable_unprepare(sdd->src_clk);
1220
1221         clk_disable_unprepare(sdd->clk);
1222
1223         pm_runtime_put_noidle(&pdev->dev);
1224         pm_runtime_disable(&pdev->dev);
1225         pm_runtime_set_suspended(&pdev->dev);
1226
1227         return 0;
1228 }
1229
1230 #ifdef CONFIG_PM_SLEEP
1231 static int s3c64xx_spi_suspend(struct device *dev)
1232 {
1233         struct spi_master *master = dev_get_drvdata(dev);
1234         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1235
1236         int ret = spi_master_suspend(master);
1237         if (ret)
1238                 return ret;
1239
1240         ret = pm_runtime_force_suspend(dev);
1241         if (ret < 0)
1242                 return ret;
1243
1244         sdd->cur_speed = 0; /* Output Clock is stopped */
1245
1246         return 0;
1247 }
1248
1249 static int s3c64xx_spi_resume(struct device *dev)
1250 {
1251         struct spi_master *master = dev_get_drvdata(dev);
1252         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1253         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1254         int ret;
1255
1256         if (sci->cfg_gpio)
1257                 sci->cfg_gpio();
1258
1259         ret = pm_runtime_force_resume(dev);
1260         if (ret < 0)
1261                 return ret;
1262
1263         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1264
1265         return spi_master_resume(master);
1266 }
1267 #endif /* CONFIG_PM_SLEEP */
1268
1269 #ifdef CONFIG_PM
1270 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1271 {
1272         struct spi_master *master = dev_get_drvdata(dev);
1273         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1274
1275         clk_disable_unprepare(sdd->clk);
1276         clk_disable_unprepare(sdd->src_clk);
1277         clk_disable_unprepare(sdd->ioclk);
1278
1279         return 0;
1280 }
1281
1282 static int s3c64xx_spi_runtime_resume(struct device *dev)
1283 {
1284         struct spi_master *master = dev_get_drvdata(dev);
1285         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1286         int ret;
1287
1288         if (sdd->port_conf->clk_ioclk) {
1289                 ret = clk_prepare_enable(sdd->ioclk);
1290                 if (ret != 0)
1291                         return ret;
1292         }
1293
1294         ret = clk_prepare_enable(sdd->src_clk);
1295         if (ret != 0)
1296                 goto err_disable_ioclk;
1297
1298         ret = clk_prepare_enable(sdd->clk);
1299         if (ret != 0)
1300                 goto err_disable_src_clk;
1301
1302         return 0;
1303
1304 err_disable_src_clk:
1305         clk_disable_unprepare(sdd->src_clk);
1306 err_disable_ioclk:
1307         clk_disable_unprepare(sdd->ioclk);
1308
1309         return ret;
1310 }
1311 #endif /* CONFIG_PM */
1312
1313 static const struct dev_pm_ops s3c64xx_spi_pm = {
1314         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1315         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1316                            s3c64xx_spi_runtime_resume, NULL)
1317 };
1318
1319 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1320         .fifo_lvl_mask  = { 0x7f },
1321         .rx_lvl_offset  = 13,
1322         .tx_st_done     = 21,
1323         .high_speed     = true,
1324 };
1325
1326 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1327         .fifo_lvl_mask  = { 0x7f, 0x7F },
1328         .rx_lvl_offset  = 13,
1329         .tx_st_done     = 21,
1330 };
1331
1332 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1333         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1334         .rx_lvl_offset  = 15,
1335         .tx_st_done     = 25,
1336         .high_speed     = true,
1337 };
1338
1339 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1340         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1341         .rx_lvl_offset  = 15,
1342         .tx_st_done     = 25,
1343         .high_speed     = true,
1344         .clk_from_cmu   = true,
1345 };
1346
1347 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1348         .fifo_lvl_mask  = { 0x1ff },
1349         .rx_lvl_offset  = 15,
1350         .tx_st_done     = 25,
1351         .high_speed     = true,
1352         .clk_from_cmu   = true,
1353         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1354 };
1355
1356 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1357         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1358         .rx_lvl_offset  = 15,
1359         .tx_st_done     = 25,
1360         .high_speed     = true,
1361         .clk_from_cmu   = true,
1362         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1363 };
1364
1365 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1366         .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1367         .rx_lvl_offset  = 15,
1368         .tx_st_done     = 25,
1369         .high_speed     = true,
1370         .clk_from_cmu   = true,
1371         .clk_ioclk      = true,
1372         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1373 };
1374
1375 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1376         {
1377                 .name           = "s3c2443-spi",
1378                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1379         }, {
1380                 .name           = "s3c6410-spi",
1381                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1382         },
1383         { },
1384 };
1385
1386 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1387         { .compatible = "samsung,s3c2443-spi",
1388                         .data = (void *)&s3c2443_spi_port_config,
1389         },
1390         { .compatible = "samsung,s3c6410-spi",
1391                         .data = (void *)&s3c6410_spi_port_config,
1392         },
1393         { .compatible = "samsung,s5pv210-spi",
1394                         .data = (void *)&s5pv210_spi_port_config,
1395         },
1396         { .compatible = "samsung,exynos4210-spi",
1397                         .data = (void *)&exynos4_spi_port_config,
1398         },
1399         { .compatible = "samsung,exynos5440-spi",
1400                         .data = (void *)&exynos5440_spi_port_config,
1401         },
1402         { .compatible = "samsung,exynos7-spi",
1403                         .data = (void *)&exynos7_spi_port_config,
1404         },
1405         { .compatible = "samsung,exynos5433-spi",
1406                         .data = (void *)&exynos5433_spi_port_config,
1407         },
1408         { },
1409 };
1410 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1411
1412 static struct platform_driver s3c64xx_spi_driver = {
1413         .driver = {
1414                 .name   = "s3c64xx-spi",
1415                 .pm = &s3c64xx_spi_pm,
1416                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1417         },
1418         .probe = s3c64xx_spi_probe,
1419         .remove = s3c64xx_spi_remove,
1420         .id_table = s3c64xx_spi_driver_ids,
1421 };
1422 MODULE_ALIAS("platform:s3c64xx-spi");
1423
1424 module_platform_driver(s3c64xx_spi_driver);
1425
1426 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1427 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1428 MODULE_LICENSE("GPL");