2 * Copyright (c) 2006 Ben Dooks
3 * Copyright 2006-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/spinlock.h>
13 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
22 #include <linux/slab.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_bitbang.h>
26 #include <linux/spi/s3c24xx.h>
27 #include <linux/module.h>
29 #include <plat/regs-spi.h>
33 #include "spi-s3c24xx-fiq.h"
36 * s3c24xx_spi_devstate - per device data
37 * @hz: Last frequency calculated for @sppre field.
38 * @mode: Last mode setting for the @spcon field.
39 * @spcon: Value to write to the SPCON register.
40 * @sppre: Value to write to the SPPRE register.
42 struct s3c24xx_spi_devstate {
57 /* bitbang has to be first */
58 struct spi_bitbang bitbang;
59 struct completion done;
66 struct fiq_handler fiq_handler;
67 enum spi_fiq_mode fiq_mode;
68 unsigned char fiq_inuse;
69 unsigned char fiq_claimed;
71 void (*set_cs)(struct s3c2410_spi_info *spi,
75 const unsigned char *tx;
79 struct spi_master *master;
80 struct spi_device *curdev;
82 struct s3c2410_spi_info *pdata;
85 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
86 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
88 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
90 return spi_master_get_devdata(sdev->master);
93 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
95 gpio_set_value(spi->pin_cs, pol);
98 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
100 struct s3c24xx_spi_devstate *cs = spi->controller_state;
101 struct s3c24xx_spi *hw = to_hw(spi);
102 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
104 /* change the chipselect state and the state of the spi engine clock */
107 case BITBANG_CS_INACTIVE:
108 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
109 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
112 case BITBANG_CS_ACTIVE:
113 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
114 hw->regs + S3C2410_SPCON);
115 hw->set_cs(hw->pdata, spi->chip_select, cspol);
120 static int s3c24xx_spi_update_state(struct spi_device *spi,
121 struct spi_transfer *t)
123 struct s3c24xx_spi *hw = to_hw(spi);
124 struct s3c24xx_spi_devstate *cs = spi->controller_state;
130 bpw = t ? t->bits_per_word : spi->bits_per_word;
131 hz = t ? t->speed_hz : spi->max_speed_hz;
137 hz = spi->max_speed_hz;
140 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
144 if (spi->mode != cs->mode) {
145 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
147 if (spi->mode & SPI_CPHA)
148 spcon |= S3C2410_SPCON_CPHA_FMTB;
150 if (spi->mode & SPI_CPOL)
151 spcon |= S3C2410_SPCON_CPOL_HIGH;
153 cs->mode = spi->mode;
158 clk = clk_get_rate(hw->clk);
159 div = DIV_ROUND_UP(clk, hz * 2) - 1;
164 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
165 div, hz, clk / (2 * (div + 1)));
174 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
175 struct spi_transfer *t)
177 struct s3c24xx_spi_devstate *cs = spi->controller_state;
178 struct s3c24xx_spi *hw = to_hw(spi);
181 ret = s3c24xx_spi_update_state(spi, t);
183 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
188 static int s3c24xx_spi_setup(struct spi_device *spi)
190 struct s3c24xx_spi_devstate *cs = spi->controller_state;
191 struct s3c24xx_spi *hw = to_hw(spi);
194 /* allocate settings on the first call */
196 cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
198 dev_err(&spi->dev, "no memory for controller state\n");
202 cs->spcon = SPCON_DEFAULT;
204 spi->controller_state = cs;
207 /* initialise the state from the device */
208 ret = s3c24xx_spi_update_state(spi, NULL);
212 spin_lock(&hw->bitbang.lock);
213 if (!hw->bitbang.busy) {
214 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
215 /* need to ndelay for 0.5 clocktick ? */
217 spin_unlock(&hw->bitbang.lock);
222 static void s3c24xx_spi_cleanup(struct spi_device *spi)
224 kfree(spi->controller_state);
227 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
229 return hw->tx ? hw->tx[count] : 0;
232 #ifdef CONFIG_SPI_S3C24XX_FIQ
233 /* Support for FIQ based pseudo-DMA to improve the transfer speed.
235 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
236 * used by the FIQ core to move data between main memory and the peripheral
237 * block. Since this is code running on the processor, there is no problem
238 * with cache coherency of the buffers, so we can use any buffer we like.
242 * struct spi_fiq_code - FIQ code and header
243 * @length: The length of the code fragment, excluding this header.
244 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
245 * @data: The code itself to install as a FIQ handler.
247 struct spi_fiq_code {
253 extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
254 extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
255 extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
258 * ack_bit - turn IRQ into IRQ acknowledgement bit
259 * @irq: The interrupt number
261 * Returns the bit to write to the interrupt acknowledge register.
263 static inline u32 ack_bit(unsigned int irq)
265 return 1 << (irq - IRQ_EINT0);
269 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
270 * @hw: The hardware state.
272 * Claim the FIQ handler (only one can be active at any one time) and
273 * then setup the correct transfer code for this transfer.
275 * This call updates all the necessary state information if successful,
276 * so the caller does not need to do anything more than start the transfer
277 * as normal, since the IRQ will have been re-routed to the FIQ handler.
279 static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
282 enum spi_fiq_mode mode;
283 struct spi_fiq_code *code;
286 if (!hw->fiq_claimed) {
287 /* try and claim fiq if we haven't got it, and if not
288 * then return and simply use another transfer method */
290 ret = claim_fiq(&hw->fiq_handler);
295 if (hw->tx && !hw->rx)
297 else if (hw->rx && !hw->tx)
300 mode = FIQ_MODE_TXRX;
302 regs.uregs[fiq_rspi] = (long)hw->regs;
303 regs.uregs[fiq_rrx] = (long)hw->rx;
304 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
305 regs.uregs[fiq_rcount] = hw->len - 1;
306 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
310 if (hw->fiq_mode != mode) {
317 code = &s3c24xx_spi_fiq_tx;
320 code = &s3c24xx_spi_fiq_rx;
323 code = &s3c24xx_spi_fiq_txrx;
331 ack_ptr = (u32 *)&code->data[code->ack_offset];
332 *ack_ptr = ack_bit(hw->irq);
334 set_fiq_handler(&code->data, code->length);
337 s3c24xx_set_fiq(hw->irq, true);
344 * s3c24xx_spi_fiqop - FIQ core code callback
345 * @pw: Data registered with the handler
346 * @release: Whether this is a release or a return.
348 * Called by the FIQ code when another module wants to use the FIQ, so
349 * return whether we are currently using this or not and then update our
352 static int s3c24xx_spi_fiqop(void *pw, int release)
354 struct s3c24xx_spi *hw = pw;
361 /* note, we do not need to unroute the FIQ, as the FIQ
362 * vector code de-routes it to signal the end of transfer */
364 hw->fiq_mode = FIQ_MODE_NONE;
374 * s3c24xx_spi_initfiq - setup the information for the FIQ core
375 * @hw: The hardware state.
377 * Setup the fiq_handler block to pass to the FIQ core.
379 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
381 hw->fiq_handler.dev_id = hw;
382 hw->fiq_handler.name = dev_name(hw->dev);
383 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
387 * s3c24xx_spi_usefiq - return if we should be using FIQ.
388 * @hw: The hardware state.
390 * Return true if the platform data specifies whether this channel is
391 * allowed to use the FIQ.
393 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
395 return hw->pdata->use_fiq;
399 * s3c24xx_spi_usingfiq - return if channel is using FIQ
400 * @spi: The hardware state.
402 * Return whether the channel is currently using the FIQ (separate from
403 * whether the FIQ is claimed).
405 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
407 return spi->fiq_inuse;
411 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
412 static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
413 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
414 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
416 #endif /* CONFIG_SPI_S3C24XX_FIQ */
418 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
420 struct s3c24xx_spi *hw = to_hw(spi);
427 init_completion(&hw->done);
430 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
431 s3c24xx_spi_tryfiq(hw);
433 /* send the first byte */
434 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
436 wait_for_completion(&hw->done);
440 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
442 struct s3c24xx_spi *hw = dev;
443 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
444 unsigned int count = hw->count;
446 if (spsta & S3C2410_SPSTA_DCOL) {
447 dev_dbg(hw->dev, "data-collision\n");
452 if (!(spsta & S3C2410_SPSTA_READY)) {
453 dev_dbg(hw->dev, "spi not ready for tx?\n");
458 if (!s3c24xx_spi_usingfiq(hw)) {
462 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
467 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
475 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
484 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
486 /* for the moment, permanently enable the clock */
490 /* program defaults into the registers */
492 writeb(0xff, hw->regs + S3C2410_SPPRE);
493 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
494 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
497 if (hw->set_cs == s3c24xx_spi_gpiocs)
498 gpio_direction_output(hw->pdata->pin_cs, 1);
500 if (hw->pdata->gpio_setup)
501 hw->pdata->gpio_setup(hw->pdata, 1);
505 static int s3c24xx_spi_probe(struct platform_device *pdev)
507 struct s3c2410_spi_info *pdata;
508 struct s3c24xx_spi *hw;
509 struct spi_master *master;
510 struct resource *res;
513 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
514 if (master == NULL) {
515 dev_err(&pdev->dev, "No memory for spi_master\n");
519 hw = spi_master_get_devdata(master);
520 memset(hw, 0, sizeof(struct s3c24xx_spi));
523 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
524 hw->dev = &pdev->dev;
527 dev_err(&pdev->dev, "No platform data supplied\n");
532 platform_set_drvdata(pdev, hw);
533 init_completion(&hw->done);
535 /* initialise fiq handler */
537 s3c24xx_spi_initfiq(hw);
539 /* setup the master state. */
541 /* the spi->mode bits understood by this driver: */
542 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
544 master->num_chipselect = hw->pdata->num_cs;
545 master->bus_num = pdata->bus_num;
547 /* setup the state for the bitbang driver */
549 hw->bitbang.master = hw->master;
550 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
551 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
552 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
554 hw->master->setup = s3c24xx_spi_setup;
555 hw->master->cleanup = s3c24xx_spi_cleanup;
557 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
559 /* find and map our resources */
560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
561 hw->regs = devm_ioremap_resource(&pdev->dev, res);
562 if (IS_ERR(hw->regs)) {
563 err = PTR_ERR(hw->regs);
567 hw->irq = platform_get_irq(pdev, 0);
569 dev_err(&pdev->dev, "No IRQ specified\n");
574 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
577 dev_err(&pdev->dev, "Cannot claim IRQ\n");
581 hw->clk = devm_clk_get(&pdev->dev, "spi");
582 if (IS_ERR(hw->clk)) {
583 dev_err(&pdev->dev, "No clock for device\n");
584 err = PTR_ERR(hw->clk);
588 /* setup any gpio we can */
590 if (!pdata->set_cs) {
591 if (pdata->pin_cs < 0) {
592 dev_err(&pdev->dev, "No chipselect pin\n");
597 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
598 dev_name(&pdev->dev));
600 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
604 hw->set_cs = s3c24xx_spi_gpiocs;
605 gpio_direction_output(pdata->pin_cs, 1);
607 hw->set_cs = pdata->set_cs;
609 s3c24xx_spi_initialsetup(hw);
611 /* register our spi controller */
613 err = spi_bitbang_start(&hw->bitbang);
615 dev_err(&pdev->dev, "Failed to register SPI master\n");
622 clk_disable(hw->clk);
625 spi_master_put(hw->master);
629 static int s3c24xx_spi_remove(struct platform_device *dev)
631 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
633 spi_bitbang_stop(&hw->bitbang);
634 clk_disable(hw->clk);
635 spi_master_put(hw->master);
642 static int s3c24xx_spi_suspend(struct device *dev)
644 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
646 if (hw->pdata && hw->pdata->gpio_setup)
647 hw->pdata->gpio_setup(hw->pdata, 0);
649 clk_disable(hw->clk);
653 static int s3c24xx_spi_resume(struct device *dev)
655 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
657 s3c24xx_spi_initialsetup(hw);
661 static const struct dev_pm_ops s3c24xx_spi_pmops = {
662 .suspend = s3c24xx_spi_suspend,
663 .resume = s3c24xx_spi_resume,
666 #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
668 #define S3C24XX_SPI_PMOPS NULL
669 #endif /* CONFIG_PM */
671 MODULE_ALIAS("platform:s3c2410-spi");
672 static struct platform_driver s3c24xx_spi_driver = {
673 .probe = s3c24xx_spi_probe,
674 .remove = s3c24xx_spi_remove,
676 .name = "s3c2410-spi",
677 .owner = THIS_MODULE,
678 .pm = S3C24XX_SPI_PMOPS,
681 module_platform_driver(s3c24xx_spi_driver);
683 MODULE_DESCRIPTION("S3C24XX SPI Driver");
684 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
685 MODULE_LICENSE("GPL");