drivers/spi/spi-pxa2xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4  * Copyright (C) 2013, Intel Corporation
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/gpio.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/property.h>
  27 #include <linux/slab.h>
  28 #include <linux/spi/pxa2xx_spi.h>
  29 #include <linux/spi/spi.h>
  30
  31 #include "spi-pxa2xx.h"
  32
  33 MODULE_AUTHOR("Stephen Street");
  34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  35 MODULE_LICENSE("GPL");
  36 MODULE_ALIAS("platform:pxa2xx-spi");
  37
  38 #define TIMOUT_DFLT             1000
  39
  40 /*
  41  * for testing SSCR1 changes that require SSP restart, basically
  42  * everything except the service and interrupt enables, the pxa270 developer
  43  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  44  * list, but the PXA255 dev man says all bits without really meaning the
  45  * service and interrupt enables
  46  */
  47 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  48                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  49                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  50                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  51                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  52                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  53
  54 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  55                                 | QUARK_X1000_SSCR1_EFWR        \
  56                                 | QUARK_X1000_SSCR1_RFT         \
  57                                 | QUARK_X1000_SSCR1_TFT         \
  58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59
  60 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  61                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  62                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  63                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  64                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  65                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  66
  67 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  68 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  69 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  70 #define LPSS_CAPS_CS_EN_SHIFT                   9
  71 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  72
  73 #define LPSS_PRIV_CLOCK_GATE 0x38
  74 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
  75 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
  76
  77 struct lpss_config {
  78         /* LPSS offset from drv_data->ioaddr */
  79         unsigned offset;
  80         /* Register offsets from drv_data->lpss_base or -1 */
  81         int reg_general;
  82         int reg_ssp;
  83         int reg_cs_ctrl;
  84         int reg_capabilities;
  85         /* FIFO thresholds */
  86         u32 rx_threshold;
  87         u32 tx_threshold_lo;
  88         u32 tx_threshold_hi;
  89         /* Chip select control */
  90         unsigned cs_sel_shift;
  91         unsigned cs_sel_mask;
  92         unsigned cs_num;
  93         /* Quirks */
  94         unsigned cs_clk_stays_gated : 1;
  95 };
  96
  97 /* Keep these sorted with enum pxa_ssp_type */
  98 static const struct lpss_config lpss_platforms[] = {
  99         {       /* LPSS_LPT_SSP */
 100                 .offset = 0x800,
 101                 .reg_general = 0x08,
 102                 .reg_ssp = 0x0c,
 103                 .reg_cs_ctrl = 0x18,
 104                 .reg_capabilities = -1,
 105                 .rx_threshold = 64,
 106                 .tx_threshold_lo = 160,
 107                 .tx_threshold_hi = 224,
 108         },
 109         {       /* LPSS_BYT_SSP */
 110                 .offset = 0x400,
 111                 .reg_general = 0x08,
 112                 .reg_ssp = 0x0c,
 113                 .reg_cs_ctrl = 0x18,
 114                 .reg_capabilities = -1,
 115                 .rx_threshold = 64,
 116                 .tx_threshold_lo = 160,
 117                 .tx_threshold_hi = 224,
 118         },
 119         {       /* LPSS_BSW_SSP */
 120                 .offset = 0x400,
 121                 .reg_general = 0x08,
 122                 .reg_ssp = 0x0c,
 123                 .reg_cs_ctrl = 0x18,
 124                 .reg_capabilities = -1,
 125                 .rx_threshold = 64,
 126                 .tx_threshold_lo = 160,
 127                 .tx_threshold_hi = 224,
 128                 .cs_sel_shift = 2,
 129                 .cs_sel_mask = 1 << 2,
 130                 .cs_num = 2,
 131         },
 132         {       /* LPSS_SPT_SSP */
 133                 .offset = 0x200,
 134                 .reg_general = -1,
 135                 .reg_ssp = 0x20,
 136                 .reg_cs_ctrl = 0x24,
 137                 .reg_capabilities = -1,
 138                 .rx_threshold = 1,
 139                 .tx_threshold_lo = 32,
 140                 .tx_threshold_hi = 56,
 141         },
 142         {       /* LPSS_BXT_SSP */
 143                 .offset = 0x200,
 144                 .reg_general = -1,
 145                 .reg_ssp = 0x20,
 146                 .reg_cs_ctrl = 0x24,
 147                 .reg_capabilities = 0xfc,
 148                 .rx_threshold = 1,
 149                 .tx_threshold_lo = 16,
 150                 .tx_threshold_hi = 48,
 151                 .cs_sel_shift = 8,
 152                 .cs_sel_mask = 3 << 8,
 153         },
 154         {       /* LPSS_CNL_SSP */
 155                 .offset = 0x200,
 156                 .reg_general = -1,
 157                 .reg_ssp = 0x20,
 158                 .reg_cs_ctrl = 0x24,
 159                 .reg_capabilities = 0xfc,
 160                 .rx_threshold = 1,
 161                 .tx_threshold_lo = 32,
 162                 .tx_threshold_hi = 56,
 163                 .cs_sel_shift = 8,
 164                 .cs_sel_mask = 3 << 8,
 165                 .cs_clk_stays_gated = true,
 166         },
 167 };
 168
 169 static inline const struct lpss_config
 170 *lpss_get_config(const struct driver_data *drv_data)
 171 {
 172         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 173 }
 174
 175 static bool is_lpss_ssp(const struct driver_data *drv_data)
 176 {
 177         switch (drv_data->ssp_type) {
 178         case LPSS_LPT_SSP:
 179         case LPSS_BYT_SSP:
 180         case LPSS_BSW_SSP:
 181         case LPSS_SPT_SSP:
 182         case LPSS_BXT_SSP:
 183         case LPSS_CNL_SSP:
 184                 return true;
 185         default:
 186                 return false;
 187         }
 188 }
 189
 190 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 191 {
 192         return drv_data->ssp_type == QUARK_X1000_SSP;
 193 }
 194
 195 static bool is_mmp2_ssp(const struct driver_data *drv_data)
 196 {
 197         return drv_data->ssp_type == MMP2_SSP;
 198 }
 199
 200 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 201 {
 202         switch (drv_data->ssp_type) {
 203         case QUARK_X1000_SSP:
 204                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 205         case CE4100_SSP:
 206                 return CE4100_SSCR1_CHANGE_MASK;
 207         default:
 208                 return SSCR1_CHANGE_MASK;
 209         }
 210 }
 211
 212 static u32
 213 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 214 {
 215         switch (drv_data->ssp_type) {
 216         case QUARK_X1000_SSP:
 217                 return RX_THRESH_QUARK_X1000_DFLT;
 218         case CE4100_SSP:
 219                 return RX_THRESH_CE4100_DFLT;
 220         default:
 221                 return RX_THRESH_DFLT;
 222         }
 223 }
 224
 225 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 226 {
 227         u32 mask;
 228
 229         switch (drv_data->ssp_type) {
 230         case QUARK_X1000_SSP:
 231                 mask = QUARK_X1000_SSSR_TFL_MASK;
 232                 break;
 233         case CE4100_SSP:
 234                 mask = CE4100_SSSR_TFL_MASK;
 235                 break;
 236         default:
 237                 mask = SSSR_TFL_MASK;
 238                 break;
 239         }
 240
 241         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 242 }
 243
 244 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 245                                      u32 *sccr1_reg)
 246 {
 247         u32 mask;
 248
 249         switch (drv_data->ssp_type) {
 250         case QUARK_X1000_SSP:
 251                 mask = QUARK_X1000_SSCR1_RFT;
 252                 break;
 253         case CE4100_SSP:
 254                 mask = CE4100_SSCR1_RFT;
 255                 break;
 256         default:
 257                 mask = SSCR1_RFT;
 258                 break;
 259         }
 260         *sccr1_reg &= ~mask;
 261 }
 262
 263 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 264                                    u32 *sccr1_reg, u32 threshold)
 265 {
 266         switch (drv_data->ssp_type) {
 267         case QUARK_X1000_SSP:
 268                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 269                 break;
 270         case CE4100_SSP:
 271                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 272                 break;
 273         default:
 274                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 275                 break;
 276         }
 277 }
 278
 279 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 280                                   u32 clk_div, u8 bits)
 281 {
 282         switch (drv_data->ssp_type) {
 283         case QUARK_X1000_SSP:
 284                 return clk_div
 285                         | QUARK_X1000_SSCR0_Motorola
 286                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 287                         | SSCR0_SSE;
 288         default:
 289                 return clk_div
 290                         | SSCR0_Motorola
 291                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 292                         | SSCR0_SSE
 293                         | (bits > 16 ? SSCR0_EDSS : 0);
 294         }
 295 }
 296
 297 /*
 298  * Read and write LPSS SSP private registers. Caller must first check that
 299  * is_lpss_ssp() returns true before these can be called.
 300  */
 301 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 302 {
 303         WARN_ON(!drv_data->lpss_base);
 304         return readl(drv_data->lpss_base + offset);
 305 }
 306
 307 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 308                                   unsigned offset, u32 value)
 309 {
 310         WARN_ON(!drv_data->lpss_base);
 311         writel(value, drv_data->lpss_base + offset);
 312 }
 313
 314 /*
 315  * lpss_ssp_setup - perform LPSS SSP specific setup
 316  * @drv_data: pointer to the driver private data
 317  *
 318  * Perform LPSS SSP specific setup. This function must be called first if
 319  * one is going to use LPSS SSP private registers.
 320  */
 321 static void lpss_ssp_setup(struct driver_data *drv_data)
 322 {
 323         const struct lpss_config *config;
 324         u32 value;
 325
 326         config = lpss_get_config(drv_data);
 327         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 328
 329         /* Enable software chip select control */
 330         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 331         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 332         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 333         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 334
 335         /* Enable multiblock DMA transfers */
 336         if (drv_data->controller_info->enable_dma) {
 337                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 338
 339                 if (config->reg_general >= 0) {
 340                         value = __lpss_ssp_read_priv(drv_data,
 341                                                      config->reg_general);
 342                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 343                         __lpss_ssp_write_priv(drv_data,
 344                                               config->reg_general, value);
 345                 }
 346         }
 347 }
 348
 349 static void lpss_ssp_select_cs(struct spi_device *spi,
 350                                const struct lpss_config *config)
 351 {
 352         struct driver_data *drv_data =
 353                 spi_controller_get_devdata(spi->controller);
 354         u32 value, cs;
 355
 356         if (!config->cs_sel_mask)
 357                 return;
 358
 359         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 360
 361         cs = spi->chip_select;
 362         cs <<= config->cs_sel_shift;
 363         if (cs != (value & config->cs_sel_mask)) {
 364                 /*
 365                  * When switching another chip select output active the
 366                  * output must be selected first and wait 2 ssp_clk cycles
 367                  * before changing state to active. Otherwise a short
 368                  * glitch will occur on the previous chip select since
 369                  * output select is latched but state control is not.
 370                  */
 371                 value &= ~config->cs_sel_mask;
 372                 value |= cs;
 373                 __lpss_ssp_write_priv(drv_data,
 374                                       config->reg_cs_ctrl, value);
 375                 ndelay(1000000000 /
 376                        (drv_data->controller->max_speed_hz / 2));
 377         }
 378 }
 379
 380 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 381 {
 382         struct driver_data *drv_data =
 383                 spi_controller_get_devdata(spi->controller);
 384         const struct lpss_config *config;
 385         u32 value;
 386
 387         config = lpss_get_config(drv_data);
 388
 389         if (enable)
 390                 lpss_ssp_select_cs(spi, config);
 391
 392         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 393         if (enable)
 394                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 395         else
 396                 value |= LPSS_CS_CONTROL_CS_HIGH;
 397         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 398         if (config->cs_clk_stays_gated) {
 399                 u32 clkgate;
 400
 401                 /*
 402                  * Changing CS alone when dynamic clock gating is on won't
 403                  * actually flip CS at that time. This ruins SPI transfers
 404                  * that specify delays, or have no data. Toggle the clock mode
 405                  * to force on briefly to poke the CS pin to move.
 406                  */
 407                 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
 408                 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
 409                         LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
 410
 411                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
 412                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
 413         }
 414 }
 415
 416 static void cs_assert(struct spi_device *spi)
 417 {
 418         struct chip_data *chip = spi_get_ctldata(spi);
 419         struct driver_data *drv_data =
 420                 spi_controller_get_devdata(spi->controller);
 421
 422         if (drv_data->ssp_type == CE4100_SSP) {
 423                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 424                 return;
 425         }
 426
 427         if (chip->cs_control) {
 428                 chip->cs_control(PXA2XX_CS_ASSERT);
 429                 return;
 430         }
 431
 432         if (chip->gpiod_cs) {
 433                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 434                 return;
 435         }
 436
 437         if (is_lpss_ssp(drv_data))
 438                 lpss_ssp_cs_control(spi, true);
 439 }
 440
 441 static void cs_deassert(struct spi_device *spi)
 442 {
 443         struct chip_data *chip = spi_get_ctldata(spi);
 444         struct driver_data *drv_data =
 445                 spi_controller_get_devdata(spi->controller);
 446         unsigned long timeout;
 447
 448         if (drv_data->ssp_type == CE4100_SSP)
 449                 return;
 450
 451         /* Wait until SSP becomes idle before deasserting the CS */
 452         timeout = jiffies + msecs_to_jiffies(10);
 453         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 454                !time_after(jiffies, timeout))
 455                 cpu_relax();
 456
 457         if (chip->cs_control) {
 458                 chip->cs_control(PXA2XX_CS_DEASSERT);
 459                 return;
 460         }
 461
 462         if (chip->gpiod_cs) {
 463                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 464                 return;
 465         }
 466
 467         if (is_lpss_ssp(drv_data))
 468                 lpss_ssp_cs_control(spi, false);
 469 }
 470
 471 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 472 {
 473         if (level)
 474                 cs_deassert(spi);
 475         else
 476                 cs_assert(spi);
 477 }
 478
 479 int pxa2xx_spi_flush(struct driver_data *drv_data)
 480 {
 481         unsigned long limit = loops_per_jiffy << 1;
 482
 483         do {
 484                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 485                         pxa2xx_spi_read(drv_data, SSDR);
 486         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 487         write_SSSR_CS(drv_data, SSSR_ROR);
 488
 489         return limit;
 490 }
 491
 492 static void pxa2xx_spi_off(struct driver_data *drv_data)
 493 {
 494         /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
 495         if (is_mmp2_ssp(drv_data))
 496                 return;
 497
 498         pxa2xx_spi_write(drv_data, SSCR0,
 499                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 500 }
 501
 502 static int null_writer(struct driver_data *drv_data)
 503 {
 504         u8 n_bytes = drv_data->n_bytes;
 505
 506         if (pxa2xx_spi_txfifo_full(drv_data)
 507                 || (drv_data->tx == drv_data->tx_end))
 508                 return 0;
 509
 510         pxa2xx_spi_write(drv_data, SSDR, 0);
 511         drv_data->tx += n_bytes;
 512
 513         return 1;
 514 }
 515
 516 static int null_reader(struct driver_data *drv_data)
 517 {
 518         u8 n_bytes = drv_data->n_bytes;
 519
 520         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 521                && (drv_data->rx < drv_data->rx_end)) {
 522                 pxa2xx_spi_read(drv_data, SSDR);
 523                 drv_data->rx += n_bytes;
 524         }
 525
 526         return drv_data->rx == drv_data->rx_end;
 527 }
 528
 529 static int u8_writer(struct driver_data *drv_data)
 530 {
 531         if (pxa2xx_spi_txfifo_full(drv_data)
 532                 || (drv_data->tx == drv_data->tx_end))
 533                 return 0;
 534
 535         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 536         ++drv_data->tx;
 537
 538         return 1;
 539 }
 540
 541 static int u8_reader(struct driver_data *drv_data)
 542 {
 543         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 544                && (drv_data->rx < drv_data->rx_end)) {
 545                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 546                 ++drv_data->rx;
 547         }
 548
 549         return drv_data->rx == drv_data->rx_end;
 550 }
 551
 552 static int u16_writer(struct driver_data *drv_data)
 553 {
 554         if (pxa2xx_spi_txfifo_full(drv_data)
 555                 || (drv_data->tx == drv_data->tx_end))
 556                 return 0;
 557
 558         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 559         drv_data->tx += 2;
 560
 561         return 1;
 562 }
 563
 564 static int u16_reader(struct driver_data *drv_data)
 565 {
 566         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 567                && (drv_data->rx < drv_data->rx_end)) {
 568                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 569                 drv_data->rx += 2;
 570         }
 571
 572         return drv_data->rx == drv_data->rx_end;
 573 }
 574
 575 static int u32_writer(struct driver_data *drv_data)
 576 {
 577         if (pxa2xx_spi_txfifo_full(drv_data)
 578                 || (drv_data->tx == drv_data->tx_end))
 579                 return 0;
 580
 581         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 582         drv_data->tx += 4;
 583
 584         return 1;
 585 }
 586
 587 static int u32_reader(struct driver_data *drv_data)
 588 {
 589         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 590                && (drv_data->rx < drv_data->rx_end)) {
 591                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 592                 drv_data->rx += 4;
 593         }
 594
 595         return drv_data->rx == drv_data->rx_end;
 596 }
 597
 598 static void reset_sccr1(struct driver_data *drv_data)
 599 {
 600         struct chip_data *chip =
 601                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 602         u32 sccr1_reg;
 603
 604         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 605         switch (drv_data->ssp_type) {
 606         case QUARK_X1000_SSP:
 607                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 608                 break;
 609         case CE4100_SSP:
 610                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 611                 break;
 612         default:
 613                 sccr1_reg &= ~SSCR1_RFT;
 614                 break;
 615         }
 616         sccr1_reg |= chip->threshold;
 617         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 618 }
 619
 620 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 621 {
 622         /* Stop and reset SSP */
 623         write_SSSR_CS(drv_data, drv_data->clear_sr);
 624         reset_sccr1(drv_data);
 625         if (!pxa25x_ssp_comp(drv_data))
 626                 pxa2xx_spi_write(drv_data, SSTO, 0);
 627         pxa2xx_spi_flush(drv_data);
 628         pxa2xx_spi_off(drv_data);
 629
 630         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 631
 632         drv_data->controller->cur_msg->status = -EIO;
 633         spi_finalize_current_transfer(drv_data->controller);
 634 }
 635
 636 static void int_transfer_complete(struct driver_data *drv_data)
 637 {
 638         /* Clear and disable interrupts */
 639         write_SSSR_CS(drv_data, drv_data->clear_sr);
 640         reset_sccr1(drv_data);
 641         if (!pxa25x_ssp_comp(drv_data))
 642                 pxa2xx_spi_write(drv_data, SSTO, 0);
 643
 644         spi_finalize_current_transfer(drv_data->controller);
 645 }
 646
 647 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 648 {
 649         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 650                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 651
 652         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 653
 654         if (irq_status & SSSR_ROR) {
 655                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 656                 return IRQ_HANDLED;
 657         }
 658
 659         if (irq_status & SSSR_TUR) {
 660                 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
 661                 return IRQ_HANDLED;
 662         }
 663
 664         if (irq_status & SSSR_TINT) {
 665                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 666                 if (drv_data->read(drv_data)) {
 667                         int_transfer_complete(drv_data);
 668                         return IRQ_HANDLED;
 669                 }
 670         }
 671
 672         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 673         do {
 674                 if (drv_data->read(drv_data)) {
 675                         int_transfer_complete(drv_data);
 676                         return IRQ_HANDLED;
 677                 }
 678         } while (drv_data->write(drv_data));
 679
 680         if (drv_data->read(drv_data)) {
 681                 int_transfer_complete(drv_data);
 682                 return IRQ_HANDLED;
 683         }
 684
 685         if (drv_data->tx == drv_data->tx_end) {
 686                 u32 bytes_left;
 687                 u32 sccr1_reg;
 688
 689                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 690                 sccr1_reg &= ~SSCR1_TIE;
 691
 692                 /*
 693                  * PXA25x_SSP has no timeout, set up rx threshould for the
 694                  * remaining RX bytes.
 695                  */
 696                 if (pxa25x_ssp_comp(drv_data)) {
 697                         u32 rx_thre;
 698
 699                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 700
 701                         bytes_left = drv_data->rx_end - drv_data->rx;
 702                         switch (drv_data->n_bytes) {
 703                         case 4:
 704                                 bytes_left >>= 2;
 705                                 break;
 706                         case 2:
 707                                 bytes_left >>= 1;
 708                                 break;
 709                         }
 710
 711                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 712                         if (rx_thre > bytes_left)
 713                                 rx_thre = bytes_left;
 714
 715                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 716                 }
 717                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 718         }
 719
 720         /* We did something */
 721         return IRQ_HANDLED;
 722 }
 723
 724 static void handle_bad_msg(struct driver_data *drv_data)
 725 {
 726         pxa2xx_spi_off(drv_data);
 727         pxa2xx_spi_write(drv_data, SSCR1,
 728                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 729         if (!pxa25x_ssp_comp(drv_data))
 730                 pxa2xx_spi_write(drv_data, SSTO, 0);
 731         write_SSSR_CS(drv_data, drv_data->clear_sr);
 732
 733         dev_err(&drv_data->pdev->dev,
 734                 "bad message state in interrupt handler\n");
 735 }
 736
 737 static irqreturn_t ssp_int(int irq, void *dev_id)
 738 {
 739         struct driver_data *drv_data = dev_id;
 740         u32 sccr1_reg;
 741         u32 mask = drv_data->mask_sr;
 742         u32 status;
 743
 744         /*
 745          * The IRQ might be shared with other peripherals so we must first
 746          * check that are we RPM suspended or not. If we are we assume that
 747          * the IRQ was not for us (we shouldn't be RPM suspended when the
 748          * interrupt is enabled).
 749          */
 750         if (pm_runtime_suspended(&drv_data->pdev->dev))
 751                 return IRQ_NONE;
 752
 753         /*
 754          * If the device is not yet in RPM suspended state and we get an
 755          * interrupt that is meant for another device, check if status bits
 756          * are all set to one. That means that the device is already
 757          * powered off.
 758          */
 759         status = pxa2xx_spi_read(drv_data, SSSR);
 760         if (status == ~0)
 761                 return IRQ_NONE;
 762
 763         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 764
 765         /* Ignore possible writes if we don't need to write */
 766         if (!(sccr1_reg & SSCR1_TIE))
 767                 mask &= ~SSSR_TFS;
 768
 769         /* Ignore RX timeout interrupt if it is disabled */
 770         if (!(sccr1_reg & SSCR1_TINTE))
 771                 mask &= ~SSSR_TINT;
 772
 773         if (!(status & mask))
 774                 return IRQ_NONE;
 775
 776         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 777         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 778
 779         if (!drv_data->controller->cur_msg) {
 780                 handle_bad_msg(drv_data);
 781                 /* Never fail */
 782                 return IRQ_HANDLED;
 783         }
 784
 785         return drv_data->transfer_handler(drv_data);
 786 }
 787
 788 /*
 789  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 790  * input frequency by fractions of 2^24. It also has a divider by 5.
 791  *
 792  * There are formulas to get baud rate value for given input frequency and
 793  * divider parameters, such as DDS_CLK_RATE and SCR:
 794  *
 795  * Fsys = 200MHz
 796  *
 797  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 798  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 799  *
 800  * DDS_CLK_RATE either 2^n or 2^n / 5.
 801  * SCR is in range 0 .. 255
 802  *
 803  * Divisor = 5^i * 2^j * 2 * k
 804  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 805  *       j = [0, 23]     j = 0 iff i = 1
 806  *       k = [1, 256]
 807  * Special case: j = 0, i = 1: Divisor = 2 / 5
 808  *
 809  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 810  * are:
 811  *      Case 1:         2^n, n = [0, 23]
 812  *      Case 2:         2^24 * 2 / 5 (0x666666)
 813  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 814  *
 815  * In all cases the lowest possible value is better.
 816  *
 817  * The function calculates parameters for all cases and chooses the one closest
 818  * to the asked baud rate.
 819  */
 820 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 821 {
 822         unsigned long xtal = 200000000;
 823         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 824                                                    see (2) */
 825                                                 /* case 3 */
 826         unsigned long fref1 = fref / 2;         /* case 1 */
 827         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 828         unsigned long scale;
 829         unsigned long q, q1, q2;
 830         long r, r1, r2;
 831         u32 mul;
 832
 833         /* Case 1 */
 834
 835         /* Set initial value for DDS_CLK_RATE */
 836         mul = (1 << 24) >> 1;
 837
 838         /* Calculate initial quot */
 839         q1 = DIV_ROUND_UP(fref1, rate);
 840
 841         /* Scale q1 if it's too big */
 842         if (q1 > 256) {
 843                 /* Scale q1 to range [1, 512] */
 844                 scale = fls_long(q1 - 1);
 845                 if (scale > 9) {
 846                         q1 >>= scale - 9;
 847                         mul >>= scale - 9;
 848                 }
 849
 850                 /* Round the result if we have a remainder */
 851                 q1 += q1 & 1;
 852         }
 853
 854         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 855         scale = __ffs(q1);
 856         q1 >>= scale;
 857         mul >>= scale;
 858
 859         /* Get the remainder */
 860         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 861
 862         /* Case 2 */
 863
 864         q2 = DIV_ROUND_UP(fref2, rate);
 865         r2 = abs(fref2 / q2 - rate);
 866
 867         /*
 868          * Choose the best between two: less remainder we have the better. We
 869          * can't go case 2 if q2 is greater than 256 since SCR register can
 870          * hold only values 0 .. 255.
 871          */
 872         if (r2 >= r1 || q2 > 256) {
 873                 /* case 1 is better */
 874                 r = r1;
 875                 q = q1;
 876         } else {
 877                 /* case 2 is better */
 878                 r = r2;
 879                 q = q2;
 880                 mul = (1 << 24) * 2 / 5;
 881         }
 882
 883         /* Check case 3 only if the divisor is big enough */
 884         if (fref / rate >= 80) {
 885                 u64 fssp;
 886                 u32 m;
 887
 888                 /* Calculate initial quot */
 889                 q1 = DIV_ROUND_UP(fref, rate);
 890                 m = (1 << 24) / q1;
 891
 892                 /* Get the remainder */
 893                 fssp = (u64)fref * m;
 894                 do_div(fssp, 1 << 24);
 895                 r1 = abs(fssp - rate);
 896
 897                 /* Choose this one if it suits better */
 898                 if (r1 < r) {
 899                         /* case 3 is better */
 900                         q = 1;
 901                         mul = m;
 902                 }
 903         }
 904
 905         *dds = mul;
 906         return q - 1;
 907 }
 908
 909 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 910 {
 911         unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 912         const struct ssp_device *ssp = drv_data->ssp;
 913
 914         rate = min_t(int, ssp_clk, rate);
 915
 916         /*
 917          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 918          * that the SSP transmission rate can be greater than the device rate
 919          */
 920         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 921                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 922         else
 923                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 924 }
 925
 926 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 927                                            int rate)
 928 {
 929         struct chip_data *chip =
 930                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 931         unsigned int clk_div;
 932
 933         switch (drv_data->ssp_type) {
 934         case QUARK_X1000_SSP:
 935                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 936                 break;
 937         default:
 938                 clk_div = ssp_get_clk_div(drv_data, rate);
 939                 break;
 940         }
 941         return clk_div << 8;
 942 }
 943
 944 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 945                                struct spi_device *spi,
 946                                struct spi_transfer *xfer)
 947 {
 948         struct chip_data *chip = spi_get_ctldata(spi);
 949
 950         return chip->enable_dma &&
 951                xfer->len <= MAX_DMA_LEN &&
 952                xfer->len >= chip->dma_burst_size;
 953 }
 954
 955 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 956                                    struct spi_device *spi,
 957                                    struct spi_transfer *transfer)
 958 {
 959         struct driver_data *drv_data = spi_controller_get_devdata(controller);
 960         struct spi_message *message = controller->cur_msg;
 961         struct chip_data *chip = spi_get_ctldata(spi);
 962         u32 dma_thresh = chip->dma_threshold;
 963         u32 dma_burst = chip->dma_burst_size;
 964         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 965         u32 clk_div;
 966         u8 bits;
 967         u32 speed;
 968         u32 cr0;
 969         u32 cr1;
 970         int err;
 971         int dma_mapped;
 972
 973         /* Check if we can DMA this transfer */
 974         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
 975
 976                 /* reject already-mapped transfers; PIO won't always work */
 977                 if (message->is_dma_mapped
 978                                 || transfer->rx_dma || transfer->tx_dma) {
 979                         dev_err(&spi->dev,
 980                                 "Mapped transfer length of %u is greater than %d\n",
 981                                 transfer->len, MAX_DMA_LEN);
 982                         return -EINVAL;
 983                 }
 984
 985                 /* warn ... we force this to PIO mode */
 986                 dev_warn_ratelimited(&spi->dev,
 987                                      "DMA disabled for transfer length %ld greater than %d\n",
 988                                      (long)transfer->len, MAX_DMA_LEN);
 989         }
 990
 991         /* Setup the transfer state based on the type of transfer */
 992         if (pxa2xx_spi_flush(drv_data) == 0) {
 993                 dev_err(&spi->dev, "Flush failed\n");
 994                 return -EIO;
 995         }
 996         drv_data->n_bytes = chip->n_bytes;
 997         drv_data->tx = (void *)transfer->tx_buf;
 998         drv_data->tx_end = drv_data->tx + transfer->len;
 999         drv_data->rx = transfer->rx_buf;
1000         drv_data->rx_end = drv_data->rx + transfer->len;
1001         drv_data->write = drv_data->tx ? chip->write : null_writer;
1002         drv_data->read = drv_data->rx ? chip->read : null_reader;
1003
1004         /* Change speed and bit per word on a per transfer */
1005         bits = transfer->bits_per_word;
1006         speed = transfer->speed_hz;
1007
1008         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1009
1010         if (bits <= 8) {
1011                 drv_data->n_bytes = 1;
1012                 drv_data->read = drv_data->read != null_reader ?
1013                                         u8_reader : null_reader;
1014                 drv_data->write = drv_data->write != null_writer ?
1015                                         u8_writer : null_writer;
1016         } else if (bits <= 16) {
1017                 drv_data->n_bytes = 2;
1018                 drv_data->read = drv_data->read != null_reader ?
1019                                         u16_reader : null_reader;
1020                 drv_data->write = drv_data->write != null_writer ?
1021                                         u16_writer : null_writer;
1022         } else if (bits <= 32) {
1023                 drv_data->n_bytes = 4;
1024                 drv_data->read = drv_data->read != null_reader ?
1025                                         u32_reader : null_reader;
1026                 drv_data->write = drv_data->write != null_writer ?
1027                                         u32_writer : null_writer;
1028         }
1029         /*
1030          * if bits/word is changed in dma mode, then must check the
1031          * thresholds and burst also
1032          */
1033         if (chip->enable_dma) {
1034                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1035                                                 spi,
1036                                                 bits, &dma_burst,
1037                                                 &dma_thresh))
1038                         dev_warn_ratelimited(&spi->dev,
1039                                              "DMA burst size reduced to match bits_per_word\n");
1040         }
1041
1042         dma_mapped = controller->can_dma &&
1043                      controller->can_dma(controller, spi, transfer) &&
1044                      controller->cur_msg_mapped;
1045         if (dma_mapped) {
1046
1047                 /* Ensure we have the correct interrupt handler */
1048                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1049
1050                 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1051                 if (err)
1052                         return err;
1053
1054                 /* Clear status and start DMA engine */
1055                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1056                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1057
1058                 pxa2xx_spi_dma_start(drv_data);
1059         } else {
1060                 /* Ensure we have the correct interrupt handler */
1061                 drv_data->transfer_handler = interrupt_transfer;
1062
1063                 /* Clear status  */
1064                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1065                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1066         }
1067
1068         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1069         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1070         if (!pxa25x_ssp_comp(drv_data))
1071                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1072                         controller->max_speed_hz
1073                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1074                         dma_mapped ? "DMA" : "PIO");
1075         else
1076                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1077                         controller->max_speed_hz / 2
1078                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1079                         dma_mapped ? "DMA" : "PIO");
1080
1081         if (is_lpss_ssp(drv_data)) {
1082                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1083                     != chip->lpss_rx_threshold)
1084                         pxa2xx_spi_write(drv_data, SSIRF,
1085                                          chip->lpss_rx_threshold);
1086                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1087                     != chip->lpss_tx_threshold)
1088                         pxa2xx_spi_write(drv_data, SSITF,
1089                                          chip->lpss_tx_threshold);
1090         }
1091
1092         if (is_quark_x1000_ssp(drv_data) &&
1093             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1094                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1095
1096         /* see if we need to reload the config registers */
1097         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1098             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1099             != (cr1 & change_mask)) {
1100                 /* stop the SSP, and update the other bits */
1101                 if (!is_mmp2_ssp(drv_data))
1102                         pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1103                 if (!pxa25x_ssp_comp(drv_data))
1104                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1105                 /* first set CR1 without interrupt and service enables */
1106                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1107                 /* restart the SSP */
1108                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1109
1110         } else {
1111                 if (!pxa25x_ssp_comp(drv_data))
1112                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1113         }
1114
1115         if (is_mmp2_ssp(drv_data)) {
1116                 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1117                                         & SSSR_TFL_MASK) >> 8;
1118
1119                 if (tx_level) {
1120                         /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1121                         dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1122                                                                 tx_level);
1123                         if (tx_level > transfer->len)
1124                                 tx_level = transfer->len;
1125                         drv_data->tx += tx_level;
1126                 }
1127         }
1128
1129         if (spi_controller_is_slave(controller)) {
1130                 while (drv_data->write(drv_data))
1131                         ;
1132                 if (drv_data->gpiod_ready) {
1133                         gpiod_set_value(drv_data->gpiod_ready, 1);
1134                         udelay(1);
1135                         gpiod_set_value(drv_data->gpiod_ready, 0);
1136                 }
1137         }
1138
1139         /*
1140          * Release the data by enabling service requests and interrupts,
1141          * without changing any mode bits
1142          */
1143         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1144
1145         return 1;
1146 }
1147
1148 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1149 {
1150         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1151
1152         /* Stop and reset SSP */
1153         write_SSSR_CS(drv_data, drv_data->clear_sr);
1154         reset_sccr1(drv_data);
1155         if (!pxa25x_ssp_comp(drv_data))
1156                 pxa2xx_spi_write(drv_data, SSTO, 0);
1157         pxa2xx_spi_flush(drv_data);
1158         pxa2xx_spi_off(drv_data);
1159
1160         dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1161
1162         drv_data->controller->cur_msg->status = -EINTR;
1163         spi_finalize_current_transfer(drv_data->controller);
1164
1165         return 0;
1166 }
1167
1168 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1169                                  struct spi_message *msg)
1170 {
1171         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1172
1173         /* Disable the SSP */
1174         pxa2xx_spi_off(drv_data);
1175         /* Clear and disable interrupts and service requests */
1176         write_SSSR_CS(drv_data, drv_data->clear_sr);
1177         pxa2xx_spi_write(drv_data, SSCR1,
1178                          pxa2xx_spi_read(drv_data, SSCR1)
1179                          & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1180         if (!pxa25x_ssp_comp(drv_data))
1181                 pxa2xx_spi_write(drv_data, SSTO, 0);
1182
1183         /*
1184          * Stop the DMA if running. Note DMA callback handler may have unset
1185          * the dma_running already, which is fine as stopping is not needed
1186          * then but we shouldn't rely this flag for anything else than
1187          * stopping. For instance to differentiate between PIO and DMA
1188          * transfers.
1189          */
1190         if (atomic_read(&drv_data->dma_running))
1191                 pxa2xx_spi_dma_stop(drv_data);
1192 }
1193
1194 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1195 {
1196         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1197
1198         /* Disable the SSP now */
1199         pxa2xx_spi_off(drv_data);
1200
1201         return 0;
1202 }
1203
1204 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1205                     struct pxa2xx_spi_chip *chip_info)
1206 {
1207         struct driver_data *drv_data =
1208                 spi_controller_get_devdata(spi->controller);
1209         struct gpio_desc *gpiod;
1210         int err = 0;
1211
1212         if (chip == NULL)
1213                 return 0;
1214
1215         if (drv_data->cs_gpiods) {
1216                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1217                 if (gpiod) {
1218                         chip->gpiod_cs = gpiod;
1219                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1220                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1221                 }
1222
1223                 return 0;
1224         }
1225
1226         if (chip_info == NULL)
1227                 return 0;
1228
1229         /* NOTE: setup() can be called multiple times, possibly with
1230          * different chip_info, release previously requested GPIO
1231          */
1232         if (chip->gpiod_cs) {
1233                 gpiod_put(chip->gpiod_cs);
1234                 chip->gpiod_cs = NULL;
1235         }
1236
1237         /* If (*cs_control) is provided, ignore GPIO chip select */
1238         if (chip_info->cs_control) {
1239                 chip->cs_control = chip_info->cs_control;
1240                 return 0;
1241         }
1242
1243         if (gpio_is_valid(chip_info->gpio_cs)) {
1244                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1245                 if (err) {
1246                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1247                                 chip_info->gpio_cs);
1248                         return err;
1249                 }
1250
1251                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1252                 chip->gpiod_cs = gpiod;
1253                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1254
1255                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1256         }
1257
1258         return err;
1259 }
1260
1261 static int setup(struct spi_device *spi)
1262 {
1263         struct pxa2xx_spi_chip *chip_info;
1264         struct chip_data *chip;
1265         const struct lpss_config *config;
1266         struct driver_data *drv_data =
1267                 spi_controller_get_devdata(spi->controller);
1268         uint tx_thres, tx_hi_thres, rx_thres;
1269
1270         switch (drv_data->ssp_type) {
1271         case QUARK_X1000_SSP:
1272                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1273                 tx_hi_thres = 0;
1274                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1275                 break;
1276         case CE4100_SSP:
1277                 tx_thres = TX_THRESH_CE4100_DFLT;
1278                 tx_hi_thres = 0;
1279                 rx_thres = RX_THRESH_CE4100_DFLT;
1280                 break;
1281         case LPSS_LPT_SSP:
1282         case LPSS_BYT_SSP:
1283         case LPSS_BSW_SSP:
1284         case LPSS_SPT_SSP:
1285         case LPSS_BXT_SSP:
1286         case LPSS_CNL_SSP:
1287                 config = lpss_get_config(drv_data);
1288                 tx_thres = config->tx_threshold_lo;
1289                 tx_hi_thres = config->tx_threshold_hi;
1290                 rx_thres = config->rx_threshold;
1291                 break;
1292         default:
1293                 tx_hi_thres = 0;
1294                 if (spi_controller_is_slave(drv_data->controller)) {
1295                         tx_thres = 1;
1296                         rx_thres = 2;
1297                 } else {
1298                         tx_thres = TX_THRESH_DFLT;
1299                         rx_thres = RX_THRESH_DFLT;
1300                 }
1301                 break;
1302         }
1303
1304         /* Only alloc on first setup */
1305         chip = spi_get_ctldata(spi);
1306         if (!chip) {
1307                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1308                 if (!chip)
1309                         return -ENOMEM;
1310
1311                 if (drv_data->ssp_type == CE4100_SSP) {
1312                         if (spi->chip_select > 4) {
1313                                 dev_err(&spi->dev,
1314                                         "failed setup: cs number must not be > 4.\n");
1315                                 kfree(chip);
1316                                 return -EINVAL;
1317                         }
1318
1319                         chip->frm = spi->chip_select;
1320                 }
1321                 chip->enable_dma = drv_data->controller_info->enable_dma;
1322                 chip->timeout = TIMOUT_DFLT;
1323         }
1324
1325         /* protocol drivers may change the chip settings, so...
1326          * if chip_info exists, use it */
1327         chip_info = spi->controller_data;
1328
1329         /* chip_info isn't always needed */
1330         chip->cr1 = 0;
1331         if (chip_info) {
1332                 if (chip_info->timeout)
1333                         chip->timeout = chip_info->timeout;
1334                 if (chip_info->tx_threshold)
1335                         tx_thres = chip_info->tx_threshold;
1336                 if (chip_info->tx_hi_threshold)
1337                         tx_hi_thres = chip_info->tx_hi_threshold;
1338                 if (chip_info->rx_threshold)
1339                         rx_thres = chip_info->rx_threshold;
1340                 chip->dma_threshold = 0;
1341                 if (chip_info->enable_loopback)
1342                         chip->cr1 = SSCR1_LBM;
1343         }
1344         if (spi_controller_is_slave(drv_data->controller)) {
1345                 chip->cr1 |= SSCR1_SCFR;
1346                 chip->cr1 |= SSCR1_SCLKDIR;
1347                 chip->cr1 |= SSCR1_SFRMDIR;
1348                 chip->cr1 |= SSCR1_SPH;
1349         }
1350
1351         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1352         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1353                                 | SSITF_TxHiThresh(tx_hi_thres);
1354
1355         /* set dma burst and threshold outside of chip_info path so that if
1356          * chip_info goes away after setting chip->enable_dma, the
1357          * burst and threshold can still respond to changes in bits_per_word */
1358         if (chip->enable_dma) {
1359                 /* set up legal burst and threshold for dma */
1360                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1361                                                 spi->bits_per_word,
1362                                                 &chip->dma_burst_size,
1363                                                 &chip->dma_threshold)) {
1364                         dev_warn(&spi->dev,
1365                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1366                 }
1367                 dev_dbg(&spi->dev,
1368                         "in setup: DMA burst size set to %u\n",
1369                         chip->dma_burst_size);
1370         }
1371
1372         switch (drv_data->ssp_type) {
1373         case QUARK_X1000_SSP:
1374                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1375                                    & QUARK_X1000_SSCR1_RFT)
1376                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1377                                    & QUARK_X1000_SSCR1_TFT);
1378                 break;
1379         case CE4100_SSP:
1380                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1381                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1382                 break;
1383         default:
1384                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1385                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1386                 break;
1387         }
1388
1389         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1390         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1391                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1392
1393         if (spi->mode & SPI_LOOP)
1394                 chip->cr1 |= SSCR1_LBM;
1395
1396         if (spi->bits_per_word <= 8) {
1397                 chip->n_bytes = 1;
1398                 chip->read = u8_reader;
1399                 chip->write = u8_writer;
1400         } else if (spi->bits_per_word <= 16) {
1401                 chip->n_bytes = 2;
1402                 chip->read = u16_reader;
1403                 chip->write = u16_writer;
1404         } else if (spi->bits_per_word <= 32) {
1405                 chip->n_bytes = 4;
1406                 chip->read = u32_reader;
1407                 chip->write = u32_writer;
1408         }
1409
1410         spi_set_ctldata(spi, chip);
1411
1412         if (drv_data->ssp_type == CE4100_SSP)
1413                 return 0;
1414
1415         return setup_cs(spi, chip, chip_info);
1416 }
1417
1418 static void cleanup(struct spi_device *spi)
1419 {
1420         struct chip_data *chip = spi_get_ctldata(spi);
1421         struct driver_data *drv_data =
1422                 spi_controller_get_devdata(spi->controller);
1423
1424         if (!chip)
1425                 return;
1426
1427         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1428             chip->gpiod_cs)
1429                 gpiod_put(chip->gpiod_cs);
1430
1431         kfree(chip);
1432 }
1433
1434 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1435         { "INT33C0", LPSS_LPT_SSP },
1436         { "INT33C1", LPSS_LPT_SSP },
1437         { "INT3430", LPSS_LPT_SSP },
1438         { "INT3431", LPSS_LPT_SSP },
1439         { "80860F0E", LPSS_BYT_SSP },
1440         { "8086228E", LPSS_BSW_SSP },
1441         { },
1442 };
1443 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1444
1445 /*
1446  * PCI IDs of compound devices that integrate both host controller and private
1447  * integrated DMA engine. Please note these are not used in module
1448  * autoloading and probing in this module but matching the LPSS SSP type.
1449  */
1450 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1451         /* SPT-LP */
1452         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1453         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1454         /* SPT-H */
1455         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1456         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1457         /* KBL-H */
1458         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1459         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1460         /* CML-V */
1461         { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1462         { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1463         /* BXT A-Step */
1464         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1465         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1466         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1467         /* BXT B-Step */
1468         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1469         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1470         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1471         /* GLK */
1472         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1473         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1474         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1475         /* ICL-LP */
1476         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1477         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1478         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1479         /* EHL */
1480         { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1481         { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1482         { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1483         /* JSL */
1484         { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1485         { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1486         { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1487         /* APL */
1488         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1489         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1490         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1491         /* CNL-LP */
1492         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1493         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1494         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1495         /* CNL-H */
1496         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1497         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1498         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1499         /* CML-LP */
1500         { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1501         { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1502         { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1503         /* CML-H */
1504         { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1505         { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1506         { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1507         /* TGL-LP */
1508         { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1509         { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1510         { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1511         { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1512         { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1513         { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1514         { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1515         { },
1516 };
1517
1518 static const struct of_device_id pxa2xx_spi_of_match[] = {
1519         { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1520         {},
1521 };
1522 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1523
1524 #ifdef CONFIG_ACPI
1525
1526 static int pxa2xx_spi_get_port_id(struct device *dev)
1527 {
1528         struct acpi_device *adev;
1529         unsigned int devid;
1530         int port_id = -1;
1531
1532         adev = ACPI_COMPANION(dev);
1533         if (adev && adev->pnp.unique_id &&
1534             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1535                 port_id = devid;
1536         return port_id;
1537 }
1538
1539 #else /* !CONFIG_ACPI */
1540
1541 static int pxa2xx_spi_get_port_id(struct device *dev)
1542 {
1543         return -1;
1544 }
1545
1546 #endif /* CONFIG_ACPI */
1547
1548
1549 #ifdef CONFIG_PCI
1550
1551 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1552 {
1553         return param == chan->device->dev;
1554 }
1555
1556 #endif /* CONFIG_PCI */
1557
1558 static struct pxa2xx_spi_controller *
1559 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1560 {
1561         struct pxa2xx_spi_controller *pdata;
1562         struct ssp_device *ssp;
1563         struct resource *res;
1564         struct device *parent = pdev->dev.parent;
1565         struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1566         const struct pci_device_id *pcidev_id = NULL;
1567         enum pxa_ssp_type type;
1568         const void *match;
1569
1570         if (pcidev)
1571                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1572
1573         match = device_get_match_data(&pdev->dev);
1574         if (match)
1575                 type = (enum pxa_ssp_type)match;
1576         else if (pcidev_id)
1577                 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1578         else
1579                 return ERR_PTR(-EINVAL);
1580
1581         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1582         if (!pdata)
1583                 return ERR_PTR(-ENOMEM);
1584
1585         ssp = &pdata->ssp;
1586
1587         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1588         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1589         if (IS_ERR(ssp->mmio_base))
1590                 return ERR_CAST(ssp->mmio_base);
1591
1592         ssp->phys_base = res->start;
1593
1594 #ifdef CONFIG_PCI
1595         if (pcidev_id) {
1596                 pdata->tx_param = parent;
1597                 pdata->rx_param = parent;
1598                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1599         }
1600 #endif
1601
1602         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1603         if (IS_ERR(ssp->clk))
1604                 return ERR_CAST(ssp->clk);
1605
1606         ssp->irq = platform_get_irq(pdev, 0);
1607         if (ssp->irq < 0)
1608                 return ERR_PTR(ssp->irq);
1609
1610         ssp->type = type;
1611         ssp->dev = &pdev->dev;
1612         ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1613
1614         pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1615         pdata->num_chipselect = 1;
1616         pdata->enable_dma = true;
1617         pdata->dma_burst_size = 1;
1618
1619         return pdata;
1620 }
1621
1622 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1623                                       unsigned int cs)
1624 {
1625         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1626
1627         if (has_acpi_companion(&drv_data->pdev->dev)) {
1628                 switch (drv_data->ssp_type) {
1629                 /*
1630                  * For Atoms the ACPI DeviceSelection used by the Windows
1631                  * driver starts from 1 instead of 0 so translate it here
1632                  * to match what Linux expects.
1633                  */
1634                 case LPSS_BYT_SSP:
1635                 case LPSS_BSW_SSP:
1636                         return cs - 1;
1637
1638                 default:
1639                         break;
1640                 }
1641         }
1642
1643         return cs;
1644 }
1645
1646 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1647 {
1648         return MAX_DMA_LEN;
1649 }
1650
1651 static int pxa2xx_spi_probe(struct platform_device *pdev)
1652 {
1653         struct device *dev = &pdev->dev;
1654         struct pxa2xx_spi_controller *platform_info;
1655         struct spi_controller *controller;
1656         struct driver_data *drv_data;
1657         struct ssp_device *ssp;
1658         const struct lpss_config *config;
1659         int status, count;
1660         u32 tmp;
1661
1662         platform_info = dev_get_platdata(dev);
1663         if (!platform_info) {
1664                 platform_info = pxa2xx_spi_init_pdata(pdev);
1665                 if (IS_ERR(platform_info)) {
1666                         dev_err(&pdev->dev, "missing platform data\n");
1667                         return PTR_ERR(platform_info);
1668                 }
1669         }
1670
1671         ssp = pxa_ssp_request(pdev->id, pdev->name);
1672         if (!ssp)
1673                 ssp = &platform_info->ssp;
1674
1675         if (!ssp->mmio_base) {
1676                 dev_err(&pdev->dev, "failed to get ssp\n");
1677                 return -ENODEV;
1678         }
1679
1680         if (platform_info->is_slave)
1681                 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1682         else
1683                 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1684
1685         if (!controller) {
1686                 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1687                 pxa_ssp_free(ssp);
1688                 return -ENOMEM;
1689         }
1690         drv_data = spi_controller_get_devdata(controller);
1691         drv_data->controller = controller;
1692         drv_data->controller_info = platform_info;
1693         drv_data->pdev = pdev;
1694         drv_data->ssp = ssp;
1695
1696         controller->dev.of_node = pdev->dev.of_node;
1697         /* the spi->mode bits understood by this driver: */
1698         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1699
1700         controller->bus_num = ssp->port_id;
1701         controller->dma_alignment = DMA_ALIGNMENT;
1702         controller->cleanup = cleanup;
1703         controller->setup = setup;
1704         controller->set_cs = pxa2xx_spi_set_cs;
1705         controller->transfer_one = pxa2xx_spi_transfer_one;
1706         controller->slave_abort = pxa2xx_spi_slave_abort;
1707         controller->handle_err = pxa2xx_spi_handle_err;
1708         controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1709         controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1710         controller->auto_runtime_pm = true;
1711         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1712
1713         drv_data->ssp_type = ssp->type;
1714
1715         drv_data->ioaddr = ssp->mmio_base;
1716         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1717         if (pxa25x_ssp_comp(drv_data)) {
1718                 switch (drv_data->ssp_type) {
1719                 case QUARK_X1000_SSP:
1720                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1721                         break;
1722                 default:
1723                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1724                         break;
1725                 }
1726
1727                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1728                 drv_data->dma_cr1 = 0;
1729                 drv_data->clear_sr = SSSR_ROR;
1730                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1731         } else {
1732                 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1733                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1734                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1735                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1736                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1737                                                 | SSSR_ROR | SSSR_TUR;
1738         }
1739
1740         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1741                         drv_data);
1742         if (status < 0) {
1743                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1744                 goto out_error_controller_alloc;
1745         }
1746
1747         /* Setup DMA if requested */
1748         if (platform_info->enable_dma) {
1749                 status = pxa2xx_spi_dma_setup(drv_data);
1750                 if (status) {
1751                         dev_warn(dev, "no DMA channels available, using PIO\n");
1752                         platform_info->enable_dma = false;
1753                 } else {
1754                         controller->can_dma = pxa2xx_spi_can_dma;
1755                         controller->max_dma_len = MAX_DMA_LEN;
1756                         controller->max_transfer_size =
1757                                 pxa2xx_spi_max_dma_transfer_size;
1758                 }
1759         }
1760
1761         /* Enable SOC clock */
1762         status = clk_prepare_enable(ssp->clk);
1763         if (status)
1764                 goto out_error_dma_irq_alloc;
1765
1766         controller->max_speed_hz = clk_get_rate(ssp->clk);
1767         /*
1768          * Set minimum speed for all other platforms than Intel Quark which is
1769          * able do under 1 Hz transfers.
1770          */
1771         if (!pxa25x_ssp_comp(drv_data))
1772                 controller->min_speed_hz =
1773                         DIV_ROUND_UP(controller->max_speed_hz, 4096);
1774         else if (!is_quark_x1000_ssp(drv_data))
1775                 controller->min_speed_hz =
1776                         DIV_ROUND_UP(controller->max_speed_hz, 512);
1777
1778         /* Load default SSP configuration */
1779         pxa2xx_spi_write(drv_data, SSCR0, 0);
1780         switch (drv_data->ssp_type) {
1781         case QUARK_X1000_SSP:
1782                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1783                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1784                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1785
1786                 /* using the Motorola SPI protocol and use 8 bit frame */
1787                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1788                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1789                 break;
1790         case CE4100_SSP:
1791                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1792                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1793                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1794                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1795                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1796                 break;
1797         default:
1798
1799                 if (spi_controller_is_slave(controller)) {
1800                         tmp = SSCR1_SCFR |
1801                               SSCR1_SCLKDIR |
1802                               SSCR1_SFRMDIR |
1803                               SSCR1_RxTresh(2) |
1804                               SSCR1_TxTresh(1) |
1805                               SSCR1_SPH;
1806                 } else {
1807                         tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1808                               SSCR1_TxTresh(TX_THRESH_DFLT);
1809                 }
1810                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1811                 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1812                 if (!spi_controller_is_slave(controller))
1813                         tmp |= SSCR0_SCR(2);
1814                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1815                 break;
1816         }
1817
1818         if (!pxa25x_ssp_comp(drv_data))
1819                 pxa2xx_spi_write(drv_data, SSTO, 0);
1820
1821         if (!is_quark_x1000_ssp(drv_data))
1822                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1823
1824         if (is_lpss_ssp(drv_data)) {
1825                 lpss_ssp_setup(drv_data);
1826                 config = lpss_get_config(drv_data);
1827                 if (config->reg_capabilities >= 0) {
1828                         tmp = __lpss_ssp_read_priv(drv_data,
1829                                                    config->reg_capabilities);
1830                         tmp &= LPSS_CAPS_CS_EN_MASK;
1831                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1832                         platform_info->num_chipselect = ffz(tmp);
1833                 } else if (config->cs_num) {
1834                         platform_info->num_chipselect = config->cs_num;
1835                 }
1836         }
1837         controller->num_chipselect = platform_info->num_chipselect;
1838
1839         count = gpiod_count(&pdev->dev, "cs");
1840         if (count > 0) {
1841                 int i;
1842
1843                 controller->num_chipselect = max_t(int, count,
1844                         controller->num_chipselect);
1845
1846                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1847                         controller->num_chipselect, sizeof(struct gpio_desc *),
1848                         GFP_KERNEL);
1849                 if (!drv_data->cs_gpiods) {
1850                         status = -ENOMEM;
1851                         goto out_error_clock_enabled;
1852                 }
1853
1854                 for (i = 0; i < controller->num_chipselect; i++) {
1855                         struct gpio_desc *gpiod;
1856
1857                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1858                         if (IS_ERR(gpiod)) {
1859                                 /* Means use native chip select */
1860                                 if (PTR_ERR(gpiod) == -ENOENT)
1861                                         continue;
1862
1863                                 status = PTR_ERR(gpiod);
1864                                 goto out_error_clock_enabled;
1865                         } else {
1866                                 drv_data->cs_gpiods[i] = gpiod;
1867                         }
1868                 }
1869         }
1870
1871         if (platform_info->is_slave) {
1872                 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1873                                                 "ready", GPIOD_OUT_LOW);
1874                 if (IS_ERR(drv_data->gpiod_ready)) {
1875                         status = PTR_ERR(drv_data->gpiod_ready);
1876                         goto out_error_clock_enabled;
1877                 }
1878         }
1879
1880         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1881         pm_runtime_use_autosuspend(&pdev->dev);
1882         pm_runtime_set_active(&pdev->dev);
1883         pm_runtime_enable(&pdev->dev);
1884
1885         /* Register with the SPI framework */
1886         platform_set_drvdata(pdev, drv_data);
1887         status = devm_spi_register_controller(&pdev->dev, controller);
1888         if (status != 0) {
1889                 dev_err(&pdev->dev, "problem registering spi controller\n");
1890                 goto out_error_pm_runtime_enabled;
1891         }
1892
1893         return status;
1894
1895 out_error_pm_runtime_enabled:
1896         pm_runtime_put_noidle(&pdev->dev);
1897         pm_runtime_disable(&pdev->dev);
1898
1899 out_error_clock_enabled:
1900         clk_disable_unprepare(ssp->clk);
1901
1902 out_error_dma_irq_alloc:
1903         pxa2xx_spi_dma_release(drv_data);
1904         free_irq(ssp->irq, drv_data);
1905
1906 out_error_controller_alloc:
1907         spi_controller_put(controller);
1908         pxa_ssp_free(ssp);
1909         return status;
1910 }
1911
1912 static int pxa2xx_spi_remove(struct platform_device *pdev)
1913 {
1914         struct driver_data *drv_data = platform_get_drvdata(pdev);
1915         struct ssp_device *ssp = drv_data->ssp;
1916
1917         pm_runtime_get_sync(&pdev->dev);
1918
1919         /* Disable the SSP at the peripheral and SOC level */
1920         pxa2xx_spi_write(drv_data, SSCR0, 0);
1921         clk_disable_unprepare(ssp->clk);
1922
1923         /* Release DMA */
1924         if (drv_data->controller_info->enable_dma)
1925                 pxa2xx_spi_dma_release(drv_data);
1926
1927         pm_runtime_put_noidle(&pdev->dev);
1928         pm_runtime_disable(&pdev->dev);
1929
1930         /* Release IRQ */
1931         free_irq(ssp->irq, drv_data);
1932
1933         /* Release SSP */
1934         pxa_ssp_free(ssp);
1935
1936         return 0;
1937 }
1938
1939 #ifdef CONFIG_PM_SLEEP
1940 static int pxa2xx_spi_suspend(struct device *dev)
1941 {
1942         struct driver_data *drv_data = dev_get_drvdata(dev);
1943         struct ssp_device *ssp = drv_data->ssp;
1944         int status;
1945
1946         status = spi_controller_suspend(drv_data->controller);
1947         if (status != 0)
1948                 return status;
1949         pxa2xx_spi_write(drv_data, SSCR0, 0);
1950
1951         if (!pm_runtime_suspended(dev))
1952                 clk_disable_unprepare(ssp->clk);
1953
1954         return 0;
1955 }
1956
1957 static int pxa2xx_spi_resume(struct device *dev)
1958 {
1959         struct driver_data *drv_data = dev_get_drvdata(dev);
1960         struct ssp_device *ssp = drv_data->ssp;
1961         int status;
1962
1963         /* Enable the SSP clock */
1964         if (!pm_runtime_suspended(dev)) {
1965                 status = clk_prepare_enable(ssp->clk);
1966                 if (status)
1967                         return status;
1968         }
1969
1970         /* Start the queue running */
1971         return spi_controller_resume(drv_data->controller);
1972 }
1973 #endif
1974
1975 #ifdef CONFIG_PM
1976 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1977 {
1978         struct driver_data *drv_data = dev_get_drvdata(dev);
1979
1980         clk_disable_unprepare(drv_data->ssp->clk);
1981         return 0;
1982 }
1983
1984 static int pxa2xx_spi_runtime_resume(struct device *dev)
1985 {
1986         struct driver_data *drv_data = dev_get_drvdata(dev);
1987         int status;
1988
1989         status = clk_prepare_enable(drv_data->ssp->clk);
1990         return status;
1991 }
1992 #endif
1993
1994 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1995         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1996         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1997                            pxa2xx_spi_runtime_resume, NULL)
1998 };
1999
2000 static struct platform_driver driver = {
2001         .driver = {
2002                 .name   = "pxa2xx-spi",
2003                 .pm     = &pxa2xx_spi_pm_ops,
2004                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
2005                 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
2006         },
2007         .probe = pxa2xx_spi_probe,
2008         .remove = pxa2xx_spi_remove,
2009 };
2010
2011 static int __init pxa2xx_spi_init(void)
2012 {
2013         return platform_driver_register(&driver);
2014 }
2015 subsys_initcall(pxa2xx_spi_init);
2016
2017 static void __exit pxa2xx_spi_exit(void)
2018 {
2019         platform_driver_unregister(&driver);
2020 }
2021 module_exit(pxa2xx_spi_exit);
2022
2023 MODULE_SOFTDEP("pre: dw_dmac");