1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
7 #include <linux/acpi.h>
8 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/gpio.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/property.h>
28 #include <linux/slab.h>
30 #include <linux/spi/pxa2xx_spi.h>
31 #include <linux/spi/spi.h>
33 #include "spi-pxa2xx.h"
35 MODULE_AUTHOR("Stephen Street");
36 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
37 MODULE_LICENSE("GPL");
38 MODULE_ALIAS("platform:pxa2xx-spi");
40 #define TIMOUT_DFLT 1000
43 * For testing SSCR1 changes that require SSP restart, basically
44 * everything except the service and interrupt enables, the PXA270 developer
45 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
46 * list, but the PXA255 developer manual says all bits without really meaning
47 * the service and interrupt enables.
49 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
50 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
51 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
52 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
53 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
54 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
56 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
57 | QUARK_X1000_SSCR1_EFWR \
58 | QUARK_X1000_SSCR1_RFT \
59 | QUARK_X1000_SSCR1_TFT \
60 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
62 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
63 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
64 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
65 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
66 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
67 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
69 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
70 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
71 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
72 #define LPSS_CAPS_CS_EN_SHIFT 9
73 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
75 #define LPSS_PRIV_CLOCK_GATE 0x38
76 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
77 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
80 /* LPSS offset from drv_data->ioaddr */
82 /* Register offsets from drv_data->lpss_base or -1 */
91 /* Chip select control */
92 unsigned cs_sel_shift;
96 unsigned cs_clk_stays_gated : 1;
99 /* Keep these sorted with enum pxa_ssp_type */
100 static const struct lpss_config lpss_platforms[] = {
106 .reg_capabilities = -1,
108 .tx_threshold_lo = 160,
109 .tx_threshold_hi = 224,
116 .reg_capabilities = -1,
118 .tx_threshold_lo = 160,
119 .tx_threshold_hi = 224,
126 .reg_capabilities = -1,
128 .tx_threshold_lo = 160,
129 .tx_threshold_hi = 224,
131 .cs_sel_mask = 1 << 2,
139 .reg_capabilities = -1,
141 .tx_threshold_lo = 32,
142 .tx_threshold_hi = 56,
149 .reg_capabilities = 0xfc,
151 .tx_threshold_lo = 16,
152 .tx_threshold_hi = 48,
154 .cs_sel_mask = 3 << 8,
155 .cs_clk_stays_gated = true,
162 .reg_capabilities = 0xfc,
164 .tx_threshold_lo = 32,
165 .tx_threshold_hi = 56,
167 .cs_sel_mask = 3 << 8,
168 .cs_clk_stays_gated = true,
172 static inline const struct lpss_config
173 *lpss_get_config(const struct driver_data *drv_data)
175 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
178 static bool is_lpss_ssp(const struct driver_data *drv_data)
180 switch (drv_data->ssp_type) {
193 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
195 return drv_data->ssp_type == QUARK_X1000_SSP;
198 static bool is_mmp2_ssp(const struct driver_data *drv_data)
200 return drv_data->ssp_type == MMP2_SSP;
203 static bool is_mrfld_ssp(const struct driver_data *drv_data)
205 return drv_data->ssp_type == MRFLD_SSP;
208 static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
210 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
211 pxa2xx_spi_write(drv_data, reg, value & mask);
214 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
216 switch (drv_data->ssp_type) {
217 case QUARK_X1000_SSP:
218 return QUARK_X1000_SSCR1_CHANGE_MASK;
220 return CE4100_SSCR1_CHANGE_MASK;
222 return SSCR1_CHANGE_MASK;
227 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
229 switch (drv_data->ssp_type) {
230 case QUARK_X1000_SSP:
231 return RX_THRESH_QUARK_X1000_DFLT;
233 return RX_THRESH_CE4100_DFLT;
235 return RX_THRESH_DFLT;
239 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
243 switch (drv_data->ssp_type) {
244 case QUARK_X1000_SSP:
245 mask = QUARK_X1000_SSSR_TFL_MASK;
248 mask = CE4100_SSSR_TFL_MASK;
251 mask = SSSR_TFL_MASK;
255 return read_SSSR_bits(drv_data, mask) == mask;
258 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
263 switch (drv_data->ssp_type) {
264 case QUARK_X1000_SSP:
265 mask = QUARK_X1000_SSCR1_RFT;
268 mask = CE4100_SSCR1_RFT;
277 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
278 u32 *sccr1_reg, u32 threshold)
280 switch (drv_data->ssp_type) {
281 case QUARK_X1000_SSP:
282 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
285 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
288 *sccr1_reg |= SSCR1_RxTresh(threshold);
293 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
294 u32 clk_div, u8 bits)
296 switch (drv_data->ssp_type) {
297 case QUARK_X1000_SSP:
299 | QUARK_X1000_SSCR0_Motorola
300 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits);
304 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
305 | (bits > 16 ? SSCR0_EDSS : 0);
310 * Read and write LPSS SSP private registers. Caller must first check that
311 * is_lpss_ssp() returns true before these can be called.
313 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
315 WARN_ON(!drv_data->lpss_base);
316 return readl(drv_data->lpss_base + offset);
319 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
320 unsigned offset, u32 value)
322 WARN_ON(!drv_data->lpss_base);
323 writel(value, drv_data->lpss_base + offset);
327 * lpss_ssp_setup - perform LPSS SSP specific setup
328 * @drv_data: pointer to the driver private data
330 * Perform LPSS SSP specific setup. This function must be called first if
331 * one is going to use LPSS SSP private registers.
333 static void lpss_ssp_setup(struct driver_data *drv_data)
335 const struct lpss_config *config;
338 config = lpss_get_config(drv_data);
339 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
341 /* Enable software chip select control */
342 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
343 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
344 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
345 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
347 /* Enable multiblock DMA transfers */
348 if (drv_data->controller_info->enable_dma) {
349 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
351 if (config->reg_general >= 0) {
352 value = __lpss_ssp_read_priv(drv_data,
353 config->reg_general);
354 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
355 __lpss_ssp_write_priv(drv_data,
356 config->reg_general, value);
361 static void lpss_ssp_select_cs(struct spi_device *spi,
362 const struct lpss_config *config)
364 struct driver_data *drv_data =
365 spi_controller_get_devdata(spi->controller);
368 if (!config->cs_sel_mask)
371 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
373 cs = spi->chip_select;
374 cs <<= config->cs_sel_shift;
375 if (cs != (value & config->cs_sel_mask)) {
377 * When switching another chip select output active the
378 * output must be selected first and wait 2 ssp_clk cycles
379 * before changing state to active. Otherwise a short
380 * glitch will occur on the previous chip select since
381 * output select is latched but state control is not.
383 value &= ~config->cs_sel_mask;
385 __lpss_ssp_write_priv(drv_data,
386 config->reg_cs_ctrl, value);
388 (drv_data->controller->max_speed_hz / 2));
392 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
394 struct driver_data *drv_data =
395 spi_controller_get_devdata(spi->controller);
396 const struct lpss_config *config;
399 config = lpss_get_config(drv_data);
402 lpss_ssp_select_cs(spi, config);
404 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
406 value &= ~LPSS_CS_CONTROL_CS_HIGH;
408 value |= LPSS_CS_CONTROL_CS_HIGH;
409 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
410 if (config->cs_clk_stays_gated) {
414 * Changing CS alone when dynamic clock gating is on won't
415 * actually flip CS at that time. This ruins SPI transfers
416 * that specify delays, or have no data. Toggle the clock mode
417 * to force on briefly to poke the CS pin to move.
419 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
420 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
421 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
423 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
424 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
428 static void cs_assert(struct spi_device *spi)
430 struct driver_data *drv_data =
431 spi_controller_get_devdata(spi->controller);
433 if (drv_data->ssp_type == CE4100_SSP) {
434 pxa2xx_spi_write(drv_data, SSSR, spi->chip_select);
438 if (is_lpss_ssp(drv_data))
439 lpss_ssp_cs_control(spi, true);
442 static void cs_deassert(struct spi_device *spi)
444 struct driver_data *drv_data =
445 spi_controller_get_devdata(spi->controller);
446 unsigned long timeout;
448 if (drv_data->ssp_type == CE4100_SSP)
451 /* Wait until SSP becomes idle before deasserting the CS */
452 timeout = jiffies + msecs_to_jiffies(10);
453 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
454 !time_after(jiffies, timeout))
457 if (is_lpss_ssp(drv_data))
458 lpss_ssp_cs_control(spi, false);
461 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
469 int pxa2xx_spi_flush(struct driver_data *drv_data)
471 unsigned long limit = loops_per_jiffy << 1;
474 while (read_SSSR_bits(drv_data, SSSR_RNE))
475 pxa2xx_spi_read(drv_data, SSDR);
476 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
477 write_SSSR_CS(drv_data, SSSR_ROR);
482 static void pxa2xx_spi_off(struct driver_data *drv_data)
484 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
485 if (is_mmp2_ssp(drv_data))
488 pxa_ssp_disable(drv_data->ssp);
491 static int null_writer(struct driver_data *drv_data)
493 u8 n_bytes = drv_data->n_bytes;
495 if (pxa2xx_spi_txfifo_full(drv_data)
496 || (drv_data->tx == drv_data->tx_end))
499 pxa2xx_spi_write(drv_data, SSDR, 0);
500 drv_data->tx += n_bytes;
505 static int null_reader(struct driver_data *drv_data)
507 u8 n_bytes = drv_data->n_bytes;
509 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
510 pxa2xx_spi_read(drv_data, SSDR);
511 drv_data->rx += n_bytes;
514 return drv_data->rx == drv_data->rx_end;
517 static int u8_writer(struct driver_data *drv_data)
519 if (pxa2xx_spi_txfifo_full(drv_data)
520 || (drv_data->tx == drv_data->tx_end))
523 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
529 static int u8_reader(struct driver_data *drv_data)
531 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
532 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
536 return drv_data->rx == drv_data->rx_end;
539 static int u16_writer(struct driver_data *drv_data)
541 if (pxa2xx_spi_txfifo_full(drv_data)
542 || (drv_data->tx == drv_data->tx_end))
545 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
551 static int u16_reader(struct driver_data *drv_data)
553 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
554 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
558 return drv_data->rx == drv_data->rx_end;
561 static int u32_writer(struct driver_data *drv_data)
563 if (pxa2xx_spi_txfifo_full(drv_data)
564 || (drv_data->tx == drv_data->tx_end))
567 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
573 static int u32_reader(struct driver_data *drv_data)
575 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
576 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
580 return drv_data->rx == drv_data->rx_end;
583 static void reset_sccr1(struct driver_data *drv_data)
585 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
586 struct chip_data *chip;
588 if (drv_data->controller->cur_msg) {
589 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
590 threshold = chip->threshold;
595 switch (drv_data->ssp_type) {
596 case QUARK_X1000_SSP:
597 mask |= QUARK_X1000_SSCR1_RFT;
600 mask |= CE4100_SSCR1_RFT;
607 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
610 static void int_stop_and_reset(struct driver_data *drv_data)
612 /* Clear and disable interrupts */
613 write_SSSR_CS(drv_data, drv_data->clear_sr);
614 reset_sccr1(drv_data);
615 if (pxa25x_ssp_comp(drv_data))
618 pxa2xx_spi_write(drv_data, SSTO, 0);
621 static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
623 int_stop_and_reset(drv_data);
624 pxa2xx_spi_flush(drv_data);
625 pxa2xx_spi_off(drv_data);
627 dev_err(drv_data->ssp->dev, "%s\n", msg);
629 drv_data->controller->cur_msg->status = err;
630 spi_finalize_current_transfer(drv_data->controller);
633 static void int_transfer_complete(struct driver_data *drv_data)
635 int_stop_and_reset(drv_data);
637 spi_finalize_current_transfer(drv_data->controller);
640 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
644 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
645 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
646 irq_status &= ~SSSR_TFS;
648 if (irq_status & SSSR_ROR) {
649 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
653 if (irq_status & SSSR_TUR) {
654 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
658 if (irq_status & SSSR_TINT) {
659 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
660 if (drv_data->read(drv_data)) {
661 int_transfer_complete(drv_data);
666 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
668 if (drv_data->read(drv_data)) {
669 int_transfer_complete(drv_data);
672 } while (drv_data->write(drv_data));
674 if (drv_data->read(drv_data)) {
675 int_transfer_complete(drv_data);
679 if (drv_data->tx == drv_data->tx_end) {
683 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
684 sccr1_reg &= ~SSCR1_TIE;
687 * PXA25x_SSP has no timeout, set up Rx threshold for
688 * the remaining Rx bytes.
690 if (pxa25x_ssp_comp(drv_data)) {
693 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
695 bytes_left = drv_data->rx_end - drv_data->rx;
696 switch (drv_data->n_bytes) {
705 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
706 if (rx_thre > bytes_left)
707 rx_thre = bytes_left;
709 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
711 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
714 /* We did something */
718 static void handle_bad_msg(struct driver_data *drv_data)
720 int_stop_and_reset(drv_data);
721 pxa2xx_spi_off(drv_data);
723 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
726 static irqreturn_t ssp_int(int irq, void *dev_id)
728 struct driver_data *drv_data = dev_id;
730 u32 mask = drv_data->mask_sr;
734 * The IRQ might be shared with other peripherals so we must first
735 * check that are we RPM suspended or not. If we are we assume that
736 * the IRQ was not for us (we shouldn't be RPM suspended when the
737 * interrupt is enabled).
739 if (pm_runtime_suspended(drv_data->ssp->dev))
743 * If the device is not yet in RPM suspended state and we get an
744 * interrupt that is meant for another device, check if status bits
745 * are all set to one. That means that the device is already
748 status = pxa2xx_spi_read(drv_data, SSSR);
752 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
754 /* Ignore possible writes if we don't need to write */
755 if (!(sccr1_reg & SSCR1_TIE))
758 /* Ignore RX timeout interrupt if it is disabled */
759 if (!(sccr1_reg & SSCR1_TINTE))
762 if (!(status & mask))
765 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
766 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
768 if (!drv_data->controller->cur_msg) {
769 handle_bad_msg(drv_data);
774 return drv_data->transfer_handler(drv_data);
778 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
779 * input frequency by fractions of 2^24. It also has a divider by 5.
781 * There are formulas to get baud rate value for given input frequency and
782 * divider parameters, such as DDS_CLK_RATE and SCR:
786 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
787 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
789 * DDS_CLK_RATE either 2^n or 2^n / 5.
790 * SCR is in range 0 .. 255
792 * Divisor = 5^i * 2^j * 2 * k
793 * i = [0, 1] i = 1 iff j = 0 or j > 3
794 * j = [0, 23] j = 0 iff i = 1
796 * Special case: j = 0, i = 1: Divisor = 2 / 5
798 * Accordingly to the specification the recommended values for DDS_CLK_RATE
800 * Case 1: 2^n, n = [0, 23]
801 * Case 2: 2^24 * 2 / 5 (0x666666)
802 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
804 * In all cases the lowest possible value is better.
806 * The function calculates parameters for all cases and chooses the one closest
807 * to the asked baud rate.
809 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
811 unsigned long xtal = 200000000;
812 unsigned long fref = xtal / 2; /* mandatory division by 2,
815 unsigned long fref1 = fref / 2; /* case 1 */
816 unsigned long fref2 = fref * 2 / 5; /* case 2 */
818 unsigned long q, q1, q2;
824 /* Set initial value for DDS_CLK_RATE */
825 mul = (1 << 24) >> 1;
827 /* Calculate initial quot */
828 q1 = DIV_ROUND_UP(fref1, rate);
830 /* Scale q1 if it's too big */
832 /* Scale q1 to range [1, 512] */
833 scale = fls_long(q1 - 1);
839 /* Round the result if we have a remainder */
843 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
848 /* Get the remainder */
849 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
853 q2 = DIV_ROUND_UP(fref2, rate);
854 r2 = abs(fref2 / q2 - rate);
857 * Choose the best between two: less remainder we have the better. We
858 * can't go case 2 if q2 is greater than 256 since SCR register can
859 * hold only values 0 .. 255.
861 if (r2 >= r1 || q2 > 256) {
862 /* case 1 is better */
866 /* case 2 is better */
869 mul = (1 << 24) * 2 / 5;
872 /* Check case 3 only if the divisor is big enough */
873 if (fref / rate >= 80) {
877 /* Calculate initial quot */
878 q1 = DIV_ROUND_UP(fref, rate);
881 /* Get the remainder */
882 fssp = (u64)fref * m;
883 do_div(fssp, 1 << 24);
884 r1 = abs(fssp - rate);
886 /* Choose this one if it suits better */
888 /* case 3 is better */
898 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
900 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
901 const struct ssp_device *ssp = drv_data->ssp;
903 rate = min_t(int, ssp_clk, rate);
906 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
907 * that the SSP transmission rate can be greater than the device rate.
909 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
910 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
912 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
915 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
918 struct chip_data *chip =
919 spi_get_ctldata(drv_data->controller->cur_msg->spi);
920 unsigned int clk_div;
922 switch (drv_data->ssp_type) {
923 case QUARK_X1000_SSP:
924 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
927 clk_div = ssp_get_clk_div(drv_data, rate);
933 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
934 struct spi_device *spi,
935 struct spi_transfer *xfer)
937 struct chip_data *chip = spi_get_ctldata(spi);
939 return chip->enable_dma &&
940 xfer->len <= MAX_DMA_LEN &&
941 xfer->len >= chip->dma_burst_size;
944 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
945 struct spi_device *spi,
946 struct spi_transfer *transfer)
948 struct driver_data *drv_data = spi_controller_get_devdata(controller);
949 struct spi_message *message = controller->cur_msg;
950 struct chip_data *chip = spi_get_ctldata(spi);
951 u32 dma_thresh = chip->dma_threshold;
952 u32 dma_burst = chip->dma_burst_size;
953 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
962 /* Check if we can DMA this transfer */
963 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
965 /* Reject already-mapped transfers; PIO won't always work */
966 if (message->is_dma_mapped
967 || transfer->rx_dma || transfer->tx_dma) {
969 "Mapped transfer length of %u is greater than %d\n",
970 transfer->len, MAX_DMA_LEN);
974 /* Warn ... we force this to PIO mode */
975 dev_warn_ratelimited(&spi->dev,
976 "DMA disabled for transfer length %u greater than %d\n",
977 transfer->len, MAX_DMA_LEN);
980 /* Setup the transfer state based on the type of transfer */
981 if (pxa2xx_spi_flush(drv_data) == 0) {
982 dev_err(&spi->dev, "Flush failed\n");
985 drv_data->tx = (void *)transfer->tx_buf;
986 drv_data->tx_end = drv_data->tx + transfer->len;
987 drv_data->rx = transfer->rx_buf;
988 drv_data->rx_end = drv_data->rx + transfer->len;
990 /* Change speed and bit per word on a per transfer */
991 bits = transfer->bits_per_word;
992 speed = transfer->speed_hz;
994 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
997 drv_data->n_bytes = 1;
998 drv_data->read = drv_data->rx ? u8_reader : null_reader;
999 drv_data->write = drv_data->tx ? u8_writer : null_writer;
1000 } else if (bits <= 16) {
1001 drv_data->n_bytes = 2;
1002 drv_data->read = drv_data->rx ? u16_reader : null_reader;
1003 drv_data->write = drv_data->tx ? u16_writer : null_writer;
1004 } else if (bits <= 32) {
1005 drv_data->n_bytes = 4;
1006 drv_data->read = drv_data->rx ? u32_reader : null_reader;
1007 drv_data->write = drv_data->tx ? u32_writer : null_writer;
1010 * If bits per word is changed in DMA mode, then must check
1011 * the thresholds and burst also.
1013 if (chip->enable_dma) {
1014 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1018 dev_warn_ratelimited(&spi->dev,
1019 "DMA burst size reduced to match bits_per_word\n");
1022 dma_mapped = controller->can_dma &&
1023 controller->can_dma(controller, spi, transfer) &&
1024 controller->cur_msg_mapped;
1027 /* Ensure we have the correct interrupt handler */
1028 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1030 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1034 /* Clear status and start DMA engine */
1035 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1036 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1038 pxa2xx_spi_dma_start(drv_data);
1040 /* Ensure we have the correct interrupt handler */
1041 drv_data->transfer_handler = interrupt_transfer;
1044 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1045 write_SSSR_CS(drv_data, drv_data->clear_sr);
1048 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1049 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1050 if (!pxa25x_ssp_comp(drv_data))
1051 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1052 controller->max_speed_hz
1053 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1054 dma_mapped ? "DMA" : "PIO");
1056 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1057 controller->max_speed_hz / 2
1058 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1059 dma_mapped ? "DMA" : "PIO");
1061 if (is_lpss_ssp(drv_data)) {
1062 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1063 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1066 if (is_mrfld_ssp(drv_data)) {
1067 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT;
1070 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold);
1071 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold);
1073 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1076 if (is_quark_x1000_ssp(drv_data))
1077 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1080 if (!is_mmp2_ssp(drv_data))
1081 pxa_ssp_disable(drv_data->ssp);
1083 if (!pxa25x_ssp_comp(drv_data))
1084 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1086 /* First set CR1 without interrupt and service enables */
1087 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1089 /* See if we need to reload the configuration registers */
1090 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1092 /* Restart the SSP */
1093 pxa_ssp_enable(drv_data->ssp);
1095 if (is_mmp2_ssp(drv_data)) {
1096 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1099 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
1100 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
1101 if (tx_level > transfer->len)
1102 tx_level = transfer->len;
1103 drv_data->tx += tx_level;
1107 if (spi_controller_is_slave(controller)) {
1108 while (drv_data->write(drv_data))
1110 if (drv_data->gpiod_ready) {
1111 gpiod_set_value(drv_data->gpiod_ready, 1);
1113 gpiod_set_value(drv_data->gpiod_ready, 0);
1118 * Release the data by enabling service requests and interrupts,
1119 * without changing any mode bits.
1121 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1126 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1128 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1130 int_error_stop(drv_data, "transfer aborted", -EINTR);
1135 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1136 struct spi_message *msg)
1138 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1140 int_stop_and_reset(drv_data);
1142 /* Disable the SSP */
1143 pxa2xx_spi_off(drv_data);
1146 * Stop the DMA if running. Note DMA callback handler may have unset
1147 * the dma_running already, which is fine as stopping is not needed
1148 * then but we shouldn't rely this flag for anything else than
1149 * stopping. For instance to differentiate between PIO and DMA
1152 if (atomic_read(&drv_data->dma_running))
1153 pxa2xx_spi_dma_stop(drv_data);
1156 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1158 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1160 /* Disable the SSP now */
1161 pxa2xx_spi_off(drv_data);
1166 static void cleanup_cs(struct spi_device *spi)
1168 if (!gpio_is_valid(spi->cs_gpio))
1171 gpio_free(spi->cs_gpio);
1172 spi->cs_gpio = -ENOENT;
1175 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1176 struct pxa2xx_spi_chip *chip_info)
1178 struct driver_data *drv_data = spi_controller_get_devdata(spi->controller);
1183 if (chip_info == NULL)
1186 if (drv_data->ssp_type == CE4100_SSP)
1190 * NOTE: setup() can be called multiple times, possibly with
1191 * different chip_info, release previously requested GPIO.
1195 if (gpio_is_valid(chip_info->gpio_cs)) {
1196 int gpio = chip_info->gpio_cs;
1199 err = gpio_request(gpio, "SPI_CS");
1201 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", gpio);
1205 err = gpio_direction_output(gpio, !(spi->mode & SPI_CS_HIGH));
1211 spi->cs_gpio = gpio;
1217 static int setup(struct spi_device *spi)
1219 struct pxa2xx_spi_chip *chip_info;
1220 struct chip_data *chip;
1221 const struct lpss_config *config;
1222 struct driver_data *drv_data =
1223 spi_controller_get_devdata(spi->controller);
1224 uint tx_thres, tx_hi_thres, rx_thres;
1227 switch (drv_data->ssp_type) {
1228 case QUARK_X1000_SSP:
1229 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1231 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1234 tx_thres = TX_THRESH_MRFLD_DFLT;
1236 rx_thres = RX_THRESH_MRFLD_DFLT;
1239 tx_thres = TX_THRESH_CE4100_DFLT;
1241 rx_thres = RX_THRESH_CE4100_DFLT;
1249 config = lpss_get_config(drv_data);
1250 tx_thres = config->tx_threshold_lo;
1251 tx_hi_thres = config->tx_threshold_hi;
1252 rx_thres = config->rx_threshold;
1256 if (spi_controller_is_slave(drv_data->controller)) {
1260 tx_thres = TX_THRESH_DFLT;
1261 rx_thres = RX_THRESH_DFLT;
1266 /* Only allocate on the first setup */
1267 chip = spi_get_ctldata(spi);
1269 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1273 if (drv_data->ssp_type == CE4100_SSP) {
1274 if (spi->chip_select > 4) {
1276 "failed setup: cs number must not be > 4.\n");
1281 chip->enable_dma = drv_data->controller_info->enable_dma;
1282 chip->timeout = TIMOUT_DFLT;
1286 * Protocol drivers may change the chip settings, so...
1287 * if chip_info exists, use it.
1289 chip_info = spi->controller_data;
1291 /* chip_info isn't always needed */
1293 if (chip_info->timeout)
1294 chip->timeout = chip_info->timeout;
1295 if (chip_info->tx_threshold)
1296 tx_thres = chip_info->tx_threshold;
1297 if (chip_info->tx_hi_threshold)
1298 tx_hi_thres = chip_info->tx_hi_threshold;
1299 if (chip_info->rx_threshold)
1300 rx_thres = chip_info->rx_threshold;
1301 chip->dma_threshold = 0;
1305 if (spi_controller_is_slave(drv_data->controller)) {
1306 chip->cr1 |= SSCR1_SCFR;
1307 chip->cr1 |= SSCR1_SCLKDIR;
1308 chip->cr1 |= SSCR1_SFRMDIR;
1309 chip->cr1 |= SSCR1_SPH;
1312 if (is_lpss_ssp(drv_data)) {
1313 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1314 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) |
1315 SSITF_TxHiThresh(tx_hi_thres);
1318 if (is_mrfld_ssp(drv_data)) {
1319 chip->lpss_rx_threshold = rx_thres;
1320 chip->lpss_tx_threshold = tx_thres;
1324 * Set DMA burst and threshold outside of chip_info path so that if
1325 * chip_info goes away after setting chip->enable_dma, the burst and
1326 * threshold can still respond to changes in bits_per_word.
1328 if (chip->enable_dma) {
1329 /* Set up legal burst and threshold for DMA */
1330 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1332 &chip->dma_burst_size,
1333 &chip->dma_threshold)) {
1335 "in setup: DMA burst size reduced to match bits_per_word\n");
1338 "in setup: DMA burst size set to %u\n",
1339 chip->dma_burst_size);
1342 switch (drv_data->ssp_type) {
1343 case QUARK_X1000_SSP:
1344 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1345 & QUARK_X1000_SSCR1_RFT)
1346 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1347 & QUARK_X1000_SSCR1_TFT);
1350 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1351 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1354 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1355 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1359 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1360 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |
1361 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0);
1363 if (spi->mode & SPI_LOOP)
1364 chip->cr1 |= SSCR1_LBM;
1366 spi_set_ctldata(spi, chip);
1368 if (drv_data->ssp_type == CE4100_SSP)
1371 err = setup_cs(spi, chip, chip_info);
1378 static void cleanup(struct spi_device *spi)
1380 struct chip_data *chip = spi_get_ctldata(spi);
1387 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1388 { "INT33C0", LPSS_LPT_SSP },
1389 { "INT33C1", LPSS_LPT_SSP },
1390 { "INT3430", LPSS_LPT_SSP },
1391 { "INT3431", LPSS_LPT_SSP },
1392 { "80860F0E", LPSS_BYT_SSP },
1393 { "8086228E", LPSS_BSW_SSP },
1396 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1400 * PCI IDs of compound devices that integrate both host controller and private
1401 * integrated DMA engine. Please note these are not used in module
1402 * autoloading and probing in this module but matching the LPSS SSP type.
1404 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1406 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1407 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1409 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1410 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1412 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1413 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1415 { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1416 { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1418 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1419 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1420 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1422 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1423 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1424 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1426 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1427 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1428 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1430 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1431 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1432 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1434 { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1435 { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1436 { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1438 { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1439 { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1440 { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1442 { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
1443 { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
1444 { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
1445 { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
1447 { PCI_VDEVICE(INTEL, 0x51aa), LPSS_CNL_SSP },
1448 { PCI_VDEVICE(INTEL, 0x51ab), LPSS_CNL_SSP },
1449 { PCI_VDEVICE(INTEL, 0x51fb), LPSS_CNL_SSP },
1451 { PCI_VDEVICE(INTEL, 0x54aa), LPSS_CNL_SSP },
1452 { PCI_VDEVICE(INTEL, 0x54ab), LPSS_CNL_SSP },
1453 { PCI_VDEVICE(INTEL, 0x54fb), LPSS_CNL_SSP },
1455 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1456 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1457 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1459 { PCI_VDEVICE(INTEL, 0x7aaa), LPSS_CNL_SSP },
1460 { PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP },
1461 { PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP },
1462 { PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP },
1464 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1465 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1466 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1468 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1469 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1470 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1472 { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1473 { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1474 { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1476 { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1477 { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1478 { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1480 { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1481 { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1482 { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1483 { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1484 { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1485 { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1486 { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1490 static const struct of_device_id pxa2xx_spi_of_match[] = {
1491 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1494 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1498 static int pxa2xx_spi_get_port_id(struct device *dev)
1500 struct acpi_device *adev;
1504 adev = ACPI_COMPANION(dev);
1505 if (adev && adev->pnp.unique_id &&
1506 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1511 #else /* !CONFIG_ACPI */
1513 static int pxa2xx_spi_get_port_id(struct device *dev)
1518 #endif /* CONFIG_ACPI */
1523 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1525 return param == chan->device->dev;
1528 #endif /* CONFIG_PCI */
1530 static struct pxa2xx_spi_controller *
1531 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1533 struct pxa2xx_spi_controller *pdata;
1534 struct ssp_device *ssp;
1535 struct resource *res;
1536 struct device *parent = pdev->dev.parent;
1537 struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1538 const struct pci_device_id *pcidev_id = NULL;
1539 enum pxa_ssp_type type;
1543 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1545 match = device_get_match_data(&pdev->dev);
1547 type = (enum pxa_ssp_type)match;
1549 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1551 return ERR_PTR(-EINVAL);
1553 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1555 return ERR_PTR(-ENOMEM);
1559 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1560 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1561 if (IS_ERR(ssp->mmio_base))
1562 return ERR_CAST(ssp->mmio_base);
1564 ssp->phys_base = res->start;
1568 pdata->tx_param = parent;
1569 pdata->rx_param = parent;
1570 pdata->dma_filter = pxa2xx_spi_idma_filter;
1574 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1575 if (IS_ERR(ssp->clk))
1576 return ERR_CAST(ssp->clk);
1578 ssp->irq = platform_get_irq(pdev, 0);
1580 return ERR_PTR(ssp->irq);
1583 ssp->dev = &pdev->dev;
1584 ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1586 pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1587 pdata->num_chipselect = 1;
1588 pdata->enable_dma = true;
1589 pdata->dma_burst_size = 1;
1594 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1597 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1599 if (has_acpi_companion(drv_data->ssp->dev)) {
1600 switch (drv_data->ssp_type) {
1602 * For Atoms the ACPI DeviceSelection used by the Windows
1603 * driver starts from 1 instead of 0 so translate it here
1604 * to match what Linux expects.
1618 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1623 static int pxa2xx_spi_probe(struct platform_device *pdev)
1625 struct device *dev = &pdev->dev;
1626 struct pxa2xx_spi_controller *platform_info;
1627 struct spi_controller *controller;
1628 struct driver_data *drv_data;
1629 struct ssp_device *ssp;
1630 const struct lpss_config *config;
1634 platform_info = dev_get_platdata(dev);
1635 if (!platform_info) {
1636 platform_info = pxa2xx_spi_init_pdata(pdev);
1637 if (IS_ERR(platform_info)) {
1638 dev_err(&pdev->dev, "missing platform data\n");
1639 return PTR_ERR(platform_info);
1643 ssp = pxa_ssp_request(pdev->id, pdev->name);
1645 ssp = &platform_info->ssp;
1647 if (!ssp->mmio_base) {
1648 dev_err(&pdev->dev, "failed to get SSP\n");
1652 if (platform_info->is_slave)
1653 controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
1655 controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
1658 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1660 goto out_error_controller_alloc;
1662 drv_data = spi_controller_get_devdata(controller);
1663 drv_data->controller = controller;
1664 drv_data->controller_info = platform_info;
1665 drv_data->ssp = ssp;
1667 device_set_node(&controller->dev, dev_fwnode(dev));
1669 /* The spi->mode bits understood by this driver: */
1670 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1672 controller->bus_num = ssp->port_id;
1673 controller->dma_alignment = DMA_ALIGNMENT;
1674 controller->cleanup = cleanup;
1675 controller->setup = setup;
1676 controller->set_cs = pxa2xx_spi_set_cs;
1677 controller->transfer_one = pxa2xx_spi_transfer_one;
1678 controller->slave_abort = pxa2xx_spi_slave_abort;
1679 controller->handle_err = pxa2xx_spi_handle_err;
1680 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1681 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1682 controller->auto_runtime_pm = true;
1683 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1685 drv_data->ssp_type = ssp->type;
1687 if (pxa25x_ssp_comp(drv_data)) {
1688 switch (drv_data->ssp_type) {
1689 case QUARK_X1000_SSP:
1690 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1693 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1697 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1698 drv_data->dma_cr1 = 0;
1699 drv_data->clear_sr = SSSR_ROR;
1700 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1702 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1703 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1704 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1705 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1706 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1707 | SSSR_ROR | SSSR_TUR;
1710 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1713 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1714 goto out_error_controller_alloc;
1717 /* Setup DMA if requested */
1718 if (platform_info->enable_dma) {
1719 status = pxa2xx_spi_dma_setup(drv_data);
1721 dev_warn(dev, "no DMA channels available, using PIO\n");
1722 platform_info->enable_dma = false;
1724 controller->can_dma = pxa2xx_spi_can_dma;
1725 controller->max_dma_len = MAX_DMA_LEN;
1726 controller->max_transfer_size =
1727 pxa2xx_spi_max_dma_transfer_size;
1731 /* Enable SOC clock */
1732 status = clk_prepare_enable(ssp->clk);
1734 goto out_error_dma_irq_alloc;
1736 controller->max_speed_hz = clk_get_rate(ssp->clk);
1738 * Set minimum speed for all other platforms than Intel Quark which is
1739 * able do under 1 Hz transfers.
1741 if (!pxa25x_ssp_comp(drv_data))
1742 controller->min_speed_hz =
1743 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1744 else if (!is_quark_x1000_ssp(drv_data))
1745 controller->min_speed_hz =
1746 DIV_ROUND_UP(controller->max_speed_hz, 512);
1748 pxa_ssp_disable(ssp);
1750 /* Load default SSP configuration */
1751 switch (drv_data->ssp_type) {
1752 case QUARK_X1000_SSP:
1753 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1754 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1755 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1757 /* Using the Motorola SPI protocol and use 8 bit frame */
1758 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1759 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1762 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1763 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1764 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1765 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1766 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1770 if (spi_controller_is_slave(controller)) {
1778 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1779 SSCR1_TxTresh(TX_THRESH_DFLT);
1781 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1782 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1783 if (!spi_controller_is_slave(controller))
1784 tmp |= SSCR0_SCR(2);
1785 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1789 if (!pxa25x_ssp_comp(drv_data))
1790 pxa2xx_spi_write(drv_data, SSTO, 0);
1792 if (!is_quark_x1000_ssp(drv_data))
1793 pxa2xx_spi_write(drv_data, SSPSP, 0);
1795 if (is_lpss_ssp(drv_data)) {
1796 lpss_ssp_setup(drv_data);
1797 config = lpss_get_config(drv_data);
1798 if (config->reg_capabilities >= 0) {
1799 tmp = __lpss_ssp_read_priv(drv_data,
1800 config->reg_capabilities);
1801 tmp &= LPSS_CAPS_CS_EN_MASK;
1802 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1803 platform_info->num_chipselect = ffz(tmp);
1804 } else if (config->cs_num) {
1805 platform_info->num_chipselect = config->cs_num;
1808 controller->num_chipselect = platform_info->num_chipselect;
1809 controller->use_gpio_descriptors = true;
1811 if (platform_info->is_slave) {
1812 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1813 "ready", GPIOD_OUT_LOW);
1814 if (IS_ERR(drv_data->gpiod_ready)) {
1815 status = PTR_ERR(drv_data->gpiod_ready);
1816 goto out_error_clock_enabled;
1820 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1821 pm_runtime_use_autosuspend(&pdev->dev);
1822 pm_runtime_set_active(&pdev->dev);
1823 pm_runtime_enable(&pdev->dev);
1825 /* Register with the SPI framework */
1826 platform_set_drvdata(pdev, drv_data);
1827 status = spi_register_controller(controller);
1829 dev_err(&pdev->dev, "problem registering SPI controller\n");
1830 goto out_error_pm_runtime_enabled;
1835 out_error_pm_runtime_enabled:
1836 pm_runtime_disable(&pdev->dev);
1838 out_error_clock_enabled:
1839 clk_disable_unprepare(ssp->clk);
1841 out_error_dma_irq_alloc:
1842 pxa2xx_spi_dma_release(drv_data);
1843 free_irq(ssp->irq, drv_data);
1845 out_error_controller_alloc:
1850 static int pxa2xx_spi_remove(struct platform_device *pdev)
1852 struct driver_data *drv_data = platform_get_drvdata(pdev);
1853 struct ssp_device *ssp = drv_data->ssp;
1855 pm_runtime_get_sync(&pdev->dev);
1857 spi_unregister_controller(drv_data->controller);
1859 /* Disable the SSP at the peripheral and SOC level */
1860 pxa_ssp_disable(ssp);
1861 clk_disable_unprepare(ssp->clk);
1864 if (drv_data->controller_info->enable_dma)
1865 pxa2xx_spi_dma_release(drv_data);
1867 pm_runtime_put_noidle(&pdev->dev);
1868 pm_runtime_disable(&pdev->dev);
1871 free_irq(ssp->irq, drv_data);
1879 #ifdef CONFIG_PM_SLEEP
1880 static int pxa2xx_spi_suspend(struct device *dev)
1882 struct driver_data *drv_data = dev_get_drvdata(dev);
1883 struct ssp_device *ssp = drv_data->ssp;
1886 status = spi_controller_suspend(drv_data->controller);
1890 pxa_ssp_disable(ssp);
1892 if (!pm_runtime_suspended(dev))
1893 clk_disable_unprepare(ssp->clk);
1898 static int pxa2xx_spi_resume(struct device *dev)
1900 struct driver_data *drv_data = dev_get_drvdata(dev);
1901 struct ssp_device *ssp = drv_data->ssp;
1904 /* Enable the SSP clock */
1905 if (!pm_runtime_suspended(dev)) {
1906 status = clk_prepare_enable(ssp->clk);
1911 /* Start the queue running */
1912 return spi_controller_resume(drv_data->controller);
1917 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1919 struct driver_data *drv_data = dev_get_drvdata(dev);
1921 clk_disable_unprepare(drv_data->ssp->clk);
1925 static int pxa2xx_spi_runtime_resume(struct device *dev)
1927 struct driver_data *drv_data = dev_get_drvdata(dev);
1930 status = clk_prepare_enable(drv_data->ssp->clk);
1935 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1936 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1937 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1938 pxa2xx_spi_runtime_resume, NULL)
1941 static struct platform_driver driver = {
1943 .name = "pxa2xx-spi",
1944 .pm = &pxa2xx_spi_pm_ops,
1945 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1946 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1948 .probe = pxa2xx_spi_probe,
1949 .remove = pxa2xx_spi_remove,
1952 static int __init pxa2xx_spi_init(void)
1954 return platform_driver_register(&driver);
1956 subsys_initcall(pxa2xx_spi_init);
1958 static void __exit pxa2xx_spi_exit(void)
1960 platform_driver_unregister(&driver);
1962 module_exit(pxa2xx_spi_exit);
1964 MODULE_SOFTDEP("pre: dw_dmac");