2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/ioport.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/spi/spi.h>
28 #include <linux/delay.h>
29 #include <linux/gpio.h>
30 #include <linux/slab.h>
31 #include <linux/clk.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/acpi.h>
35 #include "spi-pxa2xx.h"
37 MODULE_AUTHOR("Stephen Street");
38 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
39 MODULE_LICENSE("GPL");
40 MODULE_ALIAS("platform:pxa2xx-spi");
42 #define TIMOUT_DFLT 1000
45 * for testing SSCR1 changes that require SSP restart, basically
46 * everything except the service and interrupt enables, the pxa270 developer
47 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
48 * list, but the PXA255 dev man says all bits without really meaning the
49 * service and interrupt enables
51 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
52 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
53 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
54 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
55 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
56 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
58 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
59 | QUARK_X1000_SSCR1_EFWR \
60 | QUARK_X1000_SSCR1_RFT \
61 | QUARK_X1000_SSCR1_TFT \
62 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
65 #define SPI_CS_CONTROL_SW_MODE BIT(0)
66 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
69 /* LPSS offset from drv_data->ioaddr */
71 /* Register offsets from drv_data->lpss_base or -1 */
81 /* Keep these sorted with enum pxa_ssp_type */
82 static const struct lpss_config lpss_platforms[] = {
89 .tx_threshold_lo = 160,
90 .tx_threshold_hi = 224,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
107 .tx_threshold_lo = 32,
108 .tx_threshold_hi = 56,
112 static inline const struct lpss_config
113 *lpss_get_config(const struct driver_data *drv_data)
115 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
118 static bool is_lpss_ssp(const struct driver_data *drv_data)
120 switch (drv_data->ssp_type) {
130 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
132 return drv_data->ssp_type == QUARK_X1000_SSP;
135 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
137 switch (drv_data->ssp_type) {
138 case QUARK_X1000_SSP:
139 return QUARK_X1000_SSCR1_CHANGE_MASK;
141 return SSCR1_CHANGE_MASK;
146 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
148 switch (drv_data->ssp_type) {
149 case QUARK_X1000_SSP:
150 return RX_THRESH_QUARK_X1000_DFLT;
152 return RX_THRESH_DFLT;
156 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
160 switch (drv_data->ssp_type) {
161 case QUARK_X1000_SSP:
162 mask = QUARK_X1000_SSSR_TFL_MASK;
165 mask = SSSR_TFL_MASK;
169 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
172 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
177 switch (drv_data->ssp_type) {
178 case QUARK_X1000_SSP:
179 mask = QUARK_X1000_SSCR1_RFT;
188 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
189 u32 *sccr1_reg, u32 threshold)
191 switch (drv_data->ssp_type) {
192 case QUARK_X1000_SSP:
193 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
196 *sccr1_reg |= SSCR1_RxTresh(threshold);
201 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
202 u32 clk_div, u8 bits)
204 switch (drv_data->ssp_type) {
205 case QUARK_X1000_SSP:
207 | QUARK_X1000_SSCR0_Motorola
208 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
213 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
215 | (bits > 16 ? SSCR0_EDSS : 0);
220 * Read and write LPSS SSP private registers. Caller must first check that
221 * is_lpss_ssp() returns true before these can be called.
223 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
225 WARN_ON(!drv_data->lpss_base);
226 return readl(drv_data->lpss_base + offset);
229 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
230 unsigned offset, u32 value)
232 WARN_ON(!drv_data->lpss_base);
233 writel(value, drv_data->lpss_base + offset);
237 * lpss_ssp_setup - perform LPSS SSP specific setup
238 * @drv_data: pointer to the driver private data
240 * Perform LPSS SSP specific setup. This function must be called first if
241 * one is going to use LPSS SSP private registers.
243 static void lpss_ssp_setup(struct driver_data *drv_data)
245 const struct lpss_config *config;
248 config = lpss_get_config(drv_data);
249 drv_data->lpss_base = drv_data->ioaddr + config->offset;
251 /* Enable software chip select control */
252 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
253 value &= ~(SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH);
254 value |= SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
255 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
257 /* Enable multiblock DMA transfers */
258 if (drv_data->master_info->enable_dma) {
259 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
261 if (config->reg_general >= 0) {
262 value = __lpss_ssp_read_priv(drv_data,
263 config->reg_general);
264 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
265 __lpss_ssp_write_priv(drv_data,
266 config->reg_general, value);
271 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
273 const struct lpss_config *config;
276 config = lpss_get_config(drv_data);
278 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
280 value &= ~SPI_CS_CONTROL_CS_HIGH;
282 value |= SPI_CS_CONTROL_CS_HIGH;
283 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
286 static void cs_assert(struct driver_data *drv_data)
288 struct chip_data *chip = drv_data->cur_chip;
290 if (drv_data->ssp_type == CE4100_SSP) {
291 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
295 if (chip->cs_control) {
296 chip->cs_control(PXA2XX_CS_ASSERT);
300 if (gpio_is_valid(chip->gpio_cs)) {
301 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
305 if (is_lpss_ssp(drv_data))
306 lpss_ssp_cs_control(drv_data, true);
309 static void cs_deassert(struct driver_data *drv_data)
311 struct chip_data *chip = drv_data->cur_chip;
313 if (drv_data->ssp_type == CE4100_SSP)
316 if (chip->cs_control) {
317 chip->cs_control(PXA2XX_CS_DEASSERT);
321 if (gpio_is_valid(chip->gpio_cs)) {
322 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
326 if (is_lpss_ssp(drv_data))
327 lpss_ssp_cs_control(drv_data, false);
330 int pxa2xx_spi_flush(struct driver_data *drv_data)
332 unsigned long limit = loops_per_jiffy << 1;
335 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
336 pxa2xx_spi_read(drv_data, SSDR);
337 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
338 write_SSSR_CS(drv_data, SSSR_ROR);
343 static int null_writer(struct driver_data *drv_data)
345 u8 n_bytes = drv_data->n_bytes;
347 if (pxa2xx_spi_txfifo_full(drv_data)
348 || (drv_data->tx == drv_data->tx_end))
351 pxa2xx_spi_write(drv_data, SSDR, 0);
352 drv_data->tx += n_bytes;
357 static int null_reader(struct driver_data *drv_data)
359 u8 n_bytes = drv_data->n_bytes;
361 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
362 && (drv_data->rx < drv_data->rx_end)) {
363 pxa2xx_spi_read(drv_data, SSDR);
364 drv_data->rx += n_bytes;
367 return drv_data->rx == drv_data->rx_end;
370 static int u8_writer(struct driver_data *drv_data)
372 if (pxa2xx_spi_txfifo_full(drv_data)
373 || (drv_data->tx == drv_data->tx_end))
376 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
382 static int u8_reader(struct driver_data *drv_data)
384 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
385 && (drv_data->rx < drv_data->rx_end)) {
386 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
390 return drv_data->rx == drv_data->rx_end;
393 static int u16_writer(struct driver_data *drv_data)
395 if (pxa2xx_spi_txfifo_full(drv_data)
396 || (drv_data->tx == drv_data->tx_end))
399 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
405 static int u16_reader(struct driver_data *drv_data)
407 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
408 && (drv_data->rx < drv_data->rx_end)) {
409 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
413 return drv_data->rx == drv_data->rx_end;
416 static int u32_writer(struct driver_data *drv_data)
418 if (pxa2xx_spi_txfifo_full(drv_data)
419 || (drv_data->tx == drv_data->tx_end))
422 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
428 static int u32_reader(struct driver_data *drv_data)
430 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
431 && (drv_data->rx < drv_data->rx_end)) {
432 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
436 return drv_data->rx == drv_data->rx_end;
439 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
441 struct spi_message *msg = drv_data->cur_msg;
442 struct spi_transfer *trans = drv_data->cur_transfer;
444 /* Move to next transfer */
445 if (trans->transfer_list.next != &msg->transfers) {
446 drv_data->cur_transfer =
447 list_entry(trans->transfer_list.next,
450 return RUNNING_STATE;
455 /* caller already set message->status; dma and pio irqs are blocked */
456 static void giveback(struct driver_data *drv_data)
458 struct spi_transfer* last_transfer;
459 struct spi_message *msg;
461 msg = drv_data->cur_msg;
462 drv_data->cur_msg = NULL;
463 drv_data->cur_transfer = NULL;
465 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
468 /* Delay if requested before any change in chip select */
469 if (last_transfer->delay_usecs)
470 udelay(last_transfer->delay_usecs);
472 /* Drop chip select UNLESS cs_change is true or we are returning
473 * a message with an error, or next message is for another chip
475 if (!last_transfer->cs_change)
476 cs_deassert(drv_data);
478 struct spi_message *next_msg;
480 /* Holding of cs was hinted, but we need to make sure
481 * the next message is for the same chip. Don't waste
482 * time with the following tests unless this was hinted.
484 * We cannot postpone this until pump_messages, because
485 * after calling msg->complete (below) the driver that
486 * sent the current message could be unloaded, which
487 * could invalidate the cs_control() callback...
490 /* get a pointer to the next message, if any */
491 next_msg = spi_get_next_queued_message(drv_data->master);
493 /* see if the next and current messages point
496 if (next_msg && next_msg->spi != msg->spi)
498 if (!next_msg || msg->state == ERROR_STATE)
499 cs_deassert(drv_data);
502 drv_data->cur_chip = NULL;
503 spi_finalize_current_message(drv_data->master);
506 static void reset_sccr1(struct driver_data *drv_data)
508 struct chip_data *chip = drv_data->cur_chip;
511 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
512 sccr1_reg &= ~SSCR1_RFT;
513 sccr1_reg |= chip->threshold;
514 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
517 static void int_error_stop(struct driver_data *drv_data, const char* msg)
519 /* Stop and reset SSP */
520 write_SSSR_CS(drv_data, drv_data->clear_sr);
521 reset_sccr1(drv_data);
522 if (!pxa25x_ssp_comp(drv_data))
523 pxa2xx_spi_write(drv_data, SSTO, 0);
524 pxa2xx_spi_flush(drv_data);
525 pxa2xx_spi_write(drv_data, SSCR0,
526 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
528 dev_err(&drv_data->pdev->dev, "%s\n", msg);
530 drv_data->cur_msg->state = ERROR_STATE;
531 tasklet_schedule(&drv_data->pump_transfers);
534 static void int_transfer_complete(struct driver_data *drv_data)
537 write_SSSR_CS(drv_data, drv_data->clear_sr);
538 reset_sccr1(drv_data);
539 if (!pxa25x_ssp_comp(drv_data))
540 pxa2xx_spi_write(drv_data, SSTO, 0);
542 /* Update total byte transferred return count actual bytes read */
543 drv_data->cur_msg->actual_length += drv_data->len -
544 (drv_data->rx_end - drv_data->rx);
546 /* Transfer delays and chip select release are
547 * handled in pump_transfers or giveback
550 /* Move to next transfer */
551 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
553 /* Schedule transfer tasklet */
554 tasklet_schedule(&drv_data->pump_transfers);
557 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
559 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
560 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
562 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
564 if (irq_status & SSSR_ROR) {
565 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
569 if (irq_status & SSSR_TINT) {
570 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
571 if (drv_data->read(drv_data)) {
572 int_transfer_complete(drv_data);
577 /* Drain rx fifo, Fill tx fifo and prevent overruns */
579 if (drv_data->read(drv_data)) {
580 int_transfer_complete(drv_data);
583 } while (drv_data->write(drv_data));
585 if (drv_data->read(drv_data)) {
586 int_transfer_complete(drv_data);
590 if (drv_data->tx == drv_data->tx_end) {
594 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
595 sccr1_reg &= ~SSCR1_TIE;
598 * PXA25x_SSP has no timeout, set up rx threshould for the
599 * remaining RX bytes.
601 if (pxa25x_ssp_comp(drv_data)) {
604 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
606 bytes_left = drv_data->rx_end - drv_data->rx;
607 switch (drv_data->n_bytes) {
614 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
615 if (rx_thre > bytes_left)
616 rx_thre = bytes_left;
618 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
620 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
623 /* We did something */
627 static irqreturn_t ssp_int(int irq, void *dev_id)
629 struct driver_data *drv_data = dev_id;
631 u32 mask = drv_data->mask_sr;
635 * The IRQ might be shared with other peripherals so we must first
636 * check that are we RPM suspended or not. If we are we assume that
637 * the IRQ was not for us (we shouldn't be RPM suspended when the
638 * interrupt is enabled).
640 if (pm_runtime_suspended(&drv_data->pdev->dev))
644 * If the device is not yet in RPM suspended state and we get an
645 * interrupt that is meant for another device, check if status bits
646 * are all set to one. That means that the device is already
649 status = pxa2xx_spi_read(drv_data, SSSR);
653 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
655 /* Ignore possible writes if we don't need to write */
656 if (!(sccr1_reg & SSCR1_TIE))
659 if (!(status & mask))
662 if (!drv_data->cur_msg) {
664 pxa2xx_spi_write(drv_data, SSCR0,
665 pxa2xx_spi_read(drv_data, SSCR0)
667 pxa2xx_spi_write(drv_data, SSCR1,
668 pxa2xx_spi_read(drv_data, SSCR1)
669 & ~drv_data->int_cr1);
670 if (!pxa25x_ssp_comp(drv_data))
671 pxa2xx_spi_write(drv_data, SSTO, 0);
672 write_SSSR_CS(drv_data, drv_data->clear_sr);
674 dev_err(&drv_data->pdev->dev,
675 "bad message state in interrupt handler\n");
681 return drv_data->transfer_handler(drv_data);
685 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
686 * input frequency by fractions of 2^24. It also has a divider by 5.
688 * There are formulas to get baud rate value for given input frequency and
689 * divider parameters, such as DDS_CLK_RATE and SCR:
693 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
694 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
696 * DDS_CLK_RATE either 2^n or 2^n / 5.
697 * SCR is in range 0 .. 255
699 * Divisor = 5^i * 2^j * 2 * k
700 * i = [0, 1] i = 1 iff j = 0 or j > 3
701 * j = [0, 23] j = 0 iff i = 1
703 * Special case: j = 0, i = 1: Divisor = 2 / 5
705 * Accordingly to the specification the recommended values for DDS_CLK_RATE
707 * Case 1: 2^n, n = [0, 23]
708 * Case 2: 2^24 * 2 / 5 (0x666666)
709 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
711 * In all cases the lowest possible value is better.
713 * The function calculates parameters for all cases and chooses the one closest
714 * to the asked baud rate.
716 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
718 unsigned long xtal = 200000000;
719 unsigned long fref = xtal / 2; /* mandatory division by 2,
722 unsigned long fref1 = fref / 2; /* case 1 */
723 unsigned long fref2 = fref * 2 / 5; /* case 2 */
725 unsigned long q, q1, q2;
731 /* Set initial value for DDS_CLK_RATE */
732 mul = (1 << 24) >> 1;
734 /* Calculate initial quot */
735 q1 = DIV_ROUND_UP(fref1, rate);
737 /* Scale q1 if it's too big */
739 /* Scale q1 to range [1, 512] */
740 scale = fls_long(q1 - 1);
746 /* Round the result if we have a remainder */
750 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
755 /* Get the remainder */
756 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
760 q2 = DIV_ROUND_UP(fref2, rate);
761 r2 = abs(fref2 / q2 - rate);
764 * Choose the best between two: less remainder we have the better. We
765 * can't go case 2 if q2 is greater than 256 since SCR register can
766 * hold only values 0 .. 255.
768 if (r2 >= r1 || q2 > 256) {
769 /* case 1 is better */
773 /* case 2 is better */
776 mul = (1 << 24) * 2 / 5;
779 /* Check case 3 only if the divisor is big enough */
780 if (fref / rate >= 80) {
784 /* Calculate initial quot */
785 q1 = DIV_ROUND_UP(fref, rate);
788 /* Get the remainder */
789 fssp = (u64)fref * m;
790 do_div(fssp, 1 << 24);
791 r1 = abs(fssp - rate);
793 /* Choose this one if it suits better */
795 /* case 3 is better */
805 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
807 unsigned long ssp_clk = drv_data->master->max_speed_hz;
808 const struct ssp_device *ssp = drv_data->ssp;
810 rate = min_t(int, ssp_clk, rate);
812 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
813 return (ssp_clk / (2 * rate) - 1) & 0xff;
815 return (ssp_clk / rate - 1) & 0xfff;
818 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
821 struct chip_data *chip = drv_data->cur_chip;
822 unsigned int clk_div;
824 switch (drv_data->ssp_type) {
825 case QUARK_X1000_SSP:
826 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
829 clk_div = ssp_get_clk_div(drv_data, rate);
835 static void pump_transfers(unsigned long data)
837 struct driver_data *drv_data = (struct driver_data *)data;
838 struct spi_message *message = NULL;
839 struct spi_transfer *transfer = NULL;
840 struct spi_transfer *previous = NULL;
841 struct chip_data *chip = NULL;
847 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
848 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
849 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
851 /* Get current state information */
852 message = drv_data->cur_msg;
853 transfer = drv_data->cur_transfer;
854 chip = drv_data->cur_chip;
856 /* Handle for abort */
857 if (message->state == ERROR_STATE) {
858 message->status = -EIO;
863 /* Handle end of message */
864 if (message->state == DONE_STATE) {
870 /* Delay if requested at end of transfer before CS change */
871 if (message->state == RUNNING_STATE) {
872 previous = list_entry(transfer->transfer_list.prev,
875 if (previous->delay_usecs)
876 udelay(previous->delay_usecs);
878 /* Drop chip select only if cs_change is requested */
879 if (previous->cs_change)
880 cs_deassert(drv_data);
883 /* Check if we can DMA this transfer */
884 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
886 /* reject already-mapped transfers; PIO won't always work */
887 if (message->is_dma_mapped
888 || transfer->rx_dma || transfer->tx_dma) {
889 dev_err(&drv_data->pdev->dev,
890 "pump_transfers: mapped transfer length of "
891 "%u is greater than %d\n",
892 transfer->len, MAX_DMA_LEN);
893 message->status = -EINVAL;
898 /* warn ... we force this to PIO mode */
899 dev_warn_ratelimited(&message->spi->dev,
900 "pump_transfers: DMA disabled for transfer length %ld "
902 (long)drv_data->len, MAX_DMA_LEN);
905 /* Setup the transfer state based on the type of transfer */
906 if (pxa2xx_spi_flush(drv_data) == 0) {
907 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
908 message->status = -EIO;
912 drv_data->n_bytes = chip->n_bytes;
913 drv_data->tx = (void *)transfer->tx_buf;
914 drv_data->tx_end = drv_data->tx + transfer->len;
915 drv_data->rx = transfer->rx_buf;
916 drv_data->rx_end = drv_data->rx + transfer->len;
917 drv_data->rx_dma = transfer->rx_dma;
918 drv_data->tx_dma = transfer->tx_dma;
919 drv_data->len = transfer->len;
920 drv_data->write = drv_data->tx ? chip->write : null_writer;
921 drv_data->read = drv_data->rx ? chip->read : null_reader;
923 /* Change speed and bit per word on a per transfer */
924 bits = transfer->bits_per_word;
925 speed = transfer->speed_hz;
927 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
930 drv_data->n_bytes = 1;
931 drv_data->read = drv_data->read != null_reader ?
932 u8_reader : null_reader;
933 drv_data->write = drv_data->write != null_writer ?
934 u8_writer : null_writer;
935 } else if (bits <= 16) {
936 drv_data->n_bytes = 2;
937 drv_data->read = drv_data->read != null_reader ?
938 u16_reader : null_reader;
939 drv_data->write = drv_data->write != null_writer ?
940 u16_writer : null_writer;
941 } else if (bits <= 32) {
942 drv_data->n_bytes = 4;
943 drv_data->read = drv_data->read != null_reader ?
944 u32_reader : null_reader;
945 drv_data->write = drv_data->write != null_writer ?
946 u32_writer : null_writer;
949 * if bits/word is changed in dma mode, then must check the
950 * thresholds and burst also
952 if (chip->enable_dma) {
953 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
957 dev_warn_ratelimited(&message->spi->dev,
958 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
961 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
962 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
963 if (!pxa25x_ssp_comp(drv_data))
964 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
965 drv_data->master->max_speed_hz
966 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
967 chip->enable_dma ? "DMA" : "PIO");
969 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
970 drv_data->master->max_speed_hz / 2
971 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
972 chip->enable_dma ? "DMA" : "PIO");
974 message->state = RUNNING_STATE;
976 drv_data->dma_mapped = 0;
977 if (pxa2xx_spi_dma_is_possible(drv_data->len))
978 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
979 if (drv_data->dma_mapped) {
981 /* Ensure we have the correct interrupt handler */
982 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
984 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
986 /* Clear status and start DMA engine */
987 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
988 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
990 pxa2xx_spi_dma_start(drv_data);
992 /* Ensure we have the correct interrupt handler */
993 drv_data->transfer_handler = interrupt_transfer;
996 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
997 write_SSSR_CS(drv_data, drv_data->clear_sr);
1000 if (is_lpss_ssp(drv_data)) {
1001 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1002 != chip->lpss_rx_threshold)
1003 pxa2xx_spi_write(drv_data, SSIRF,
1004 chip->lpss_rx_threshold);
1005 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1006 != chip->lpss_tx_threshold)
1007 pxa2xx_spi_write(drv_data, SSITF,
1008 chip->lpss_tx_threshold);
1011 if (is_quark_x1000_ssp(drv_data) &&
1012 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1013 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1015 /* see if we need to reload the config registers */
1016 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1017 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1018 != (cr1 & change_mask)) {
1019 /* stop the SSP, and update the other bits */
1020 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1021 if (!pxa25x_ssp_comp(drv_data))
1022 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1023 /* first set CR1 without interrupt and service enables */
1024 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1025 /* restart the SSP */
1026 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1029 if (!pxa25x_ssp_comp(drv_data))
1030 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1033 cs_assert(drv_data);
1035 /* after chip select, release the data by enabling service
1036 * requests and interrupts, without changing any mode bits */
1037 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1040 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1041 struct spi_message *msg)
1043 struct driver_data *drv_data = spi_master_get_devdata(master);
1045 drv_data->cur_msg = msg;
1046 /* Initial message state*/
1047 drv_data->cur_msg->state = START_STATE;
1048 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1049 struct spi_transfer,
1052 /* prepare to setup the SSP, in pump_transfers, using the per
1053 * chip configuration */
1054 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1056 /* Mark as busy and launch transfers */
1057 tasklet_schedule(&drv_data->pump_transfers);
1061 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1063 struct driver_data *drv_data = spi_master_get_devdata(master);
1065 /* Disable the SSP now */
1066 pxa2xx_spi_write(drv_data, SSCR0,
1067 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1072 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1073 struct pxa2xx_spi_chip *chip_info)
1077 if (chip == NULL || chip_info == NULL)
1080 /* NOTE: setup() can be called multiple times, possibly with
1081 * different chip_info, release previously requested GPIO
1083 if (gpio_is_valid(chip->gpio_cs))
1084 gpio_free(chip->gpio_cs);
1086 /* If (*cs_control) is provided, ignore GPIO chip select */
1087 if (chip_info->cs_control) {
1088 chip->cs_control = chip_info->cs_control;
1092 if (gpio_is_valid(chip_info->gpio_cs)) {
1093 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1095 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1096 chip_info->gpio_cs);
1100 chip->gpio_cs = chip_info->gpio_cs;
1101 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1103 err = gpio_direction_output(chip->gpio_cs,
1104 !chip->gpio_cs_inverted);
1110 static int setup(struct spi_device *spi)
1112 struct pxa2xx_spi_chip *chip_info = NULL;
1113 struct chip_data *chip;
1114 const struct lpss_config *config;
1115 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1116 uint tx_thres, tx_hi_thres, rx_thres;
1118 switch (drv_data->ssp_type) {
1119 case QUARK_X1000_SSP:
1120 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1122 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1127 config = lpss_get_config(drv_data);
1128 tx_thres = config->tx_threshold_lo;
1129 tx_hi_thres = config->tx_threshold_hi;
1130 rx_thres = config->rx_threshold;
1133 tx_thres = TX_THRESH_DFLT;
1135 rx_thres = RX_THRESH_DFLT;
1139 /* Only alloc on first setup */
1140 chip = spi_get_ctldata(spi);
1142 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1146 if (drv_data->ssp_type == CE4100_SSP) {
1147 if (spi->chip_select > 4) {
1149 "failed setup: cs number must not be > 4.\n");
1154 chip->frm = spi->chip_select;
1157 chip->enable_dma = 0;
1158 chip->timeout = TIMOUT_DFLT;
1161 /* protocol drivers may change the chip settings, so...
1162 * if chip_info exists, use it */
1163 chip_info = spi->controller_data;
1165 /* chip_info isn't always needed */
1168 if (chip_info->timeout)
1169 chip->timeout = chip_info->timeout;
1170 if (chip_info->tx_threshold)
1171 tx_thres = chip_info->tx_threshold;
1172 if (chip_info->tx_hi_threshold)
1173 tx_hi_thres = chip_info->tx_hi_threshold;
1174 if (chip_info->rx_threshold)
1175 rx_thres = chip_info->rx_threshold;
1176 chip->enable_dma = drv_data->master_info->enable_dma;
1177 chip->dma_threshold = 0;
1178 if (chip_info->enable_loopback)
1179 chip->cr1 = SSCR1_LBM;
1180 } else if (ACPI_HANDLE(&spi->dev)) {
1182 * Slave devices enumerated from ACPI namespace don't
1183 * usually have chip_info but we still might want to use
1186 chip->enable_dma = drv_data->master_info->enable_dma;
1189 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1190 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1191 | SSITF_TxHiThresh(tx_hi_thres);
1193 /* set dma burst and threshold outside of chip_info path so that if
1194 * chip_info goes away after setting chip->enable_dma, the
1195 * burst and threshold can still respond to changes in bits_per_word */
1196 if (chip->enable_dma) {
1197 /* set up legal burst and threshold for dma */
1198 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1200 &chip->dma_burst_size,
1201 &chip->dma_threshold)) {
1203 "in setup: DMA burst size reduced to match bits_per_word\n");
1207 switch (drv_data->ssp_type) {
1208 case QUARK_X1000_SSP:
1209 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1210 & QUARK_X1000_SSCR1_RFT)
1211 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1212 & QUARK_X1000_SSCR1_TFT);
1215 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1216 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1220 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1221 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1222 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1224 if (spi->mode & SPI_LOOP)
1225 chip->cr1 |= SSCR1_LBM;
1227 if (spi->bits_per_word <= 8) {
1229 chip->read = u8_reader;
1230 chip->write = u8_writer;
1231 } else if (spi->bits_per_word <= 16) {
1233 chip->read = u16_reader;
1234 chip->write = u16_writer;
1235 } else if (spi->bits_per_word <= 32) {
1237 chip->read = u32_reader;
1238 chip->write = u32_writer;
1241 spi_set_ctldata(spi, chip);
1243 if (drv_data->ssp_type == CE4100_SSP)
1246 return setup_cs(spi, chip, chip_info);
1249 static void cleanup(struct spi_device *spi)
1251 struct chip_data *chip = spi_get_ctldata(spi);
1252 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1257 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1258 gpio_free(chip->gpio_cs);
1265 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1266 { "INT33C0", LPSS_LPT_SSP },
1267 { "INT33C1", LPSS_LPT_SSP },
1268 { "INT3430", LPSS_LPT_SSP },
1269 { "INT3431", LPSS_LPT_SSP },
1270 { "80860F0E", LPSS_BYT_SSP },
1271 { "8086228E", LPSS_BYT_SSP },
1274 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1277 * PCI IDs of compound devices that integrate both host controller and private
1278 * integrated DMA engine. Please note these are not used in module
1279 * autoloading and probing in this module but matching the LPSS SSP type.
1281 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1283 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1284 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1286 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1287 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1291 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1293 struct device *dev = param;
1295 if (dev != chan->device->dev->parent)
1301 static struct pxa2xx_spi_master *
1302 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1304 struct pxa2xx_spi_master *pdata;
1305 struct acpi_device *adev;
1306 struct ssp_device *ssp;
1307 struct resource *res;
1308 const struct acpi_device_id *adev_id = NULL;
1309 const struct pci_device_id *pcidev_id = NULL;
1313 adev = ACPI_COMPANION(&pdev->dev);
1317 if (dev_is_pci(pdev->dev.parent))
1318 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1319 to_pci_dev(pdev->dev.parent));
1321 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1325 type = (int)adev_id->driver_data;
1327 type = (int)pcidev_id->driver_data;
1331 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1341 ssp->phys_base = res->start;
1342 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1343 if (IS_ERR(ssp->mmio_base))
1347 pdata->tx_param = pdev->dev.parent;
1348 pdata->rx_param = pdev->dev.parent;
1349 pdata->dma_filter = pxa2xx_spi_idma_filter;
1352 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1353 ssp->irq = platform_get_irq(pdev, 0);
1358 if (adev->pnp.unique_id && !kstrtouint(adev->pnp.unique_id, 0, &devid))
1359 ssp->port_id = devid;
1361 pdata->num_chipselect = 1;
1362 pdata->enable_dma = true;
1368 static inline struct pxa2xx_spi_master *
1369 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1375 static int pxa2xx_spi_probe(struct platform_device *pdev)
1377 struct device *dev = &pdev->dev;
1378 struct pxa2xx_spi_master *platform_info;
1379 struct spi_master *master;
1380 struct driver_data *drv_data;
1381 struct ssp_device *ssp;
1385 platform_info = dev_get_platdata(dev);
1386 if (!platform_info) {
1387 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1388 if (!platform_info) {
1389 dev_err(&pdev->dev, "missing platform data\n");
1394 ssp = pxa_ssp_request(pdev->id, pdev->name);
1396 ssp = &platform_info->ssp;
1398 if (!ssp->mmio_base) {
1399 dev_err(&pdev->dev, "failed to get ssp\n");
1403 master = spi_alloc_master(dev, sizeof(struct driver_data));
1405 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1409 drv_data = spi_master_get_devdata(master);
1410 drv_data->master = master;
1411 drv_data->master_info = platform_info;
1412 drv_data->pdev = pdev;
1413 drv_data->ssp = ssp;
1415 master->dev.parent = &pdev->dev;
1416 master->dev.of_node = pdev->dev.of_node;
1417 /* the spi->mode bits understood by this driver: */
1418 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1420 master->bus_num = ssp->port_id;
1421 master->num_chipselect = platform_info->num_chipselect;
1422 master->dma_alignment = DMA_ALIGNMENT;
1423 master->cleanup = cleanup;
1424 master->setup = setup;
1425 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1426 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1427 master->auto_runtime_pm = true;
1429 drv_data->ssp_type = ssp->type;
1431 drv_data->ioaddr = ssp->mmio_base;
1432 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1433 if (pxa25x_ssp_comp(drv_data)) {
1434 switch (drv_data->ssp_type) {
1435 case QUARK_X1000_SSP:
1436 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1439 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1443 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1444 drv_data->dma_cr1 = 0;
1445 drv_data->clear_sr = SSSR_ROR;
1446 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1448 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1449 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1450 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1451 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1452 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1455 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1458 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1459 goto out_error_master_alloc;
1462 /* Setup DMA if requested */
1463 if (platform_info->enable_dma) {
1464 status = pxa2xx_spi_dma_setup(drv_data);
1466 dev_dbg(dev, "no DMA channels available, using PIO\n");
1467 platform_info->enable_dma = false;
1471 /* Enable SOC clock */
1472 clk_prepare_enable(ssp->clk);
1474 master->max_speed_hz = clk_get_rate(ssp->clk);
1476 /* Load default SSP configuration */
1477 pxa2xx_spi_write(drv_data, SSCR0, 0);
1478 switch (drv_data->ssp_type) {
1479 case QUARK_X1000_SSP:
1480 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1481 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1482 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1484 /* using the Motorola SPI protocol and use 8 bit frame */
1485 pxa2xx_spi_write(drv_data, SSCR0,
1486 QUARK_X1000_SSCR0_Motorola
1487 | QUARK_X1000_SSCR0_DataSize(8));
1490 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1491 SSCR1_TxTresh(TX_THRESH_DFLT);
1492 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1493 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1494 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1498 if (!pxa25x_ssp_comp(drv_data))
1499 pxa2xx_spi_write(drv_data, SSTO, 0);
1501 if (!is_quark_x1000_ssp(drv_data))
1502 pxa2xx_spi_write(drv_data, SSPSP, 0);
1504 if (is_lpss_ssp(drv_data))
1505 lpss_ssp_setup(drv_data);
1507 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1508 (unsigned long)drv_data);
1510 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1511 pm_runtime_use_autosuspend(&pdev->dev);
1512 pm_runtime_set_active(&pdev->dev);
1513 pm_runtime_enable(&pdev->dev);
1515 /* Register with the SPI framework */
1516 platform_set_drvdata(pdev, drv_data);
1517 status = devm_spi_register_master(&pdev->dev, master);
1519 dev_err(&pdev->dev, "problem registering spi master\n");
1520 goto out_error_clock_enabled;
1525 out_error_clock_enabled:
1526 clk_disable_unprepare(ssp->clk);
1527 pxa2xx_spi_dma_release(drv_data);
1528 free_irq(ssp->irq, drv_data);
1530 out_error_master_alloc:
1531 spi_master_put(master);
1536 static int pxa2xx_spi_remove(struct platform_device *pdev)
1538 struct driver_data *drv_data = platform_get_drvdata(pdev);
1539 struct ssp_device *ssp;
1543 ssp = drv_data->ssp;
1545 pm_runtime_get_sync(&pdev->dev);
1547 /* Disable the SSP at the peripheral and SOC level */
1548 pxa2xx_spi_write(drv_data, SSCR0, 0);
1549 clk_disable_unprepare(ssp->clk);
1552 if (drv_data->master_info->enable_dma)
1553 pxa2xx_spi_dma_release(drv_data);
1555 pm_runtime_put_noidle(&pdev->dev);
1556 pm_runtime_disable(&pdev->dev);
1559 free_irq(ssp->irq, drv_data);
1567 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1571 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1572 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1575 #ifdef CONFIG_PM_SLEEP
1576 static int pxa2xx_spi_suspend(struct device *dev)
1578 struct driver_data *drv_data = dev_get_drvdata(dev);
1579 struct ssp_device *ssp = drv_data->ssp;
1582 status = spi_master_suspend(drv_data->master);
1585 pxa2xx_spi_write(drv_data, SSCR0, 0);
1587 if (!pm_runtime_suspended(dev))
1588 clk_disable_unprepare(ssp->clk);
1593 static int pxa2xx_spi_resume(struct device *dev)
1595 struct driver_data *drv_data = dev_get_drvdata(dev);
1596 struct ssp_device *ssp = drv_data->ssp;
1599 /* Enable the SSP clock */
1600 if (!pm_runtime_suspended(dev))
1601 clk_prepare_enable(ssp->clk);
1603 /* Restore LPSS private register bits */
1604 if (is_lpss_ssp(drv_data))
1605 lpss_ssp_setup(drv_data);
1607 /* Start the queue running */
1608 status = spi_master_resume(drv_data->master);
1610 dev_err(dev, "problem starting queue (%d)\n", status);
1619 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1621 struct driver_data *drv_data = dev_get_drvdata(dev);
1623 clk_disable_unprepare(drv_data->ssp->clk);
1627 static int pxa2xx_spi_runtime_resume(struct device *dev)
1629 struct driver_data *drv_data = dev_get_drvdata(dev);
1631 clk_prepare_enable(drv_data->ssp->clk);
1636 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1637 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1638 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1639 pxa2xx_spi_runtime_resume, NULL)
1642 static struct platform_driver driver = {
1644 .name = "pxa2xx-spi",
1645 .pm = &pxa2xx_spi_pm_ops,
1646 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1648 .probe = pxa2xx_spi_probe,
1649 .remove = pxa2xx_spi_remove,
1650 .shutdown = pxa2xx_spi_shutdown,
1653 static int __init pxa2xx_spi_init(void)
1655 return platform_driver_register(&driver);
1657 subsys_initcall(pxa2xx_spi_init);
1659 static void __exit pxa2xx_spi_exit(void)
1661 platform_driver_unregister(&driver);
1663 module_exit(pxa2xx_spi_exit);