drivers/spi/spi-pci1xxxx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // PCI1xxxx SPI driver
   3 // Copyright (C) 2022 Microchip Technology Inc.
   4 // Authors: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
   5 //          Kumaravel Thiagarajan <Kumaravel.Thiagarajan@microchip.com>
   6
   7
   8 #include <linux/dma-mapping.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/irq.h>
  11 #include <linux/module.h>
  12 #include <linux/msi.h>
  13 #include <linux/pci_regs.h>
  14 #include <linux/pci.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/delay.h>
  17
  18 #define DRV_NAME "spi-pci1xxxx"
  19
  20 #define SYS_FREQ_DEFAULT                (62500000)
  21
  22 #define PCI1XXXX_SPI_MAX_CLOCK_HZ       (30000000)
  23 #define PCI1XXXX_SPI_CLK_20MHZ          (20000000)
  24 #define PCI1XXXX_SPI_CLK_15MHZ          (15000000)
  25 #define PCI1XXXX_SPI_CLK_12MHZ          (12000000)
  26 #define PCI1XXXX_SPI_CLK_10MHZ          (10000000)
  27 #define PCI1XXXX_SPI_MIN_CLOCK_HZ       (2000000)
  28
  29 #define PCI1XXXX_SPI_BUFFER_SIZE        (320)
  30
  31 #define SPI_MST_CTL_DEVSEL_MASK         (GENMASK(27, 25))
  32 #define SPI_MST_CTL_CMD_LEN_MASK        (GENMASK(16, 8))
  33 #define SPI_MST_CTL_SPEED_MASK          (GENMASK(7, 5))
  34 #define SPI_MSI_VECTOR_SEL_MASK         (GENMASK(4, 4))
  35
  36 #define SPI_MST_CTL_FORCE_CE            (BIT(4))
  37 #define SPI_MST_CTL_MODE_SEL            (BIT(2))
  38 #define SPI_MST_CTL_GO                  (BIT(0))
  39
  40 #define SPI_SYSTEM_ADDR_BASE            (0x2000)
  41 #define SPI_MST1_ADDR_BASE              (0x800)
  42
  43 #define DEV_REV_REG                     (SPI_SYSTEM_ADDR_BASE + 0x00)
  44 #define SPI_SYSLOCK_REG                 (SPI_SYSTEM_ADDR_BASE + 0xA0)
  45 #define SPI_CONFIG_PERI_ENABLE_REG      (SPI_SYSTEM_ADDR_BASE + 0x108)
  46
  47 #define SPI_PERI_ENBLE_PF_MASK          (GENMASK(17, 16))
  48 #define DEV_REV_MASK                    (GENMASK(7, 0))
  49
  50 #define SPI_SYSLOCK                     BIT(4)
  51
  52 /* DMA Related Registers */
  53 #define SPI_DMA_ADDR_BASE               (0x1000)
  54 #define SPI_DMA_GLOBAL_WR_ENGINE_EN     (SPI_DMA_ADDR_BASE + 0x0C)
  55 #define SPI_DMA_GLOBAL_RD_ENGINE_EN     (SPI_DMA_ADDR_BASE + 0x2C)
  56 #define SPI_DMA_INTR_IMWR_WDONE_LOW     (SPI_DMA_ADDR_BASE + 0x60)
  57 #define SPI_DMA_INTR_IMWR_WDONE_HIGH    (SPI_DMA_ADDR_BASE + 0x64)
  58 #define SPI_DMA_INTR_IMWR_WABORT_LOW    (SPI_DMA_ADDR_BASE + 0x68)
  59 #define SPI_DMA_INTR_IMWR_WABORT_HIGH   (SPI_DMA_ADDR_BASE + 0x6C)
  60 #define SPI_DMA_INTR_WR_IMWR_DATA       (SPI_DMA_ADDR_BASE + 0x70)
  61 #define SPI_DMA_INTR_IMWR_RDONE_LOW     (SPI_DMA_ADDR_BASE + 0xCC)
  62 #define SPI_DMA_INTR_IMWR_RDONE_HIGH    (SPI_DMA_ADDR_BASE + 0xD0)
  63 #define SPI_DMA_INTR_IMWR_RABORT_LOW    (SPI_DMA_ADDR_BASE + 0xD4)
  64 #define SPI_DMA_INTR_IMWR_RABORT_HIGH   (SPI_DMA_ADDR_BASE + 0xD8)
  65 #define SPI_DMA_INTR_RD_IMWR_DATA       (SPI_DMA_ADDR_BASE + 0xDC)
  66
  67 /* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
  68
  69 #define SPI_MST_CMD_BUF_OFFSET(x)               (((x) * SPI_MST1_ADDR_BASE) + 0x00)
  70 #define SPI_MST_RSP_BUF_OFFSET(x)               (((x) * SPI_MST1_ADDR_BASE) + 0x200)
  71 #define SPI_MST_CTL_REG_OFFSET(x)               (((x) * SPI_MST1_ADDR_BASE) + 0x400)
  72 #define SPI_MST_EVENT_REG_OFFSET(x)             (((x) * SPI_MST1_ADDR_BASE) + 0x420)
  73 #define SPI_MST_EVENT_MASK_REG_OFFSET(x)        (((x) * SPI_MST1_ADDR_BASE) + 0x424)
  74 #define SPI_MST_PAD_CTL_REG_OFFSET(x)           (((x) * SPI_MST1_ADDR_BASE) + 0x460)
  75 #define SPIALERT_MST_DB_REG_OFFSET(x)           (((x) * SPI_MST1_ADDR_BASE) + 0x464)
  76 #define SPIALERT_MST_VAL_REG_OFFSET(x)          (((x) * SPI_MST1_ADDR_BASE) + 0x468)
  77 #define SPI_PCI_CTRL_REG_OFFSET(x)              (((x) * SPI_MST1_ADDR_BASE) + 0x480)
  78
  79 #define PCI1XXXX_IRQ_FLAGS                      (IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE)
  80 #define SPI_MAX_DATA_LEN                        320
  81
  82 #define PCI1XXXX_SPI_TIMEOUT                    (msecs_to_jiffies(100))
  83 #define SYSLOCK_RETRY_CNT                       (1000)
  84 #define SPI_DMA_ENGINE_EN                       (0x1)
  85
  86 #define SPI_INTR                BIT(8)
  87 #define SPI_FORCE_CE            BIT(4)
  88
  89 #define SPI_CHIP_SEL_COUNT 7
  90 #define VENDOR_ID_MCHP 0x1055
  91
  92 #define SPI_SUSPEND_CONFIG 0x101
  93 #define SPI_RESUME_CONFIG 0x203
  94
  95 struct pci1xxxx_spi_internal {
  96         u8 hw_inst;
  97         bool spi_xfer_in_progress;
  98         int irq;
  99         struct completion spi_xfer_done;
 100         struct spi_controller *spi_host;
 101         struct pci1xxxx_spi *parent;
 102         struct {
 103                 unsigned int dev_sel : 3;
 104                 unsigned int msi_vector_sel : 1;
 105         } prev_val;
 106 };
 107
 108 struct pci1xxxx_spi {
 109         struct pci_dev *dev;
 110         u8 total_hw_instances;
 111         u8 dev_rev;
 112         void __iomem *reg_base;
 113         void __iomem *dma_offset_bar;
 114         bool can_dma;
 115         struct pci1xxxx_spi_internal *spi_int[] __counted_by(total_hw_instances);
 116 };
 117
 118 static const struct pci_device_id pci1xxxx_spi_pci_id_table[] = {
 119         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
 120         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
 121         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
 122         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
 123         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
 124         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
 125         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
 126         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
 127         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
 128         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
 129         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
 130         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
 131         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
 132         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
 133         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
 134         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
 135         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
 136         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
 137         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
 138         { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
 139         { 0, }
 140 };
 141
 142 MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table);
 143
 144 static int pci1xxxx_set_sys_lock(struct pci1xxxx_spi *par)
 145 {
 146         writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG);
 147         return readl(par->reg_base + SPI_SYSLOCK_REG);
 148 }
 149
 150 static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_spi *par)
 151 {
 152         u32 regval;
 153
 154         return readx_poll_timeout(pci1xxxx_set_sys_lock, par, regval,
 155                            (regval & SPI_SYSLOCK), 100,
 156                            SYSLOCK_RETRY_CNT * 100);
 157 }
 158
 159 static void pci1xxxx_release_sys_lock(struct pci1xxxx_spi *par)
 160 {
 161         writel(0x0, par->reg_base + SPI_SYSLOCK_REG);
 162 }
 163
 164 static int pci1xxxx_check_spi_can_dma(struct pci1xxxx_spi *spi_bus, int irq)
 165 {
 166         struct pci_dev *pdev = spi_bus->dev;
 167         u32 pf_num;
 168         u32 regval;
 169         int ret;
 170
 171         /*
 172          * DEV REV Registers is a system register, HW Syslock bit
 173          * should be acquired before accessing the register
 174          */
 175         ret = pci1xxxx_acquire_sys_lock(spi_bus);
 176         if (ret) {
 177                 dev_err(&pdev->dev, "Error failed to acquire syslock\n");
 178                 return ret;
 179         }
 180
 181         regval = readl(spi_bus->reg_base + DEV_REV_REG);
 182         spi_bus->dev_rev = regval & DEV_REV_MASK;
 183         if (spi_bus->dev_rev >= 0xC0) {
 184                 regval = readl(spi_bus->reg_base +
 185                                SPI_CONFIG_PERI_ENABLE_REG);
 186                 pf_num = regval & SPI_PERI_ENBLE_PF_MASK;
 187         }
 188
 189         pci1xxxx_release_sys_lock(spi_bus);
 190
 191         /*
 192          * DMA is supported only from C0 and SPI can use DMA only if
 193          * it is mapped to PF0
 194          */
 195         if (spi_bus->dev_rev < 0xC0 || pf_num)
 196                 return -EOPNOTSUPP;
 197
 198         /*
 199          * DMA Supported only with MSI Interrupts
 200          * One of the SPI instance's MSI vector address and data
 201          * is used for DMA Interrupt
 202          */
 203         if (!irq_get_msi_desc(irq)) {
 204                 dev_warn(&pdev->dev, "Error MSI Interrupt not supported, will operate in PIO mode\n");
 205                 return -EOPNOTSUPP;
 206         }
 207
 208         spi_bus->dma_offset_bar = pcim_iomap(pdev, 2, pci_resource_len(pdev, 2));
 209         if (!spi_bus->dma_offset_bar) {
 210                 dev_warn(&pdev->dev, "Error failed to map dma bar, will operate in PIO mode\n");
 211                 return -EOPNOTSUPP;
 212         }
 213
 214         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
 215                 dev_warn(&pdev->dev, "Error failed to set DMA mask, will operate in PIO mode\n");
 216                 pcim_iounmap(pdev, spi_bus->dma_offset_bar);
 217                 spi_bus->dma_offset_bar = NULL;
 218                 return -EOPNOTSUPP;
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int irq)
 225 {
 226         struct msi_msg msi;
 227         int ret;
 228
 229         ret = pci1xxxx_check_spi_can_dma(spi_bus, irq);
 230         if (ret)
 231                 return ret;
 232
 233         get_cached_msi_msg(irq, &msi);
 234         writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
 235         writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
 236         writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_HIGH);
 237         writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_HIGH);
 238         writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_HIGH);
 239         writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_HIGH);
 240         writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_LOW);
 241         writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_LOW);
 242         writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_LOW);
 243         writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_LOW);
 244         writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
 245         writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
 246         spi_bus->can_dma = true;
 247         return 0;
 248 }
 249
 250 static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable)
 251 {
 252         struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi->controller);
 253         struct pci1xxxx_spi *par = p->parent;
 254         u32 regval;
 255
 256         /* Set the DEV_SEL bits of the SPI_MST_CTL_REG */
 257         regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
 258         if (!enable) {
 259                 regval |= SPI_FORCE_CE;
 260                 regval &= ~SPI_MST_CTL_DEVSEL_MASK;
 261                 regval |= (spi_get_chipselect(spi, 0) << 25);
 262         } else {
 263                 regval &= ~SPI_FORCE_CE;
 264         }
 265         writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
 266 }
 267
 268 static u8 pci1xxxx_get_clock_div(u32 hz)
 269 {
 270         u8 val = 0;
 271
 272         if (hz >= PCI1XXXX_SPI_MAX_CLOCK_HZ)
 273                 val = 2;
 274         else if ((hz < PCI1XXXX_SPI_MAX_CLOCK_HZ) && (hz >= PCI1XXXX_SPI_CLK_20MHZ))
 275                 val = 3;
 276         else if ((hz < PCI1XXXX_SPI_CLK_20MHZ) && (hz >= PCI1XXXX_SPI_CLK_15MHZ))
 277                 val = 4;
 278         else if ((hz < PCI1XXXX_SPI_CLK_15MHZ) && (hz >= PCI1XXXX_SPI_CLK_12MHZ))
 279                 val = 5;
 280         else if ((hz < PCI1XXXX_SPI_CLK_12MHZ) && (hz >= PCI1XXXX_SPI_CLK_10MHZ))
 281                 val = 6;
 282         else if ((hz < PCI1XXXX_SPI_CLK_10MHZ) && (hz >= PCI1XXXX_SPI_MIN_CLOCK_HZ))
 283                 val = 7;
 284         else
 285                 val = 2;
 286
 287         return val;
 288 }
 289
 290 static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
 291                                      struct spi_device *spi, struct spi_transfer *xfer)
 292 {
 293         struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
 294         int mode, len, loop_iter, transfer_len;
 295         struct pci1xxxx_spi *par = p->parent;
 296         unsigned long bytes_transfered;
 297         unsigned long bytes_recvd;
 298         unsigned long loop_count;
 299         u8 *rx_buf, result;
 300         const u8 *tx_buf;
 301         u32 regval;
 302         u8 clkdiv;
 303
 304         p->spi_xfer_in_progress = true;
 305         mode = spi->mode;
 306         clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
 307         tx_buf = xfer->tx_buf;
 308         rx_buf = xfer->rx_buf;
 309         transfer_len = xfer->len;
 310         regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
 311         writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
 312
 313         if (tx_buf) {
 314                 bytes_transfered = 0;
 315                 bytes_recvd = 0;
 316                 loop_count = transfer_len / SPI_MAX_DATA_LEN;
 317                 if (transfer_len % SPI_MAX_DATA_LEN != 0)
 318                         loop_count += 1;
 319
 320                 for (loop_iter = 0; loop_iter < loop_count; loop_iter++) {
 321                         len = SPI_MAX_DATA_LEN;
 322                         if ((transfer_len % SPI_MAX_DATA_LEN != 0) &&
 323                             (loop_iter == loop_count - 1))
 324                                 len = transfer_len % SPI_MAX_DATA_LEN;
 325
 326                         reinit_completion(&p->spi_xfer_done);
 327                         memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst),
 328                                     &tx_buf[bytes_transfered], len);
 329                         bytes_transfered += len;
 330                         regval = readl(par->reg_base +
 331                                        SPI_MST_CTL_REG_OFFSET(p->hw_inst));
 332                         regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |
 333                                     SPI_MST_CTL_SPEED_MASK);
 334
 335                         if (mode == SPI_MODE_3)
 336                                 regval |= SPI_MST_CTL_MODE_SEL;
 337                         else
 338                                 regval &= ~SPI_MST_CTL_MODE_SEL;
 339
 340                         regval |= (clkdiv << 5);
 341                         regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
 342                         regval |= (len << 8);
 343                         writel(regval, par->reg_base +
 344                                SPI_MST_CTL_REG_OFFSET(p->hw_inst));
 345                         regval = readl(par->reg_base +
 346                                        SPI_MST_CTL_REG_OFFSET(p->hw_inst));
 347                         regval |= SPI_MST_CTL_GO;
 348                         writel(regval, par->reg_base +
 349                                SPI_MST_CTL_REG_OFFSET(p->hw_inst));
 350
 351                         /* Wait for DMA_TERM interrupt */
 352                         result = wait_for_completion_timeout(&p->spi_xfer_done,
 353                                                              PCI1XXXX_SPI_TIMEOUT);
 354                         if (!result)
 355                                 return -ETIMEDOUT;
 356
 357                         if (rx_buf) {
 358                                 memcpy_fromio(&rx_buf[bytes_recvd], par->reg_base +
 359                                               SPI_MST_RSP_BUF_OFFSET(p->hw_inst), len);
 360                                 bytes_recvd += len;
 361                         }
 362                 }
 363         }
 364         p->spi_xfer_in_progress = false;
 365
 366         return 0;
 367 }
 368
 369 static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
 370 {
 371         struct pci1xxxx_spi_internal *p = dev;
 372         irqreturn_t spi_int_fired = IRQ_NONE;
 373         u32 regval;
 374
 375         /* Clear the SPI GO_BIT Interrupt */
 376         regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
 377         if (regval & SPI_INTR) {
 378                 /* Clear xfer_done */
 379                 complete(&p->spi_xfer_done);
 380                 spi_int_fired = IRQ_HANDLED;
 381         }
 382
 383         writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
 384
 385         return spi_int_fired;
 386 }
 387
 388 static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 389 {
 390         u8 hw_inst_cnt, iter, start, only_sec_inst;
 391         struct pci1xxxx_spi_internal *spi_sub_ptr;
 392         struct device *dev = &pdev->dev;
 393         struct pci1xxxx_spi *spi_bus;
 394         struct spi_controller *spi_host;
 395         u32 regval;
 396         int ret;
 397
 398         hw_inst_cnt = ent->driver_data & 0x0f;
 399         start = (ent->driver_data & 0xf0) >> 4;
 400         if (start == 1)
 401                 only_sec_inst = 1;
 402         else
 403                 only_sec_inst = 0;
 404
 405         spi_bus = devm_kzalloc(&pdev->dev,
 406                                struct_size(spi_bus, spi_int, hw_inst_cnt),
 407                                GFP_KERNEL);
 408         if (!spi_bus)
 409                 return -ENOMEM;
 410
 411         spi_bus->dev = pdev;
 412         spi_bus->total_hw_instances = hw_inst_cnt;
 413         pci_set_master(pdev);
 414
 415         for (iter = 0; iter < hw_inst_cnt; iter++) {
 416                 spi_bus->spi_int[iter] = devm_kzalloc(&pdev->dev,
 417                                                       sizeof(struct pci1xxxx_spi_internal),
 418                                                       GFP_KERNEL);
 419                 spi_sub_ptr = spi_bus->spi_int[iter];
 420                 spi_sub_ptr->spi_host = devm_spi_alloc_host(dev, sizeof(struct spi_controller));
 421                 if (!spi_sub_ptr->spi_host)
 422                         return -ENOMEM;
 423
 424                 spi_sub_ptr->parent = spi_bus;
 425                 spi_sub_ptr->spi_xfer_in_progress = false;
 426
 427                 if (!iter) {
 428                         ret = pcim_enable_device(pdev);
 429                         if (ret)
 430                                 return -ENOMEM;
 431
 432                         ret = pci_request_regions(pdev, DRV_NAME);
 433                         if (ret)
 434                                 return -ENOMEM;
 435
 436                         spi_bus->reg_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
 437                         if (!spi_bus->reg_base) {
 438                                 ret = -EINVAL;
 439                                 goto error;
 440                         }
 441
 442                         ret = pci_alloc_irq_vectors(pdev, hw_inst_cnt, hw_inst_cnt,
 443                                                     PCI_IRQ_ALL_TYPES);
 444                         if (ret < 0) {
 445                                 dev_err(&pdev->dev, "Error allocating MSI vectors\n");
 446                                 goto error;
 447                         }
 448
 449                         init_completion(&spi_sub_ptr->spi_xfer_done);
 450                         /* Initialize Interrupts - SPI_INT */
 451                         regval = readl(spi_bus->reg_base +
 452                                        SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
 453                         regval &= ~SPI_INTR;
 454                         writel(regval, spi_bus->reg_base +
 455                                SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
 456                         spi_sub_ptr->irq = pci_irq_vector(pdev, 0);
 457
 458                         ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
 459                                                pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
 460                                                pci_name(pdev), spi_sub_ptr);
 461                         if (ret < 0) {
 462                                 dev_err(&pdev->dev, "Unable to request irq : %d",
 463                                         spi_sub_ptr->irq);
 464                                 ret = -ENODEV;
 465                                 goto error;
 466                         }
 467
 468                         ret = pci1xxxx_spi_dma_init(spi_bus, spi_sub_ptr->irq);
 469                         if (ret && ret != -EOPNOTSUPP)
 470                                 return ret;
 471
 472                         /* This register is only applicable for 1st instance */
 473                         regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
 474                         if (!only_sec_inst)
 475                                 regval |= (BIT(4));
 476                         else
 477                                 regval &= ~(BIT(4));
 478
 479                         writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
 480                 }
 481
 482                 spi_sub_ptr->hw_inst = start++;
 483
 484                 if (iter == 1) {
 485                         init_completion(&spi_sub_ptr->spi_xfer_done);
 486                         /* Initialize Interrupts - SPI_INT */
 487                         regval = readl(spi_bus->reg_base +
 488                                SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
 489                         regval &= ~SPI_INTR;
 490                         writel(regval, spi_bus->reg_base +
 491                                SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
 492                         spi_sub_ptr->irq = pci_irq_vector(pdev, iter);
 493                         ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
 494                                                pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
 495                                                pci_name(pdev), spi_sub_ptr);
 496                         if (ret < 0) {
 497                                 dev_err(&pdev->dev, "Unable to request irq : %d",
 498                                         spi_sub_ptr->irq);
 499                                 ret = -ENODEV;
 500                                 goto error;
 501                         }
 502                 }
 503
 504                 spi_host = spi_sub_ptr->spi_host;
 505                 spi_host->num_chipselect = SPI_CHIP_SEL_COUNT;
 506                 spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL |
 507                                       SPI_TX_DUAL | SPI_LOOP;
 508                 spi_host->transfer_one = pci1xxxx_spi_transfer_one;
 509                 spi_host->set_cs = pci1xxxx_spi_set_cs;
 510                 spi_host->bits_per_word_mask = SPI_BPW_MASK(8);
 511                 spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;
 512                 spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ;
 513                 spi_host->flags = SPI_CONTROLLER_MUST_TX;
 514                 spi_controller_set_devdata(spi_host, spi_sub_ptr);
 515                 ret = devm_spi_register_controller(dev, spi_host);
 516                 if (ret)
 517                         goto error;
 518         }
 519         pci_set_drvdata(pdev, spi_bus);
 520
 521         return 0;
 522
 523 error:
 524         pci_release_regions(pdev);
 525         return ret;
 526 }
 527
 528 static void store_restore_config(struct pci1xxxx_spi *spi_ptr,
 529                                  struct pci1xxxx_spi_internal *spi_sub_ptr,
 530                                  u8 inst, bool store)
 531 {
 532         u32 regval;
 533
 534         if (store) {
 535                 regval = readl(spi_ptr->reg_base +
 536                                SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst));
 537                 regval &= SPI_MST_CTL_DEVSEL_MASK;
 538                 spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7;
 539                 regval = readl(spi_ptr->reg_base +
 540                                SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst));
 541                 regval &= SPI_MSI_VECTOR_SEL_MASK;
 542                 spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1;
 543         } else {
 544                 regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
 545                 regval &= ~SPI_MST_CTL_DEVSEL_MASK;
 546                 regval |= (spi_sub_ptr->prev_val.dev_sel << 25);
 547                 writel(regval,
 548                        spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
 549                 writel((spi_sub_ptr->prev_val.msi_vector_sel << 4),
 550                         spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst));
 551         }
 552 }
 553
 554 static int pci1xxxx_spi_resume(struct device *dev)
 555 {
 556         struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
 557         struct pci1xxxx_spi_internal *spi_sub_ptr;
 558         u32 regval = SPI_RESUME_CONFIG;
 559         u8 iter;
 560
 561         for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
 562                 spi_sub_ptr = spi_ptr->spi_int[iter];
 563                 spi_controller_resume(spi_sub_ptr->spi_host);
 564                 writel(regval, spi_ptr->reg_base +
 565                        SPI_MST_EVENT_MASK_REG_OFFSET(iter));
 566
 567                 /* Restore config at resume */
 568                 store_restore_config(spi_ptr, spi_sub_ptr, iter, 0);
 569         }
 570
 571         return 0;
 572 }
 573
 574 static int pci1xxxx_spi_suspend(struct device *dev)
 575 {
 576         struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
 577         struct pci1xxxx_spi_internal *spi_sub_ptr;
 578         u32 reg1 = SPI_SUSPEND_CONFIG;
 579         u8 iter;
 580
 581         for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
 582                 spi_sub_ptr = spi_ptr->spi_int[iter];
 583
 584                 while (spi_sub_ptr->spi_xfer_in_progress)
 585                         msleep(20);
 586
 587                 /* Store existing config before suspend */
 588                 store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);
 589                 spi_controller_suspend(spi_sub_ptr->spi_host);
 590                 writel(reg1, spi_ptr->reg_base +
 591                        SPI_MST_EVENT_MASK_REG_OFFSET(iter));
 592         }
 593
 594         return 0;
 595 }
 596
 597 static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend,
 598                                 pci1xxxx_spi_resume);
 599
 600 static struct pci_driver pci1xxxx_spi_driver = {
 601         .name           = DRV_NAME,
 602         .id_table       = pci1xxxx_spi_pci_id_table,
 603         .probe          = pci1xxxx_spi_probe,
 604         .driver         =       {
 605                 .pm = pm_sleep_ptr(&spi_pm_ops),
 606         },
 607 };
 608
 609 module_pci_driver(pci1xxxx_spi_driver);
 610
 611 MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx SPI bus driver");
 612 MODULE_AUTHOR("Tharun Kumar P<tharunkumar.pasumarthi@microchip.com>");
 613 MODULE_AUTHOR("Kumaravel Thiagarajan<kumaravel.thiagarajan@microchip.com>");
 614 MODULE_LICENSE("GPL v2");