2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/delay.h>
15 #include <linux/platform_device.h>
16 #include <linux/err.h>
18 #include <linux/spi/spi.h>
19 #include <linux/module.h>
21 #include <linux/clk.h>
22 #include <asm/unaligned.h>
24 #define DRIVER_NAME "orion_spi"
26 #define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
27 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
29 #define ORION_SPI_IF_CTRL_REG 0x00
30 #define ORION_SPI_IF_CONFIG_REG 0x04
31 #define ORION_SPI_DATA_OUT_REG 0x08
32 #define ORION_SPI_DATA_IN_REG 0x0c
33 #define ORION_SPI_INT_CAUSE_REG 0x10
35 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
36 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
39 struct work_struct work;
41 /* Lock access to transfer list. */
44 struct list_head msg_queue;
45 struct spi_master *master;
47 unsigned int max_speed;
48 unsigned int min_speed;
52 static struct workqueue_struct *orion_spi_wq;
54 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
56 return orion_spi->base + reg;
60 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
62 void __iomem *reg_addr = spi_reg(orion_spi, reg);
65 val = readl(reg_addr);
67 writel(val, reg_addr);
71 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
73 void __iomem *reg_addr = spi_reg(orion_spi, reg);
76 val = readl(reg_addr);
78 writel(val, reg_addr);
81 static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
84 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
85 ORION_SPI_IF_8_16_BIT_MODE);
86 } else if (size == 8) {
87 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
88 ORION_SPI_IF_8_16_BIT_MODE);
90 pr_debug("Bad bits per word value %d (only 8 or 16 are "
98 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
104 struct orion_spi *orion_spi;
106 orion_spi = spi_master_get_devdata(spi->master);
108 tclk_hz = clk_get_rate(orion_spi->clk);
111 * the supported rates are: 4,6,8...30
112 * round up as we look for equal or less speed
114 rate = DIV_ROUND_UP(tclk_hz, speed);
115 rate = roundup(rate, 2);
117 /* check if requested speed is too small */
124 /* Convert the rate to SPI clock divisor value. */
125 prescale = 0x10 + rate/2;
127 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
128 reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
129 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
135 * called only when no transfer is active on the bus
138 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
140 struct orion_spi *orion_spi;
141 unsigned int speed = spi->max_speed_hz;
142 unsigned int bits_per_word = spi->bits_per_word;
145 orion_spi = spi_master_get_devdata(spi->master);
147 if ((t != NULL) && t->speed_hz)
150 if ((t != NULL) && t->bits_per_word)
151 bits_per_word = t->bits_per_word;
153 rc = orion_spi_baudrate_set(spi, speed);
157 return orion_spi_set_transfer_size(orion_spi, bits_per_word);
160 static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
163 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
165 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
168 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
172 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
173 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
183 orion_spi_write_read_8bit(struct spi_device *spi,
184 const u8 **tx_buf, u8 **rx_buf)
186 void __iomem *tx_reg, *rx_reg, *int_reg;
187 struct orion_spi *orion_spi;
189 orion_spi = spi_master_get_devdata(spi->master);
190 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
191 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
192 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
194 /* clear the interrupt cause register */
195 writel(0x0, int_reg);
197 if (tx_buf && *tx_buf)
198 writel(*(*tx_buf)++, tx_reg);
202 if (orion_spi_wait_till_ready(orion_spi) < 0) {
203 dev_err(&spi->dev, "TXS timed out\n");
207 if (rx_buf && *rx_buf)
208 *(*rx_buf)++ = readl(rx_reg);
214 orion_spi_write_read_16bit(struct spi_device *spi,
215 const u16 **tx_buf, u16 **rx_buf)
217 void __iomem *tx_reg, *rx_reg, *int_reg;
218 struct orion_spi *orion_spi;
220 orion_spi = spi_master_get_devdata(spi->master);
221 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
222 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
223 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
225 /* clear the interrupt cause register */
226 writel(0x0, int_reg);
228 if (tx_buf && *tx_buf)
229 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
233 if (orion_spi_wait_till_ready(orion_spi) < 0) {
234 dev_err(&spi->dev, "TXS timed out\n");
238 if (rx_buf && *rx_buf)
239 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
245 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
247 struct orion_spi *orion_spi;
251 orion_spi = spi_master_get_devdata(spi->master);
252 word_len = spi->bits_per_word;
256 const u8 *tx = xfer->tx_buf;
257 u8 *rx = xfer->rx_buf;
260 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
264 } else if (word_len == 16) {
265 const u16 *tx = xfer->tx_buf;
266 u16 *rx = xfer->rx_buf;
269 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
276 return xfer->len - count;
280 static void orion_spi_work(struct work_struct *work)
282 struct orion_spi *orion_spi =
283 container_of(work, struct orion_spi, work);
285 spin_lock_irq(&orion_spi->lock);
286 while (!list_empty(&orion_spi->msg_queue)) {
287 struct spi_message *m;
288 struct spi_device *spi;
289 struct spi_transfer *t = NULL;
290 int par_override = 0;
294 m = container_of(orion_spi->msg_queue.next, struct spi_message,
297 list_del_init(&m->queue);
298 spin_unlock_irq(&orion_spi->lock);
303 status = orion_spi_setup_transfer(spi, NULL);
308 list_for_each_entry(t, &m->transfers, transfer_list) {
309 if (par_override || t->speed_hz || t->bits_per_word) {
311 status = orion_spi_setup_transfer(spi, t);
314 if (!t->speed_hz && !t->bits_per_word)
319 orion_spi_set_cs(orion_spi, 1);
325 orion_spi_write_read(spi, t);
328 udelay(t->delay_usecs);
331 orion_spi_set_cs(orion_spi, 0);
338 orion_spi_set_cs(orion_spi, 0);
341 m->complete(m->context);
343 spin_lock_irq(&orion_spi->lock);
346 spin_unlock_irq(&orion_spi->lock);
349 static int __init orion_spi_reset(struct orion_spi *orion_spi)
351 /* Verify that the CS is deasserted */
352 orion_spi_set_cs(orion_spi, 0);
357 static int orion_spi_setup(struct spi_device *spi)
359 struct orion_spi *orion_spi;
361 orion_spi = spi_master_get_devdata(spi->master);
363 if ((spi->max_speed_hz == 0)
364 || (spi->max_speed_hz > orion_spi->max_speed))
365 spi->max_speed_hz = orion_spi->max_speed;
367 if (spi->max_speed_hz < orion_spi->min_speed) {
368 dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
374 * baudrate & width will be set orion_spi_setup_transfer
379 static int orion_spi_transfer(struct spi_device *spi, struct spi_message *m)
381 struct orion_spi *orion_spi;
382 struct spi_transfer *t = NULL;
385 m->actual_length = 0;
388 /* reject invalid messages and transfers */
389 if (list_empty(&m->transfers) || !m->complete)
392 orion_spi = spi_master_get_devdata(spi->master);
394 list_for_each_entry(t, &m->transfers, transfer_list) {
395 unsigned int bits_per_word = spi->bits_per_word;
397 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
399 "message rejected : "
400 "invalid transfer data buffers\n");
404 if (t->bits_per_word)
405 bits_per_word = t->bits_per_word;
407 if ((bits_per_word != 8) && (bits_per_word != 16)) {
409 "message rejected : "
410 "invalid transfer bits_per_word (%d bits)\n",
414 /*make sure buffer length is even when working in 16 bit mode*/
415 if ((t->bits_per_word == 16) && (t->len & 1)) {
417 "message rejected : "
418 "odd data length (%d) while in 16 bit mode\n",
423 if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
425 "message rejected : "
426 "device min speed (%d Hz) exceeds "
427 "required transfer speed (%d Hz)\n",
428 orion_spi->min_speed, t->speed_hz);
434 spin_lock_irqsave(&orion_spi->lock, flags);
435 list_add_tail(&m->queue, &orion_spi->msg_queue);
436 queue_work(orion_spi_wq, &orion_spi->work);
437 spin_unlock_irqrestore(&orion_spi->lock, flags);
441 /* Message rejected and not queued */
444 m->complete(m->context);
448 static int __init orion_spi_probe(struct platform_device *pdev)
450 struct spi_master *master;
451 struct orion_spi *spi;
453 unsigned long tclk_hz;
458 master = spi_alloc_master(&pdev->dev, sizeof *spi);
459 if (master == NULL) {
460 dev_dbg(&pdev->dev, "master allocation failed\n");
465 master->bus_num = pdev->id;
466 if (pdev->dev.of_node) {
467 iprop = of_get_property(pdev->dev.of_node, "cell-index",
469 if (iprop && size == sizeof(*iprop))
470 master->bus_num = *iprop;
473 /* we support only mode 0, and no options */
474 master->mode_bits = 0;
476 master->setup = orion_spi_setup;
477 master->transfer = orion_spi_transfer;
478 master->num_chipselect = ORION_NUM_CHIPSELECTS;
480 dev_set_drvdata(&pdev->dev, master);
482 spi = spi_master_get_devdata(master);
483 spi->master = master;
485 spi->clk = clk_get(&pdev->dev, NULL);
486 if (IS_ERR(spi->clk)) {
487 status = PTR_ERR(spi->clk);
491 clk_prepare(spi->clk);
492 clk_enable(spi->clk);
493 tclk_hz = clk_get_rate(spi->clk);
494 spi->max_speed = DIV_ROUND_UP(tclk_hz, 4);
495 spi->min_speed = DIV_ROUND_UP(tclk_hz, 30);
497 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
503 if (!request_mem_region(r->start, resource_size(r),
504 dev_name(&pdev->dev))) {
508 spi->base = ioremap(r->start, SZ_1K);
510 INIT_WORK(&spi->work, orion_spi_work);
512 spin_lock_init(&spi->lock);
513 INIT_LIST_HEAD(&spi->msg_queue);
515 if (orion_spi_reset(spi) < 0)
518 master->dev.of_node = pdev->dev.of_node;
519 status = spi_register_master(master);
526 release_mem_region(r->start, resource_size(r));
528 clk_disable_unprepare(spi->clk);
531 spi_master_put(master);
536 static int __exit orion_spi_remove(struct platform_device *pdev)
538 struct spi_master *master;
539 struct orion_spi *spi;
542 master = dev_get_drvdata(&pdev->dev);
543 spi = spi_master_get_devdata(master);
545 cancel_work_sync(&spi->work);
547 clk_disable_unprepare(spi->clk);
550 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
551 release_mem_region(r->start, resource_size(r));
553 spi_unregister_master(master);
558 MODULE_ALIAS("platform:" DRIVER_NAME);
560 static const struct of_device_id orion_spi_of_match_table[] __devinitdata = {
561 { .compatible = "marvell,orion-spi", },
564 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
566 static struct platform_driver orion_spi_driver = {
569 .owner = THIS_MODULE,
570 .of_match_table = of_match_ptr(orion_spi_of_match_table),
572 .remove = __exit_p(orion_spi_remove),
575 static int __init orion_spi_init(void)
577 orion_spi_wq = create_singlethread_workqueue(
578 orion_spi_driver.driver.name);
579 if (orion_spi_wq == NULL)
582 return platform_driver_probe(&orion_spi_driver, orion_spi_probe);
584 module_init(orion_spi_init);
586 static void __exit orion_spi_exit(void)
588 flush_workqueue(orion_spi_wq);
589 platform_driver_unregister(&orion_spi_driver);
591 destroy_workqueue(orion_spi_wq);
593 module_exit(orion_spi_exit);
595 MODULE_DESCRIPTION("Orion SPI driver");
596 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
597 MODULE_LICENSE("GPL");