1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
5 * Author: Shadi Ammouri <shadi@marvell.com>
6 * Copyright (C) 2007-2008 Marvell Ltd.
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/platform_device.h>
12 #include <linux/err.h>
14 #include <linux/spi/spi.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/clk.h>
21 #include <linux/sizes.h>
22 #include <asm/unaligned.h>
24 #define DRIVER_NAME "orion_spi"
26 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
27 #define SPI_AUTOSUSPEND_TIMEOUT 200
29 /* Some SoCs using this driver support up to 8 chip selects.
30 * It is up to the implementer to only use the chip selects
33 #define ORION_NUM_CHIPSELECTS 8
35 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
37 #define ORION_SPI_IF_CTRL_REG 0x00
38 #define ORION_SPI_IF_CONFIG_REG 0x04
39 #define ORION_SPI_IF_RXLSBF BIT(14)
40 #define ORION_SPI_IF_TXLSBF BIT(13)
41 #define ORION_SPI_DATA_OUT_REG 0x08
42 #define ORION_SPI_DATA_IN_REG 0x0c
43 #define ORION_SPI_INT_CAUSE_REG 0x10
44 #define ORION_SPI_TIMING_PARAMS_REG 0x18
46 /* Register for the "Direct Mode" */
47 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
49 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
50 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
51 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
53 #define ORION_SPI_MODE_CPOL (1 << 11)
54 #define ORION_SPI_MODE_CPHA (1 << 12)
55 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
56 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
57 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
58 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
60 #define ORION_SPI_CS_MASK 0x1C
61 #define ORION_SPI_CS_SHIFT 2
62 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
70 struct orion_spi_dev {
71 enum orion_spi_type typ;
73 * min_divisor and max_hz should be exclusive, the only we can
74 * have both is for managing the armada-370-spi case with old
78 unsigned int min_divisor;
79 unsigned int max_divisor;
81 bool is_errata_50mhz_ac;
84 struct orion_direct_acc {
89 struct orion_child_options {
90 struct orion_direct_acc direct_access;
94 struct spi_master *master;
98 const struct orion_spi_dev *devdata;
101 struct orion_child_options child[ORION_NUM_CHIPSELECTS];
105 static int orion_spi_runtime_suspend(struct device *dev);
106 static int orion_spi_runtime_resume(struct device *dev);
109 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
111 return orion_spi->base + reg;
115 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
117 void __iomem *reg_addr = spi_reg(orion_spi, reg);
120 val = readl(reg_addr);
122 writel(val, reg_addr);
126 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
128 void __iomem *reg_addr = spi_reg(orion_spi, reg);
131 val = readl(reg_addr);
133 writel(val, reg_addr);
136 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
142 struct orion_spi *orion_spi;
143 const struct orion_spi_dev *devdata;
145 orion_spi = spi_master_get_devdata(spi->master);
146 devdata = orion_spi->devdata;
148 tclk_hz = clk_get_rate(orion_spi->clk);
150 if (devdata->typ == ARMADA_SPI) {
152 * Given the core_clk (tclk_hz) and the target rate (speed) we
153 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
156 * core_clk / (SPR * 2 ** SPPR)
158 * is as big as possible but not bigger than speed.
161 /* best integer divider: */
162 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
166 /* This is the easy case, divider is less than 16 */
171 unsigned two_pow_sppr;
173 * Find the highest bit set in divider. This and the
174 * three next bits define SPR (apart from rounding).
175 * SPPR is then the number of zero bits that must be
178 sppr = fls(divider) - 4;
181 * As SPR only has 4 bits, we have to round divider up
182 * to the next multiple of 2 ** sppr.
184 two_pow_sppr = 1 << sppr;
185 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
188 * recalculate sppr as rounding up divider might have
189 * increased it enough to change the position of the
190 * highest set bit. In this case the bit that now
191 * doesn't make it into SPR is 0, so there is no need to
194 sppr = fls(divider) - 4;
195 spr = divider >> sppr;
198 * Now do range checking. SPR is constructed to have a
199 * width of 4 bits, so this is fine for sure. So we
200 * still need to check for sppr to fit into 3 bits:
206 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
209 * the supported rates are: 4,6,8...30
210 * round up as we look for equal or less speed
212 rate = DIV_ROUND_UP(tclk_hz, speed);
213 rate = roundup(rate, 2);
215 /* check if requested speed is too small */
222 /* Convert the rate to SPI clock divisor value. */
223 prescale = 0x10 + rate/2;
226 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
227 reg = ((reg & ~devdata->prescale_mask) | prescale);
228 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
234 orion_spi_mode_set(struct spi_device *spi)
237 struct orion_spi *orion_spi;
239 orion_spi = spi_master_get_devdata(spi->master);
241 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
242 reg &= ~ORION_SPI_MODE_MASK;
243 if (spi->mode & SPI_CPOL)
244 reg |= ORION_SPI_MODE_CPOL;
245 if (spi->mode & SPI_CPHA)
246 reg |= ORION_SPI_MODE_CPHA;
247 if (spi->mode & SPI_LSB_FIRST)
248 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
250 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
252 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
256 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
259 struct orion_spi *orion_spi;
261 orion_spi = spi_master_get_devdata(spi->master);
264 * Erratum description: (Erratum NO. FE-9144572) The device
265 * SPI interface supports frequencies of up to 50 MHz.
266 * However, due to this erratum, when the device core clock is
267 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
268 * clock and CPOL=CPHA=1 there might occur data corruption on
269 * reads from the SPI device.
270 * Erratum Workaround:
271 * Work in one of the following configurations:
272 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
274 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
275 * Register" before setting the interface.
277 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
278 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
280 if (clk_get_rate(orion_spi->clk) == 250000000 &&
281 speed == 50000000 && spi->mode & SPI_CPOL &&
282 spi->mode & SPI_CPHA)
283 reg |= ORION_SPI_TMISO_SAMPLE_2;
285 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
287 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
291 * called only when no transfer is active on the bus
294 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
296 struct orion_spi *orion_spi;
297 unsigned int speed = spi->max_speed_hz;
298 unsigned int bits_per_word = spi->bits_per_word;
301 orion_spi = spi_master_get_devdata(spi->master);
303 if ((t != NULL) && t->speed_hz)
306 if ((t != NULL) && t->bits_per_word)
307 bits_per_word = t->bits_per_word;
309 orion_spi_mode_set(spi);
311 if (orion_spi->devdata->is_errata_50mhz_ac)
312 orion_spi_50mhz_ac_timing_erratum(spi, speed);
314 rc = orion_spi_baudrate_set(spi, speed);
318 if (bits_per_word == 16)
319 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
320 ORION_SPI_IF_8_16_BIT_MODE);
322 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
323 ORION_SPI_IF_8_16_BIT_MODE);
328 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
330 struct orion_spi *orion_spi;
332 orion_spi = spi_master_get_devdata(spi->master);
335 * If this line is using a GPIO to control chip select, this internal
336 * .set_cs() function will still be called, so we clear any previous
337 * chip select. The CS we activate will not have any elecrical effect,
338 * as it is handled by a GPIO, but that doesn't matter. What we need
339 * is to deassert the old chip select and assert some other chip select.
341 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
342 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
343 ORION_SPI_CS(spi->chip_select));
346 * Chip select logic is inverted from spi_set_cs(). For lines using a
347 * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
348 * in the GPIO library, but we don't care about that, because in those
349 * cases we are dealing with an unused native CS anyways so the polarity
353 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
355 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
358 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
362 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
363 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
373 orion_spi_write_read_8bit(struct spi_device *spi,
374 const u8 **tx_buf, u8 **rx_buf)
376 void __iomem *tx_reg, *rx_reg, *int_reg;
377 struct orion_spi *orion_spi;
380 cs_single_byte = spi->mode & SPI_CS_WORD;
382 orion_spi = spi_master_get_devdata(spi->master);
385 orion_spi_set_cs(spi, 0);
387 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
388 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
389 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
391 /* clear the interrupt cause register */
392 writel(0x0, int_reg);
394 if (tx_buf && *tx_buf)
395 writel(*(*tx_buf)++, tx_reg);
399 if (orion_spi_wait_till_ready(orion_spi) < 0) {
400 if (cs_single_byte) {
401 orion_spi_set_cs(spi, 1);
402 /* Satisfy some SLIC devices requirements */
405 dev_err(&spi->dev, "TXS timed out\n");
409 if (rx_buf && *rx_buf)
410 *(*rx_buf)++ = readl(rx_reg);
412 if (cs_single_byte) {
413 orion_spi_set_cs(spi, 1);
414 /* Satisfy some SLIC devices requirements */
422 orion_spi_write_read_16bit(struct spi_device *spi,
423 const u16 **tx_buf, u16 **rx_buf)
425 void __iomem *tx_reg, *rx_reg, *int_reg;
426 struct orion_spi *orion_spi;
428 if (spi->mode & SPI_CS_WORD) {
429 dev_err(&spi->dev, "SPI_CS_WORD is only supported for 8 bit words\n");
433 orion_spi = spi_master_get_devdata(spi->master);
434 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
435 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
436 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
438 /* clear the interrupt cause register */
439 writel(0x0, int_reg);
441 if (tx_buf && *tx_buf)
442 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
446 if (orion_spi_wait_till_ready(orion_spi) < 0) {
447 dev_err(&spi->dev, "TXS timed out\n");
451 if (rx_buf && *rx_buf)
452 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
458 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
462 struct orion_spi *orion_spi;
463 int cs = spi->chip_select;
466 word_len = spi->bits_per_word;
469 orion_spi = spi_master_get_devdata(spi->master);
472 * Use SPI direct write mode if base address is available
473 * and SPI_CS_WORD flag is not set.
474 * Otherwise fall back to PIO mode for this transfer.
476 vaddr = orion_spi->child[cs].direct_access.vaddr;
478 if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & SPI_CS_WORD) == 0) {
479 unsigned int cnt = count / 4;
480 unsigned int rem = count % 4;
483 * Send the TX-data to the SPI device via the direct
484 * mapped address window
486 iowrite32_rep(vaddr, xfer->tx_buf, cnt);
488 u32 *buf = (u32 *)xfer->tx_buf;
490 iowrite8_rep(vaddr, &buf[cnt], rem);
497 const u8 *tx = xfer->tx_buf;
498 u8 *rx = xfer->rx_buf;
501 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
504 spi_delay_exec(&xfer->word_delay, xfer);
506 } else if (word_len == 16) {
507 const u16 *tx = xfer->tx_buf;
508 u16 *rx = xfer->rx_buf;
511 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
514 spi_delay_exec(&xfer->word_delay, xfer);
519 return xfer->len - count;
522 static int orion_spi_transfer_one(struct spi_master *master,
523 struct spi_device *spi,
524 struct spi_transfer *t)
528 status = orion_spi_setup_transfer(spi, t);
533 orion_spi_write_read(spi, t);
538 static int orion_spi_setup(struct spi_device *spi)
542 struct orion_spi *orion_spi = spi_master_get_devdata(spi->master);
543 struct device *dev = orion_spi->dev;
545 orion_spi_runtime_resume(dev);
548 ret = orion_spi_setup_transfer(spi, NULL);
551 orion_spi_runtime_suspend(dev);
557 static int orion_spi_reset(struct orion_spi *orion_spi)
559 /* Verify that the CS is deasserted */
560 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
562 /* Don't deassert CS between the direct mapped SPI transfers */
563 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
568 static const struct orion_spi_dev orion_spi_dev_data = {
572 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
575 static const struct orion_spi_dev armada_370_spi_dev_data = {
580 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
583 static const struct orion_spi_dev armada_xp_spi_dev_data = {
587 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
590 static const struct orion_spi_dev armada_375_spi_dev_data = {
594 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
597 static const struct orion_spi_dev armada_380_spi_dev_data = {
601 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
602 .is_errata_50mhz_ac = true,
605 static const struct of_device_id orion_spi_of_match_table[] = {
607 .compatible = "marvell,orion-spi",
608 .data = &orion_spi_dev_data,
611 .compatible = "marvell,armada-370-spi",
612 .data = &armada_370_spi_dev_data,
615 .compatible = "marvell,armada-375-spi",
616 .data = &armada_375_spi_dev_data,
619 .compatible = "marvell,armada-380-spi",
620 .data = &armada_380_spi_dev_data,
623 .compatible = "marvell,armada-390-spi",
624 .data = &armada_xp_spi_dev_data,
627 .compatible = "marvell,armada-xp-spi",
628 .data = &armada_xp_spi_dev_data,
633 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
635 static int orion_spi_probe(struct platform_device *pdev)
637 const struct of_device_id *of_id;
638 const struct orion_spi_dev *devdata;
639 struct spi_master *master;
640 struct orion_spi *spi;
642 unsigned long tclk_hz;
644 struct device_node *np;
646 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
647 if (master == NULL) {
648 dev_dbg(&pdev->dev, "master allocation failed\n");
653 master->bus_num = pdev->id;
654 if (pdev->dev.of_node) {
657 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
659 master->bus_num = cell_index;
662 /* we support all 4 SPI modes and LSB first option */
663 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;
664 master->set_cs = orion_spi_set_cs;
665 master->transfer_one = orion_spi_transfer_one;
666 master->num_chipselect = ORION_NUM_CHIPSELECTS;
667 master->setup = orion_spi_setup;
668 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
669 master->auto_runtime_pm = true;
670 master->use_gpio_descriptors = true;
671 master->flags = SPI_MASTER_GPIO_SS;
673 platform_set_drvdata(pdev, master);
675 spi = spi_master_get_devdata(master);
676 spi->master = master;
677 spi->dev = &pdev->dev;
679 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
680 devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
681 spi->devdata = devdata;
683 spi->clk = devm_clk_get(&pdev->dev, NULL);
684 if (IS_ERR(spi->clk)) {
685 status = PTR_ERR(spi->clk);
689 status = clk_prepare_enable(spi->clk);
693 /* The following clock is only used by some SoCs */
694 spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
695 if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
696 status = -EPROBE_DEFER;
699 if (!IS_ERR(spi->axi_clk))
700 clk_prepare_enable(spi->axi_clk);
702 tclk_hz = clk_get_rate(spi->clk);
705 * With old device tree, armada-370-spi could be used with
706 * Armada XP, however for this SoC the maximum frequency is
707 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
708 * higher than 200MHz. So, in order to be able to handle both
709 * SoCs, we can take the minimum of 50MHz and tclk/4.
711 if (of_device_is_compatible(pdev->dev.of_node,
712 "marvell,armada-370-spi"))
713 master->max_speed_hz = min(devdata->max_hz,
714 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
715 else if (devdata->min_divisor)
716 master->max_speed_hz =
717 DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
719 master->max_speed_hz = devdata->max_hz;
720 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
722 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
723 spi->base = devm_ioremap_resource(&pdev->dev, r);
724 if (IS_ERR(spi->base)) {
725 status = PTR_ERR(spi->base);
726 goto out_rel_axi_clk;
729 for_each_available_child_of_node(pdev->dev.of_node, np) {
730 struct orion_direct_acc *dir_acc;
733 /* Get chip-select number from the "reg" property */
734 status = of_property_read_u32(np, "reg", &cs);
737 "%pOF has no valid 'reg' property (%d)\n",
743 * Check if an address is configured for this SPI device. If
744 * not, the MBus mapping via the 'ranges' property in the 'soc'
745 * node is not configured and this device should not use the
746 * direct mode. In this case, just continue with the next
749 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
754 * Only map one page for direct access. This is enough for the
755 * simple TX transfer which only writes to the first word.
756 * This needs to get extended for the direct SPI NOR / SPI NAND
757 * support, once this gets implemented.
759 dir_acc = &spi->child[cs].direct_access;
760 dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
761 if (!dir_acc->vaddr) {
763 goto out_rel_axi_clk;
765 dir_acc->size = PAGE_SIZE;
767 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
770 pm_runtime_set_active(&pdev->dev);
771 pm_runtime_use_autosuspend(&pdev->dev);
772 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
773 pm_runtime_enable(&pdev->dev);
775 status = orion_spi_reset(spi);
779 master->dev.of_node = pdev->dev.of_node;
780 status = spi_register_master(master);
787 pm_runtime_disable(&pdev->dev);
789 clk_disable_unprepare(spi->axi_clk);
791 clk_disable_unprepare(spi->clk);
793 spi_master_put(master);
798 static int orion_spi_remove(struct platform_device *pdev)
800 struct spi_master *master = platform_get_drvdata(pdev);
801 struct orion_spi *spi = spi_master_get_devdata(master);
803 pm_runtime_get_sync(&pdev->dev);
804 clk_disable_unprepare(spi->axi_clk);
805 clk_disable_unprepare(spi->clk);
807 spi_unregister_master(master);
808 pm_runtime_disable(&pdev->dev);
813 MODULE_ALIAS("platform:" DRIVER_NAME);
816 static int orion_spi_runtime_suspend(struct device *dev)
818 struct spi_master *master = dev_get_drvdata(dev);
819 struct orion_spi *spi = spi_master_get_devdata(master);
821 clk_disable_unprepare(spi->axi_clk);
822 clk_disable_unprepare(spi->clk);
826 static int orion_spi_runtime_resume(struct device *dev)
828 struct spi_master *master = dev_get_drvdata(dev);
829 struct orion_spi *spi = spi_master_get_devdata(master);
831 if (!IS_ERR(spi->axi_clk))
832 clk_prepare_enable(spi->axi_clk);
833 return clk_prepare_enable(spi->clk);
837 static const struct dev_pm_ops orion_spi_pm_ops = {
838 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
839 orion_spi_runtime_resume,
843 static struct platform_driver orion_spi_driver = {
846 .pm = &orion_spi_pm_ops,
847 .of_match_table = of_match_ptr(orion_spi_of_match_table),
849 .probe = orion_spi_probe,
850 .remove = orion_spi_remove,
853 module_platform_driver(orion_spi_driver);
855 MODULE_DESCRIPTION("Orion SPI driver");
856 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
857 MODULE_LICENSE("GPL");