2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/clk.h>
24 #include <linux/sizes.h>
25 #include <linux/gpio.h>
26 #include <asm/unaligned.h>
28 #define DRIVER_NAME "orion_spi"
30 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
31 #define SPI_AUTOSUSPEND_TIMEOUT 200
33 /* Some SoCs using this driver support up to 8 chip selects.
34 * It is up to the implementer to only use the chip selects
37 #define ORION_NUM_CHIPSELECTS 8
39 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
41 #define ORION_SPI_IF_CTRL_REG 0x00
42 #define ORION_SPI_IF_CONFIG_REG 0x04
43 #define ORION_SPI_IF_RXLSBF BIT(14)
44 #define ORION_SPI_IF_TXLSBF BIT(13)
45 #define ORION_SPI_DATA_OUT_REG 0x08
46 #define ORION_SPI_DATA_IN_REG 0x0c
47 #define ORION_SPI_INT_CAUSE_REG 0x10
48 #define ORION_SPI_TIMING_PARAMS_REG 0x18
50 /* Register for the "Direct Mode" */
51 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
53 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
54 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
55 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
57 #define ORION_SPI_MODE_CPOL (1 << 11)
58 #define ORION_SPI_MODE_CPHA (1 << 12)
59 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
60 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
61 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
62 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
64 #define ORION_SPI_CS_MASK 0x1C
65 #define ORION_SPI_CS_SHIFT 2
66 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
74 struct orion_spi_dev {
75 enum orion_spi_type typ;
77 * min_divisor and max_hz should be exclusive, the only we can
78 * have both is for managing the armada-370-spi case with old
82 unsigned int min_divisor;
83 unsigned int max_divisor;
85 bool is_errata_50mhz_ac;
88 struct orion_direct_acc {
94 struct spi_master *master;
98 const struct orion_spi_dev *devdata;
100 struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS];
103 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
105 return orion_spi->base + reg;
109 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
111 void __iomem *reg_addr = spi_reg(orion_spi, reg);
114 val = readl(reg_addr);
116 writel(val, reg_addr);
120 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
122 void __iomem *reg_addr = spi_reg(orion_spi, reg);
125 val = readl(reg_addr);
127 writel(val, reg_addr);
130 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
136 struct orion_spi *orion_spi;
137 const struct orion_spi_dev *devdata;
139 orion_spi = spi_master_get_devdata(spi->master);
140 devdata = orion_spi->devdata;
142 tclk_hz = clk_get_rate(orion_spi->clk);
144 if (devdata->typ == ARMADA_SPI) {
146 * Given the core_clk (tclk_hz) and the target rate (speed) we
147 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
150 * core_clk / (SPR * 2 ** SPPR)
152 * is as big as possible but not bigger than speed.
155 /* best integer divider: */
156 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
160 /* This is the easy case, divider is less than 16 */
165 unsigned two_pow_sppr;
167 * Find the highest bit set in divider. This and the
168 * three next bits define SPR (apart from rounding).
169 * SPPR is then the number of zero bits that must be
172 sppr = fls(divider) - 4;
175 * As SPR only has 4 bits, we have to round divider up
176 * to the next multiple of 2 ** sppr.
178 two_pow_sppr = 1 << sppr;
179 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
182 * recalculate sppr as rounding up divider might have
183 * increased it enough to change the position of the
184 * highest set bit. In this case the bit that now
185 * doesn't make it into SPR is 0, so there is no need to
188 sppr = fls(divider) - 4;
189 spr = divider >> sppr;
192 * Now do range checking. SPR is constructed to have a
193 * width of 4 bits, so this is fine for sure. So we
194 * still need to check for sppr to fit into 3 bits:
200 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
203 * the supported rates are: 4,6,8...30
204 * round up as we look for equal or less speed
206 rate = DIV_ROUND_UP(tclk_hz, speed);
207 rate = roundup(rate, 2);
209 /* check if requested speed is too small */
216 /* Convert the rate to SPI clock divisor value. */
217 prescale = 0x10 + rate/2;
220 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
221 reg = ((reg & ~devdata->prescale_mask) | prescale);
222 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
228 orion_spi_mode_set(struct spi_device *spi)
231 struct orion_spi *orion_spi;
233 orion_spi = spi_master_get_devdata(spi->master);
235 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
236 reg &= ~ORION_SPI_MODE_MASK;
237 if (spi->mode & SPI_CPOL)
238 reg |= ORION_SPI_MODE_CPOL;
239 if (spi->mode & SPI_CPHA)
240 reg |= ORION_SPI_MODE_CPHA;
241 if (spi->mode & SPI_LSB_FIRST)
242 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
244 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
246 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
250 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
253 struct orion_spi *orion_spi;
255 orion_spi = spi_master_get_devdata(spi->master);
258 * Erratum description: (Erratum NO. FE-9144572) The device
259 * SPI interface supports frequencies of up to 50 MHz.
260 * However, due to this erratum, when the device core clock is
261 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
262 * clock and CPOL=CPHA=1 there might occur data corruption on
263 * reads from the SPI device.
264 * Erratum Workaround:
265 * Work in one of the following configurations:
266 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
268 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
269 * Register" before setting the interface.
271 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
272 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
274 if (clk_get_rate(orion_spi->clk) == 250000000 &&
275 speed == 50000000 && spi->mode & SPI_CPOL &&
276 spi->mode & SPI_CPHA)
277 reg |= ORION_SPI_TMISO_SAMPLE_2;
279 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
281 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
285 * called only when no transfer is active on the bus
288 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
290 struct orion_spi *orion_spi;
291 unsigned int speed = spi->max_speed_hz;
292 unsigned int bits_per_word = spi->bits_per_word;
295 orion_spi = spi_master_get_devdata(spi->master);
297 if ((t != NULL) && t->speed_hz)
300 if ((t != NULL) && t->bits_per_word)
301 bits_per_word = t->bits_per_word;
303 orion_spi_mode_set(spi);
305 if (orion_spi->devdata->is_errata_50mhz_ac)
306 orion_spi_50mhz_ac_timing_erratum(spi, speed);
308 rc = orion_spi_baudrate_set(spi, speed);
312 if (bits_per_word == 16)
313 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
314 ORION_SPI_IF_8_16_BIT_MODE);
316 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
317 ORION_SPI_IF_8_16_BIT_MODE);
322 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
324 struct orion_spi *orion_spi;
327 if (gpio_is_valid(spi->cs_gpio))
330 cs = spi->chip_select;
332 orion_spi = spi_master_get_devdata(spi->master);
334 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
335 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
338 /* Chip select logic is inverted from spi_set_cs */
340 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
342 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
345 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
349 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
350 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
360 orion_spi_write_read_8bit(struct spi_device *spi,
361 const u8 **tx_buf, u8 **rx_buf)
363 void __iomem *tx_reg, *rx_reg, *int_reg;
364 struct orion_spi *orion_spi;
366 orion_spi = spi_master_get_devdata(spi->master);
367 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
368 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
369 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
371 /* clear the interrupt cause register */
372 writel(0x0, int_reg);
374 if (tx_buf && *tx_buf)
375 writel(*(*tx_buf)++, tx_reg);
379 if (orion_spi_wait_till_ready(orion_spi) < 0) {
380 dev_err(&spi->dev, "TXS timed out\n");
384 if (rx_buf && *rx_buf)
385 *(*rx_buf)++ = readl(rx_reg);
391 orion_spi_write_read_16bit(struct spi_device *spi,
392 const u16 **tx_buf, u16 **rx_buf)
394 void __iomem *tx_reg, *rx_reg, *int_reg;
395 struct orion_spi *orion_spi;
397 orion_spi = spi_master_get_devdata(spi->master);
398 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
399 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
400 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
402 /* clear the interrupt cause register */
403 writel(0x0, int_reg);
405 if (tx_buf && *tx_buf)
406 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
410 if (orion_spi_wait_till_ready(orion_spi) < 0) {
411 dev_err(&spi->dev, "TXS timed out\n");
415 if (rx_buf && *rx_buf)
416 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
422 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
426 struct orion_spi *orion_spi;
427 int cs = spi->chip_select;
429 word_len = spi->bits_per_word;
432 orion_spi = spi_master_get_devdata(spi->master);
435 * Use SPI direct write mode if base address is available. Otherwise
436 * fall back to PIO mode for this transfer.
438 if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) &&
440 unsigned int cnt = count / 4;
441 unsigned int rem = count % 4;
444 * Send the TX-data to the SPI device via the direct
445 * mapped address window
447 iowrite32_rep(orion_spi->direct_access[cs].vaddr,
450 u32 *buf = (u32 *)xfer->tx_buf;
452 iowrite8_rep(orion_spi->direct_access[cs].vaddr,
460 const u8 *tx = xfer->tx_buf;
461 u8 *rx = xfer->rx_buf;
464 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
468 } else if (word_len == 16) {
469 const u16 *tx = xfer->tx_buf;
470 u16 *rx = xfer->rx_buf;
473 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
480 return xfer->len - count;
483 static int orion_spi_transfer_one(struct spi_master *master,
484 struct spi_device *spi,
485 struct spi_transfer *t)
489 status = orion_spi_setup_transfer(spi, t);
494 orion_spi_write_read(spi, t);
499 static int orion_spi_setup(struct spi_device *spi)
501 return orion_spi_setup_transfer(spi, NULL);
504 static int orion_spi_reset(struct orion_spi *orion_spi)
506 /* Verify that the CS is deasserted */
507 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
509 /* Don't deassert CS between the direct mapped SPI transfers */
510 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
515 static const struct orion_spi_dev orion_spi_dev_data = {
519 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
522 static const struct orion_spi_dev armada_370_spi_dev_data = {
527 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
530 static const struct orion_spi_dev armada_xp_spi_dev_data = {
534 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
537 static const struct orion_spi_dev armada_375_spi_dev_data = {
541 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
544 static const struct orion_spi_dev armada_380_spi_dev_data = {
548 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
549 .is_errata_50mhz_ac = true,
552 static const struct of_device_id orion_spi_of_match_table[] = {
554 .compatible = "marvell,orion-spi",
555 .data = &orion_spi_dev_data,
558 .compatible = "marvell,armada-370-spi",
559 .data = &armada_370_spi_dev_data,
562 .compatible = "marvell,armada-375-spi",
563 .data = &armada_375_spi_dev_data,
566 .compatible = "marvell,armada-380-spi",
567 .data = &armada_380_spi_dev_data,
570 .compatible = "marvell,armada-390-spi",
571 .data = &armada_xp_spi_dev_data,
574 .compatible = "marvell,armada-xp-spi",
575 .data = &armada_xp_spi_dev_data,
580 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
582 static int orion_spi_probe(struct platform_device *pdev)
584 const struct of_device_id *of_id;
585 const struct orion_spi_dev *devdata;
586 struct spi_master *master;
587 struct orion_spi *spi;
589 unsigned long tclk_hz;
591 struct device_node *np;
593 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
594 if (master == NULL) {
595 dev_dbg(&pdev->dev, "master allocation failed\n");
600 master->bus_num = pdev->id;
601 if (pdev->dev.of_node) {
604 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
606 master->bus_num = cell_index;
609 /* we support all 4 SPI modes and LSB first option */
610 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
611 master->set_cs = orion_spi_set_cs;
612 master->transfer_one = orion_spi_transfer_one;
613 master->num_chipselect = ORION_NUM_CHIPSELECTS;
614 master->setup = orion_spi_setup;
615 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
616 master->auto_runtime_pm = true;
617 master->flags = SPI_MASTER_GPIO_SS;
619 platform_set_drvdata(pdev, master);
621 spi = spi_master_get_devdata(master);
622 spi->master = master;
624 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
625 devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
626 spi->devdata = devdata;
628 spi->clk = devm_clk_get(&pdev->dev, NULL);
629 if (IS_ERR(spi->clk)) {
630 status = PTR_ERR(spi->clk);
634 status = clk_prepare_enable(spi->clk);
638 /* The following clock is only used by some SoCs */
639 spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
640 if (IS_ERR(spi->axi_clk) &&
641 PTR_ERR(spi->axi_clk) == -EPROBE_DEFER)
642 return -EPROBE_DEFER;
643 if (!IS_ERR(spi->axi_clk))
644 clk_prepare_enable(spi->axi_clk);
646 tclk_hz = clk_get_rate(spi->clk);
649 * With old device tree, armada-370-spi could be used with
650 * Armada XP, however for this SoC the maximum frequency is
651 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
652 * higher than 200MHz. So, in order to be able to handle both
653 * SoCs, we can take the minimum of 50MHz and tclk/4.
655 if (of_device_is_compatible(pdev->dev.of_node,
656 "marvell,armada-370-spi"))
657 master->max_speed_hz = min(devdata->max_hz,
658 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
659 else if (devdata->min_divisor)
660 master->max_speed_hz =
661 DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
663 master->max_speed_hz = devdata->max_hz;
664 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
666 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
667 spi->base = devm_ioremap_resource(&pdev->dev, r);
668 if (IS_ERR(spi->base)) {
669 status = PTR_ERR(spi->base);
673 /* Scan all SPI devices of this controller for direct mapped devices */
674 for_each_available_child_of_node(pdev->dev.of_node, np) {
677 /* Get chip-select number from the "reg" property */
678 status = of_property_read_u32(np, "reg", &cs);
681 "%pOF has no valid 'reg' property (%d)\n",
687 * Check if an address is configured for this SPI device. If
688 * not, the MBus mapping via the 'ranges' property in the 'soc'
689 * node is not configured and this device should not use the
690 * direct mode. In this case, just continue with the next
693 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
698 * Only map one page for direct access. This is enough for the
699 * simple TX transfer which only writes to the first word.
700 * This needs to get extended for the direct SPI-NOR / SPI-NAND
701 * support, once this gets implemented.
703 spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev,
706 if (!spi->direct_access[cs].vaddr) {
710 spi->direct_access[cs].size = PAGE_SIZE;
712 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
715 pm_runtime_set_active(&pdev->dev);
716 pm_runtime_use_autosuspend(&pdev->dev);
717 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
718 pm_runtime_enable(&pdev->dev);
720 status = orion_spi_reset(spi);
724 pm_runtime_mark_last_busy(&pdev->dev);
725 pm_runtime_put_autosuspend(&pdev->dev);
727 master->dev.of_node = pdev->dev.of_node;
728 status = spi_register_master(master);
735 pm_runtime_disable(&pdev->dev);
737 clk_disable_unprepare(spi->axi_clk);
738 clk_disable_unprepare(spi->clk);
740 spi_master_put(master);
745 static int orion_spi_remove(struct platform_device *pdev)
747 struct spi_master *master = platform_get_drvdata(pdev);
748 struct orion_spi *spi = spi_master_get_devdata(master);
750 pm_runtime_get_sync(&pdev->dev);
751 clk_disable_unprepare(spi->axi_clk);
752 clk_disable_unprepare(spi->clk);
754 spi_unregister_master(master);
755 pm_runtime_disable(&pdev->dev);
760 MODULE_ALIAS("platform:" DRIVER_NAME);
763 static int orion_spi_runtime_suspend(struct device *dev)
765 struct spi_master *master = dev_get_drvdata(dev);
766 struct orion_spi *spi = spi_master_get_devdata(master);
768 clk_disable_unprepare(spi->axi_clk);
769 clk_disable_unprepare(spi->clk);
773 static int orion_spi_runtime_resume(struct device *dev)
775 struct spi_master *master = dev_get_drvdata(dev);
776 struct orion_spi *spi = spi_master_get_devdata(master);
778 if (!IS_ERR(spi->axi_clk))
779 clk_prepare_enable(spi->axi_clk);
780 return clk_prepare_enable(spi->clk);
784 static const struct dev_pm_ops orion_spi_pm_ops = {
785 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
786 orion_spi_runtime_resume,
790 static struct platform_driver orion_spi_driver = {
793 .pm = &orion_spi_pm_ops,
794 .of_match_table = of_match_ptr(orion_spi_of_match_table),
796 .probe = orion_spi_probe,
797 .remove = orion_spi_remove,
800 module_platform_driver(orion_spi_driver);
802 MODULE_DESCRIPTION("Orion SPI driver");
803 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
804 MODULE_LICENSE("GPL");