1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
21 #include <linux/dma-mapping.h>
23 #define SPI_CFG0_REG 0x0000
24 #define SPI_CFG1_REG 0x0004
25 #define SPI_TX_SRC_REG 0x0008
26 #define SPI_RX_DST_REG 0x000c
27 #define SPI_TX_DATA_REG 0x0010
28 #define SPI_RX_DATA_REG 0x0014
29 #define SPI_CMD_REG 0x0018
30 #define SPI_STATUS0_REG 0x001c
31 #define SPI_PAD_SEL_REG 0x0024
32 #define SPI_CFG2_REG 0x0028
33 #define SPI_TX_SRC_REG_64 0x002c
34 #define SPI_RX_DST_REG_64 0x0030
35 #define SPI_CFG3_IPM_REG 0x0040
37 #define SPI_CFG0_SCK_HIGH_OFFSET 0
38 #define SPI_CFG0_SCK_LOW_OFFSET 8
39 #define SPI_CFG0_CS_HOLD_OFFSET 16
40 #define SPI_CFG0_CS_SETUP_OFFSET 24
41 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
42 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
44 #define SPI_CFG1_CS_IDLE_OFFSET 0
45 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
46 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
47 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29
48 #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30
50 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
51 #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000
53 #define SPI_CFG1_CS_IDLE_MASK 0xff
54 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
55 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
56 #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
57 #define SPI_CFG2_SCK_HIGH_OFFSET 0
58 #define SPI_CFG2_SCK_LOW_OFFSET 16
60 #define SPI_CMD_ACT BIT(0)
61 #define SPI_CMD_RESUME BIT(1)
62 #define SPI_CMD_RST BIT(2)
63 #define SPI_CMD_PAUSE_EN BIT(4)
64 #define SPI_CMD_DEASSERT BIT(5)
65 #define SPI_CMD_SAMPLE_SEL BIT(6)
66 #define SPI_CMD_CS_POL BIT(7)
67 #define SPI_CMD_CPHA BIT(8)
68 #define SPI_CMD_CPOL BIT(9)
69 #define SPI_CMD_RX_DMA BIT(10)
70 #define SPI_CMD_TX_DMA BIT(11)
71 #define SPI_CMD_TXMSBF BIT(12)
72 #define SPI_CMD_RXMSBF BIT(13)
73 #define SPI_CMD_RX_ENDIAN BIT(14)
74 #define SPI_CMD_TX_ENDIAN BIT(15)
75 #define SPI_CMD_FINISH_IE BIT(16)
76 #define SPI_CMD_PAUSE_IE BIT(17)
77 #define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
78 #define SPI_CMD_IPM_SPIM_LOOP BIT(21)
79 #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
81 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)
83 #define PIN_MODE_CFG(x) ((x) / 2)
85 #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
86 #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
87 #define SPI_CFG3_IPM_XMODE_EN BIT(4)
88 #define SPI_CFG3_IPM_NODATA_FLAG BIT(5)
89 #define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8
90 #define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12
92 #define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0)
93 #define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8)
94 #define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12)
96 #define MT8173_SPI_MAX_PAD_SEL 3
98 #define MTK_SPI_PAUSE_INT_STATUS 0x2
100 #define MTK_SPI_IDLE 0
101 #define MTK_SPI_PAUSED 1
103 #define MTK_SPI_MAX_FIFO_SIZE 32U
104 #define MTK_SPI_PACKET_SIZE 1024
105 #define MTK_SPI_IPM_PACKET_SIZE SZ_64K
106 #define MTK_SPI_IPM_PACKET_LOOP SZ_256
108 #define MTK_SPI_32BITS_MASK (0xffffffff)
110 #define DMA_ADDR_EXT_BITS (36)
111 #define DMA_ADDR_DEF_BITS (32)
113 struct mtk_spi_compatible {
115 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
117 /* some IC design adjust cfg register to enhance time accuracy */
119 /* some IC support DMA addr extension */
121 /* some IC no need unprepare SPI clk */
122 bool no_need_unprepare;
123 /* IPM design adjust and extend register to support more features */
132 struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk;
133 struct spi_transfer *cur_transfer;
136 struct scatterlist *tx_sgl, *rx_sgl;
137 u32 tx_sgl_len, rx_sgl_len;
138 const struct mtk_spi_compatible *dev_comp;
140 struct completion spimem_done;
147 static const struct mtk_spi_compatible mtk_common_compat;
149 static const struct mtk_spi_compatible mt2712_compat = {
153 static const struct mtk_spi_compatible mtk_ipm_compat = {
154 .enhance_timing = true,
159 static const struct mtk_spi_compatible mt6765_compat = {
160 .need_pad_sel = true,
162 .enhance_timing = true,
166 static const struct mtk_spi_compatible mt7622_compat = {
168 .enhance_timing = true,
171 static const struct mtk_spi_compatible mt8173_compat = {
172 .need_pad_sel = true,
176 static const struct mtk_spi_compatible mt8183_compat = {
177 .need_pad_sel = true,
179 .enhance_timing = true,
182 static const struct mtk_spi_compatible mt6893_compat = {
183 .need_pad_sel = true,
185 .enhance_timing = true,
187 .no_need_unprepare = true,
191 * A piece of default chip info unless the platform
194 static const struct mtk_chip_config mtk_default_chip_info = {
199 static const struct of_device_id mtk_spi_of_match[] = {
200 { .compatible = "mediatek,spi-ipm",
201 .data = (void *)&mtk_ipm_compat,
203 { .compatible = "mediatek,mt2701-spi",
204 .data = (void *)&mtk_common_compat,
206 { .compatible = "mediatek,mt2712-spi",
207 .data = (void *)&mt2712_compat,
209 { .compatible = "mediatek,mt6589-spi",
210 .data = (void *)&mtk_common_compat,
212 { .compatible = "mediatek,mt6765-spi",
213 .data = (void *)&mt6765_compat,
215 { .compatible = "mediatek,mt7622-spi",
216 .data = (void *)&mt7622_compat,
218 { .compatible = "mediatek,mt7629-spi",
219 .data = (void *)&mt7622_compat,
221 { .compatible = "mediatek,mt8135-spi",
222 .data = (void *)&mtk_common_compat,
224 { .compatible = "mediatek,mt8173-spi",
225 .data = (void *)&mt8173_compat,
227 { .compatible = "mediatek,mt8183-spi",
228 .data = (void *)&mt8183_compat,
230 { .compatible = "mediatek,mt8192-spi",
231 .data = (void *)&mt6765_compat,
233 { .compatible = "mediatek,mt6893-spi",
234 .data = (void *)&mt6893_compat,
238 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
240 static void mtk_spi_reset(struct mtk_spi *mdata)
244 /* set the software reset bit in SPI_CMD_REG. */
245 reg_val = readl(mdata->base + SPI_CMD_REG);
246 reg_val |= SPI_CMD_RST;
247 writel(reg_val, mdata->base + SPI_CMD_REG);
249 reg_val = readl(mdata->base + SPI_CMD_REG);
250 reg_val &= ~SPI_CMD_RST;
251 writel(reg_val, mdata->base + SPI_CMD_REG);
254 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
256 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
257 struct spi_delay *cs_setup = &spi->cs_setup;
258 struct spi_delay *cs_hold = &spi->cs_hold;
259 struct spi_delay *cs_inactive = &spi->cs_inactive;
260 u32 setup, hold, inactive;
264 delay = spi_delay_to_ns(cs_setup, NULL);
267 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
269 delay = spi_delay_to_ns(cs_hold, NULL);
272 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
274 delay = spi_delay_to_ns(cs_inactive, NULL);
277 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
280 reg_val = readl(mdata->base + SPI_CFG0_REG);
281 if (mdata->dev_comp->enhance_timing) {
283 hold = min_t(u32, hold, 0x10000);
284 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
285 reg_val |= (((hold - 1) & 0xffff)
286 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
289 setup = min_t(u32, setup, 0x10000);
290 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
291 reg_val |= (((setup - 1) & 0xffff)
292 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
296 hold = min_t(u32, hold, 0x100);
297 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
298 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
301 setup = min_t(u32, setup, 0x100);
302 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
303 reg_val |= (((setup - 1) & 0xff)
304 << SPI_CFG0_CS_SETUP_OFFSET);
307 writel(reg_val, mdata->base + SPI_CFG0_REG);
311 inactive = min_t(u32, inactive, 0x100);
312 reg_val = readl(mdata->base + SPI_CFG1_REG);
313 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
314 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
315 writel(reg_val, mdata->base + SPI_CFG1_REG);
321 static int mtk_spi_hw_init(struct spi_master *master,
322 struct spi_device *spi)
326 struct mtk_chip_config *chip_config = spi->controller_data;
327 struct mtk_spi *mdata = spi_master_get_devdata(master);
329 cpha = spi->mode & SPI_CPHA ? 1 : 0;
330 cpol = spi->mode & SPI_CPOL ? 1 : 0;
332 reg_val = readl(mdata->base + SPI_CMD_REG);
333 if (mdata->dev_comp->ipm_design) {
334 /* SPI transfer without idle time until packet length done */
335 reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
336 if (spi->mode & SPI_LOOP)
337 reg_val |= SPI_CMD_IPM_SPIM_LOOP;
339 reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
343 reg_val |= SPI_CMD_CPHA;
345 reg_val &= ~SPI_CMD_CPHA;
347 reg_val |= SPI_CMD_CPOL;
349 reg_val &= ~SPI_CMD_CPOL;
351 /* set the mlsbx and mlsbtx */
352 if (spi->mode & SPI_LSB_FIRST) {
353 reg_val &= ~SPI_CMD_TXMSBF;
354 reg_val &= ~SPI_CMD_RXMSBF;
356 reg_val |= SPI_CMD_TXMSBF;
357 reg_val |= SPI_CMD_RXMSBF;
360 /* set the tx/rx endian */
361 #ifdef __LITTLE_ENDIAN
362 reg_val &= ~SPI_CMD_TX_ENDIAN;
363 reg_val &= ~SPI_CMD_RX_ENDIAN;
365 reg_val |= SPI_CMD_TX_ENDIAN;
366 reg_val |= SPI_CMD_RX_ENDIAN;
369 if (mdata->dev_comp->enhance_timing) {
370 /* set CS polarity */
371 if (spi->mode & SPI_CS_HIGH)
372 reg_val |= SPI_CMD_CS_POL;
374 reg_val &= ~SPI_CMD_CS_POL;
376 if (chip_config->sample_sel)
377 reg_val |= SPI_CMD_SAMPLE_SEL;
379 reg_val &= ~SPI_CMD_SAMPLE_SEL;
382 /* set finish and pause interrupt always enable */
383 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
385 /* disable dma mode */
386 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
388 /* disable deassert mode */
389 reg_val &= ~SPI_CMD_DEASSERT;
391 writel(reg_val, mdata->base + SPI_CMD_REG);
394 if (mdata->dev_comp->need_pad_sel)
395 writel(mdata->pad_sel[spi->chip_select],
396 mdata->base + SPI_PAD_SEL_REG);
399 if (mdata->dev_comp->enhance_timing) {
400 if (mdata->dev_comp->ipm_design) {
401 reg_val = readl(mdata->base + SPI_CMD_REG);
402 reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
403 reg_val |= ((chip_config->tick_delay & 0x7)
404 << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
405 writel(reg_val, mdata->base + SPI_CMD_REG);
407 reg_val = readl(mdata->base + SPI_CFG1_REG);
408 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
409 reg_val |= ((chip_config->tick_delay & 0x7)
410 << SPI_CFG1_GET_TICK_DLY_OFFSET);
411 writel(reg_val, mdata->base + SPI_CFG1_REG);
414 reg_val = readl(mdata->base + SPI_CFG1_REG);
415 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
416 reg_val |= ((chip_config->tick_delay & 0x3)
417 << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
418 writel(reg_val, mdata->base + SPI_CFG1_REG);
421 /* set hw cs timing */
422 mtk_spi_set_hw_cs_timing(spi);
426 static int mtk_spi_prepare_message(struct spi_master *master,
427 struct spi_message *msg)
429 return mtk_spi_hw_init(master, msg->spi);
432 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
435 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
437 if (spi->mode & SPI_CS_HIGH)
440 reg_val = readl(mdata->base + SPI_CMD_REG);
442 reg_val |= SPI_CMD_PAUSE_EN;
443 writel(reg_val, mdata->base + SPI_CMD_REG);
445 reg_val &= ~SPI_CMD_PAUSE_EN;
446 writel(reg_val, mdata->base + SPI_CMD_REG);
447 mdata->state = MTK_SPI_IDLE;
448 mtk_spi_reset(mdata);
452 static void mtk_spi_prepare_transfer(struct spi_master *master,
455 u32 div, sck_time, reg_val;
456 struct mtk_spi *mdata = spi_master_get_devdata(master);
458 if (speed_hz < mdata->spi_clk_hz / 2)
459 div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
463 sck_time = (div + 1) / 2;
465 if (mdata->dev_comp->enhance_timing) {
466 reg_val = readl(mdata->base + SPI_CFG2_REG);
467 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
468 reg_val |= (((sck_time - 1) & 0xffff)
469 << SPI_CFG2_SCK_HIGH_OFFSET);
470 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
471 reg_val |= (((sck_time - 1) & 0xffff)
472 << SPI_CFG2_SCK_LOW_OFFSET);
473 writel(reg_val, mdata->base + SPI_CFG2_REG);
475 reg_val = readl(mdata->base + SPI_CFG0_REG);
476 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
477 reg_val |= (((sck_time - 1) & 0xff)
478 << SPI_CFG0_SCK_HIGH_OFFSET);
479 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
480 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
481 writel(reg_val, mdata->base + SPI_CFG0_REG);
485 static void mtk_spi_setup_packet(struct spi_master *master)
487 u32 packet_size, packet_loop, reg_val;
488 struct mtk_spi *mdata = spi_master_get_devdata(master);
490 if (mdata->dev_comp->ipm_design)
491 packet_size = min_t(u32,
493 MTK_SPI_IPM_PACKET_SIZE);
495 packet_size = min_t(u32,
497 MTK_SPI_PACKET_SIZE);
499 packet_loop = mdata->xfer_len / packet_size;
501 reg_val = readl(mdata->base + SPI_CFG1_REG);
502 if (mdata->dev_comp->ipm_design)
503 reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
505 reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
506 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
507 reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
508 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
509 writel(reg_val, mdata->base + SPI_CFG1_REG);
512 static void mtk_spi_enable_transfer(struct spi_master *master)
515 struct mtk_spi *mdata = spi_master_get_devdata(master);
517 cmd = readl(mdata->base + SPI_CMD_REG);
518 if (mdata->state == MTK_SPI_IDLE)
521 cmd |= SPI_CMD_RESUME;
522 writel(cmd, mdata->base + SPI_CMD_REG);
525 static int mtk_spi_get_mult_delta(u32 xfer_len)
529 if (xfer_len > MTK_SPI_PACKET_SIZE)
530 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
537 static void mtk_spi_update_mdata_len(struct spi_master *master)
540 struct mtk_spi *mdata = spi_master_get_devdata(master);
542 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
543 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
544 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
545 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
546 mdata->rx_sgl_len = mult_delta;
547 mdata->tx_sgl_len -= mdata->xfer_len;
549 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
550 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
551 mdata->tx_sgl_len = mult_delta;
552 mdata->rx_sgl_len -= mdata->xfer_len;
554 } else if (mdata->tx_sgl_len) {
555 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
556 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
557 mdata->tx_sgl_len = mult_delta;
558 } else if (mdata->rx_sgl_len) {
559 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
560 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
561 mdata->rx_sgl_len = mult_delta;
565 static void mtk_spi_setup_dma_addr(struct spi_master *master,
566 struct spi_transfer *xfer)
568 struct mtk_spi *mdata = spi_master_get_devdata(master);
571 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
572 mdata->base + SPI_TX_SRC_REG);
573 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
574 if (mdata->dev_comp->dma_ext)
575 writel((u32)(xfer->tx_dma >> 32),
576 mdata->base + SPI_TX_SRC_REG_64);
581 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
582 mdata->base + SPI_RX_DST_REG);
583 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
584 if (mdata->dev_comp->dma_ext)
585 writel((u32)(xfer->rx_dma >> 32),
586 mdata->base + SPI_RX_DST_REG_64);
591 static int mtk_spi_fifo_transfer(struct spi_master *master,
592 struct spi_device *spi,
593 struct spi_transfer *xfer)
597 struct mtk_spi *mdata = spi_master_get_devdata(master);
599 mdata->cur_transfer = xfer;
600 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
601 mdata->num_xfered = 0;
602 mtk_spi_prepare_transfer(master, xfer->speed_hz);
603 mtk_spi_setup_packet(master);
607 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
608 remainder = xfer->len % 4;
611 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
612 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
616 mtk_spi_enable_transfer(master);
621 static int mtk_spi_dma_transfer(struct spi_master *master,
622 struct spi_device *spi,
623 struct spi_transfer *xfer)
626 struct mtk_spi *mdata = spi_master_get_devdata(master);
628 mdata->tx_sgl = NULL;
629 mdata->rx_sgl = NULL;
630 mdata->tx_sgl_len = 0;
631 mdata->rx_sgl_len = 0;
632 mdata->cur_transfer = xfer;
633 mdata->num_xfered = 0;
635 mtk_spi_prepare_transfer(master, xfer->speed_hz);
637 cmd = readl(mdata->base + SPI_CMD_REG);
639 cmd |= SPI_CMD_TX_DMA;
641 cmd |= SPI_CMD_RX_DMA;
642 writel(cmd, mdata->base + SPI_CMD_REG);
645 mdata->tx_sgl = xfer->tx_sg.sgl;
647 mdata->rx_sgl = xfer->rx_sg.sgl;
650 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
651 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
654 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
655 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
658 mtk_spi_update_mdata_len(master);
659 mtk_spi_setup_packet(master);
660 mtk_spi_setup_dma_addr(master, xfer);
661 mtk_spi_enable_transfer(master);
666 static int mtk_spi_transfer_one(struct spi_master *master,
667 struct spi_device *spi,
668 struct spi_transfer *xfer)
670 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
673 /* prepare xfer direction and duplex mode */
674 if (mdata->dev_comp->ipm_design) {
675 if (!xfer->tx_buf || !xfer->rx_buf) {
676 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
678 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
680 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
683 if (master->can_dma(master, spi, xfer))
684 return mtk_spi_dma_transfer(master, spi, xfer);
686 return mtk_spi_fifo_transfer(master, spi, xfer);
689 static bool mtk_spi_can_dma(struct spi_master *master,
690 struct spi_device *spi,
691 struct spi_transfer *xfer)
693 /* Buffers for DMA transactions must be 4-byte aligned */
694 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
695 (unsigned long)xfer->tx_buf % 4 == 0 &&
696 (unsigned long)xfer->rx_buf % 4 == 0);
699 static int mtk_spi_setup(struct spi_device *spi)
701 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
703 if (!spi->controller_data)
704 spi->controller_data = (void *)&mtk_default_chip_info;
706 if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
707 /* CS de-asserted, gpiolib will handle inversion */
708 gpiod_direction_output(spi->cs_gpiod, 0);
713 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
715 u32 cmd, reg_val, cnt, remainder, len;
716 struct spi_master *master = dev_id;
717 struct mtk_spi *mdata = spi_master_get_devdata(master);
718 struct spi_transfer *trans = mdata->cur_transfer;
720 reg_val = readl(mdata->base + SPI_STATUS0_REG);
721 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
722 mdata->state = MTK_SPI_PAUSED;
724 mdata->state = MTK_SPI_IDLE;
727 if (mdata->use_spimem) {
728 complete(&mdata->spimem_done);
732 if (!master->can_dma(master, NULL, trans)) {
734 cnt = mdata->xfer_len / 4;
735 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
736 trans->rx_buf + mdata->num_xfered, cnt);
737 remainder = mdata->xfer_len % 4;
739 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
740 memcpy(trans->rx_buf +
748 mdata->num_xfered += mdata->xfer_len;
749 if (mdata->num_xfered == trans->len) {
750 spi_finalize_current_transfer(master);
754 len = trans->len - mdata->num_xfered;
755 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
756 mtk_spi_setup_packet(master);
758 cnt = mdata->xfer_len / 4;
759 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
760 trans->tx_buf + mdata->num_xfered, cnt);
762 remainder = mdata->xfer_len % 4;
766 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
768 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
771 mtk_spi_enable_transfer(master);
777 trans->tx_dma += mdata->xfer_len;
779 trans->rx_dma += mdata->xfer_len;
781 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
782 mdata->tx_sgl = sg_next(mdata->tx_sgl);
784 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
785 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
788 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
789 mdata->rx_sgl = sg_next(mdata->rx_sgl);
791 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
792 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
796 if (!mdata->tx_sgl && !mdata->rx_sgl) {
797 /* spi disable dma */
798 cmd = readl(mdata->base + SPI_CMD_REG);
799 cmd &= ~SPI_CMD_TX_DMA;
800 cmd &= ~SPI_CMD_RX_DMA;
801 writel(cmd, mdata->base + SPI_CMD_REG);
803 spi_finalize_current_transfer(master);
807 mtk_spi_update_mdata_len(master);
808 mtk_spi_setup_packet(master);
809 mtk_spi_setup_dma_addr(master, trans);
810 mtk_spi_enable_transfer(master);
815 static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
816 struct spi_mem_op *op)
820 if (op->data.dir != SPI_MEM_NO_DATA) {
821 opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
822 if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
823 op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len;
824 /* force data buffer dma-aligned. */
825 op->data.nbytes -= op->data.nbytes % 4;
832 static bool mtk_spi_mem_supports_op(struct spi_mem *mem,
833 const struct spi_mem_op *op)
835 if (!spi_mem_default_supports_op(mem, op))
838 if (op->addr.nbytes && op->dummy.nbytes &&
839 op->addr.buswidth != op->dummy.buswidth)
842 if (op->addr.nbytes + op->dummy.nbytes > 16)
845 if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
846 if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE >
847 MTK_SPI_IPM_PACKET_LOOP ||
848 op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0)
855 static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master,
856 const struct spi_mem_op *op)
858 struct mtk_spi *mdata = spi_master_get_devdata(master);
860 writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK),
861 mdata->base + SPI_TX_SRC_REG);
862 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
863 if (mdata->dev_comp->dma_ext)
864 writel((u32)(mdata->tx_dma >> 32),
865 mdata->base + SPI_TX_SRC_REG_64);
868 if (op->data.dir == SPI_MEM_DATA_IN) {
869 writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK),
870 mdata->base + SPI_RX_DST_REG);
871 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
872 if (mdata->dev_comp->dma_ext)
873 writel((u32)(mdata->rx_dma >> 32),
874 mdata->base + SPI_RX_DST_REG_64);
879 static int mtk_spi_transfer_wait(struct spi_mem *mem,
880 const struct spi_mem_op *op)
882 struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
884 * For each byte we wait for 8 cycles of the SPI clock.
885 * Since speed is defined in Hz and we want milliseconds,
886 * so it should be 8 * 1000.
890 if (op->data.dir == SPI_MEM_NO_DATA)
891 ms *= 32; /* prevent we may get 0 for short transfers. */
893 ms *= op->data.nbytes;
894 ms = div_u64(ms, mem->spi->max_speed_hz);
895 ms += ms + 1000; /* 1s tolerance */
900 if (!wait_for_completion_timeout(&mdata->spimem_done,
901 msecs_to_jiffies(ms))) {
902 dev_err(mdata->dev, "spi-mem transfer timeout\n");
909 static int mtk_spi_mem_exec_op(struct spi_mem *mem,
910 const struct spi_mem_op *op)
912 struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
913 u32 reg_val, nio, tx_size;
914 char *tx_tmp_buf, *rx_tmp_buf;
917 mdata->use_spimem = true;
918 reinit_completion(&mdata->spimem_done);
920 mtk_spi_reset(mdata);
921 mtk_spi_hw_init(mem->spi->master, mem->spi);
922 mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz);
924 reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
925 /* opcode byte len */
926 reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
927 reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
929 /* addr & dummy byte len */
930 reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
931 if (op->addr.nbytes || op->dummy.nbytes)
932 reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
933 SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET;
936 if (op->data.dir == SPI_MEM_NO_DATA) {
937 reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
938 writel(0, mdata->base + SPI_CFG1_REG);
940 reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
941 mdata->xfer_len = op->data.nbytes;
942 mtk_spi_setup_packet(mem->spi->master);
945 if (op->addr.nbytes || op->dummy.nbytes) {
946 if (op->addr.buswidth == 1 || op->dummy.buswidth == 1)
947 reg_val |= SPI_CFG3_IPM_XMODE_EN;
949 reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
952 if (op->addr.buswidth == 2 ||
953 op->dummy.buswidth == 2 ||
954 op->data.buswidth == 2)
956 else if (op->addr.buswidth == 4 ||
957 op->dummy.buswidth == 4 ||
958 op->data.buswidth == 4)
963 reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
964 reg_val |= PIN_MODE_CFG(nio);
966 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
967 if (op->data.dir == SPI_MEM_DATA_IN)
968 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
970 reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
971 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
973 tx_size = 1 + op->addr.nbytes + op->dummy.nbytes;
974 if (op->data.dir == SPI_MEM_DATA_OUT)
975 tx_size += op->data.nbytes;
977 tx_size = max_t(u32, tx_size, 32);
979 tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA);
981 mdata->use_spimem = false;
985 tx_tmp_buf[0] = op->cmd.opcode;
987 if (op->addr.nbytes) {
990 for (i = 0; i < op->addr.nbytes; i++)
991 tx_tmp_buf[i + 1] = op->addr.val >>
992 (8 * (op->addr.nbytes - i - 1));
995 if (op->dummy.nbytes)
996 memset(tx_tmp_buf + op->addr.nbytes + 1,
1000 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
1001 memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1,
1005 mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf,
1006 tx_size, DMA_TO_DEVICE);
1007 if (dma_mapping_error(mdata->dev, mdata->tx_dma)) {
1012 if (op->data.dir == SPI_MEM_DATA_IN) {
1013 if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
1014 rx_tmp_buf = kzalloc(op->data.nbytes,
1015 GFP_KERNEL | GFP_DMA);
1021 rx_tmp_buf = op->data.buf.in;
1024 mdata->rx_dma = dma_map_single(mdata->dev,
1028 if (dma_mapping_error(mdata->dev, mdata->rx_dma)) {
1030 goto kfree_rx_tmp_buf;
1034 reg_val = readl(mdata->base + SPI_CMD_REG);
1035 reg_val |= SPI_CMD_TX_DMA;
1036 if (op->data.dir == SPI_MEM_DATA_IN)
1037 reg_val |= SPI_CMD_RX_DMA;
1038 writel(reg_val, mdata->base + SPI_CMD_REG);
1040 mtk_spi_mem_setup_dma_xfer(mem->spi->master, op);
1042 mtk_spi_enable_transfer(mem->spi->master);
1044 /* Wait for the interrupt. */
1045 ret = mtk_spi_transfer_wait(mem, op);
1049 /* spi disable dma */
1050 reg_val = readl(mdata->base + SPI_CMD_REG);
1051 reg_val &= ~SPI_CMD_TX_DMA;
1052 if (op->data.dir == SPI_MEM_DATA_IN)
1053 reg_val &= ~SPI_CMD_RX_DMA;
1054 writel(reg_val, mdata->base + SPI_CMD_REG);
1057 if (op->data.dir == SPI_MEM_DATA_IN) {
1058 dma_unmap_single(mdata->dev, mdata->rx_dma,
1059 op->data.nbytes, DMA_FROM_DEVICE);
1060 if (!IS_ALIGNED((size_t)op->data.buf.in, 4))
1061 memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
1064 if (op->data.dir == SPI_MEM_DATA_IN &&
1065 !IS_ALIGNED((size_t)op->data.buf.in, 4))
1068 dma_unmap_single(mdata->dev, mdata->tx_dma,
1069 tx_size, DMA_TO_DEVICE);
1072 mdata->use_spimem = false;
1077 static const struct spi_controller_mem_ops mtk_spi_mem_ops = {
1078 .adjust_op_size = mtk_spi_mem_adjust_op_size,
1079 .supports_op = mtk_spi_mem_supports_op,
1080 .exec_op = mtk_spi_mem_exec_op,
1083 static int mtk_spi_probe(struct platform_device *pdev)
1085 struct spi_master *master;
1086 struct mtk_spi *mdata;
1087 const struct of_device_id *of_id;
1088 int i, irq, ret, addr_bits;
1090 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
1092 dev_err(&pdev->dev, "failed to alloc spi master\n");
1096 master->auto_runtime_pm = true;
1097 master->dev.of_node = pdev->dev.of_node;
1098 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1100 master->set_cs = mtk_spi_set_cs;
1101 master->prepare_message = mtk_spi_prepare_message;
1102 master->transfer_one = mtk_spi_transfer_one;
1103 master->can_dma = mtk_spi_can_dma;
1104 master->setup = mtk_spi_setup;
1105 master->set_cs_timing = mtk_spi_set_hw_cs_timing;
1106 master->use_gpio_descriptors = true;
1108 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
1110 dev_err(&pdev->dev, "failed to probe of_node\n");
1112 goto err_put_master;
1115 mdata = spi_master_get_devdata(master);
1116 mdata->dev_comp = of_id->data;
1118 if (mdata->dev_comp->enhance_timing)
1119 master->mode_bits |= SPI_CS_HIGH;
1121 if (mdata->dev_comp->must_tx)
1122 master->flags = SPI_MASTER_MUST_TX;
1123 if (mdata->dev_comp->ipm_design)
1124 master->mode_bits |= SPI_LOOP;
1126 if (mdata->dev_comp->ipm_design) {
1127 mdata->dev = &pdev->dev;
1128 master->mem_ops = &mtk_spi_mem_ops;
1129 init_completion(&mdata->spimem_done);
1132 if (mdata->dev_comp->need_pad_sel) {
1133 mdata->pad_num = of_property_count_u32_elems(
1135 "mediatek,pad-select");
1136 if (mdata->pad_num < 0) {
1138 "No 'mediatek,pad-select' property\n");
1140 goto err_put_master;
1143 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
1144 sizeof(u32), GFP_KERNEL);
1145 if (!mdata->pad_sel) {
1147 goto err_put_master;
1150 for (i = 0; i < mdata->pad_num; i++) {
1151 of_property_read_u32_index(pdev->dev.of_node,
1152 "mediatek,pad-select",
1153 i, &mdata->pad_sel[i]);
1154 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
1155 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
1156 i, mdata->pad_sel[i]);
1158 goto err_put_master;
1163 platform_set_drvdata(pdev, master);
1164 mdata->base = devm_platform_ioremap_resource(pdev, 0);
1165 if (IS_ERR(mdata->base)) {
1166 ret = PTR_ERR(mdata->base);
1167 goto err_put_master;
1170 irq = platform_get_irq(pdev, 0);
1173 goto err_put_master;
1176 if (!pdev->dev.dma_mask)
1177 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
1179 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
1180 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
1182 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
1183 goto err_put_master;
1186 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
1187 if (IS_ERR(mdata->parent_clk)) {
1188 ret = PTR_ERR(mdata->parent_clk);
1189 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
1190 goto err_put_master;
1193 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
1194 if (IS_ERR(mdata->sel_clk)) {
1195 ret = PTR_ERR(mdata->sel_clk);
1196 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
1197 goto err_put_master;
1200 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
1201 if (IS_ERR(mdata->spi_clk)) {
1202 ret = PTR_ERR(mdata->spi_clk);
1203 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
1204 goto err_put_master;
1207 mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk");
1208 if (IS_ERR(mdata->spi_hclk)) {
1209 ret = PTR_ERR(mdata->spi_hclk);
1210 dev_err(&pdev->dev, "failed to get hclk: %d\n", ret);
1211 goto err_put_master;
1214 ret = clk_prepare_enable(mdata->spi_hclk);
1216 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret);
1217 goto err_put_master;
1220 ret = clk_prepare_enable(mdata->spi_clk);
1222 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
1223 goto err_disable_spi_hclk;
1226 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
1228 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
1229 goto err_disable_spi_clk;
1232 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
1234 if (mdata->dev_comp->no_need_unprepare) {
1235 clk_disable(mdata->spi_clk);
1236 clk_disable(mdata->spi_hclk);
1238 clk_disable_unprepare(mdata->spi_clk);
1239 clk_disable_unprepare(mdata->spi_hclk);
1242 pm_runtime_enable(&pdev->dev);
1244 if (mdata->dev_comp->need_pad_sel) {
1245 if (mdata->pad_num != master->num_chipselect) {
1247 "pad_num does not match num_chipselect(%d != %d)\n",
1248 mdata->pad_num, master->num_chipselect);
1250 goto err_disable_runtime_pm;
1253 if (!master->cs_gpiods && master->num_chipselect > 1) {
1255 "cs_gpios not specified and num_chipselect > 1\n");
1257 goto err_disable_runtime_pm;
1261 if (mdata->dev_comp->dma_ext)
1262 addr_bits = DMA_ADDR_EXT_BITS;
1264 addr_bits = DMA_ADDR_DEF_BITS;
1265 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
1267 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
1270 ret = devm_spi_register_master(&pdev->dev, master);
1272 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
1273 goto err_disable_runtime_pm;
1278 err_disable_runtime_pm:
1279 pm_runtime_disable(&pdev->dev);
1280 err_disable_spi_clk:
1281 clk_disable_unprepare(mdata->spi_clk);
1282 err_disable_spi_hclk:
1283 clk_disable_unprepare(mdata->spi_hclk);
1285 spi_master_put(master);
1290 static int mtk_spi_remove(struct platform_device *pdev)
1292 struct spi_master *master = platform_get_drvdata(pdev);
1293 struct mtk_spi *mdata = spi_master_get_devdata(master);
1295 pm_runtime_disable(&pdev->dev);
1297 mtk_spi_reset(mdata);
1299 if (mdata->dev_comp->no_need_unprepare) {
1300 clk_unprepare(mdata->spi_clk);
1301 clk_unprepare(mdata->spi_hclk);
1307 #ifdef CONFIG_PM_SLEEP
1308 static int mtk_spi_suspend(struct device *dev)
1311 struct spi_master *master = dev_get_drvdata(dev);
1312 struct mtk_spi *mdata = spi_master_get_devdata(master);
1314 ret = spi_master_suspend(master);
1318 if (!pm_runtime_suspended(dev)) {
1319 clk_disable_unprepare(mdata->spi_clk);
1320 clk_disable_unprepare(mdata->spi_hclk);
1326 static int mtk_spi_resume(struct device *dev)
1329 struct spi_master *master = dev_get_drvdata(dev);
1330 struct mtk_spi *mdata = spi_master_get_devdata(master);
1332 if (!pm_runtime_suspended(dev)) {
1333 ret = clk_prepare_enable(mdata->spi_clk);
1335 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
1339 ret = clk_prepare_enable(mdata->spi_hclk);
1341 dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
1342 clk_disable_unprepare(mdata->spi_clk);
1347 ret = spi_master_resume(master);
1349 clk_disable_unprepare(mdata->spi_clk);
1350 clk_disable_unprepare(mdata->spi_hclk);
1355 #endif /* CONFIG_PM_SLEEP */
1358 static int mtk_spi_runtime_suspend(struct device *dev)
1360 struct spi_master *master = dev_get_drvdata(dev);
1361 struct mtk_spi *mdata = spi_master_get_devdata(master);
1363 if (mdata->dev_comp->no_need_unprepare) {
1364 clk_disable(mdata->spi_clk);
1365 clk_disable(mdata->spi_hclk);
1367 clk_disable_unprepare(mdata->spi_clk);
1368 clk_disable_unprepare(mdata->spi_hclk);
1374 static int mtk_spi_runtime_resume(struct device *dev)
1376 struct spi_master *master = dev_get_drvdata(dev);
1377 struct mtk_spi *mdata = spi_master_get_devdata(master);
1380 if (mdata->dev_comp->no_need_unprepare) {
1381 ret = clk_enable(mdata->spi_clk);
1383 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
1386 ret = clk_enable(mdata->spi_hclk);
1388 dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
1389 clk_disable(mdata->spi_clk);
1393 ret = clk_prepare_enable(mdata->spi_clk);
1395 dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret);
1399 ret = clk_prepare_enable(mdata->spi_hclk);
1401 dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret);
1402 clk_disable_unprepare(mdata->spi_clk);
1409 #endif /* CONFIG_PM */
1411 static const struct dev_pm_ops mtk_spi_pm = {
1412 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
1413 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
1414 mtk_spi_runtime_resume, NULL)
1417 static struct platform_driver mtk_spi_driver = {
1421 .of_match_table = mtk_spi_of_match,
1423 .probe = mtk_spi_probe,
1424 .remove = mtk_spi_remove,
1427 module_platform_driver(mtk_spi_driver);
1429 MODULE_DESCRIPTION("MTK SPI Controller driver");
1430 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
1431 MODULE_LICENSE("GPL v2");
1432 MODULE_ALIAS("platform:mtk-spi");