1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
22 #define SPI_CFG0_REG 0x0000
23 #define SPI_CFG1_REG 0x0004
24 #define SPI_TX_SRC_REG 0x0008
25 #define SPI_RX_DST_REG 0x000c
26 #define SPI_TX_DATA_REG 0x0010
27 #define SPI_RX_DATA_REG 0x0014
28 #define SPI_CMD_REG 0x0018
29 #define SPI_STATUS0_REG 0x001c
30 #define SPI_PAD_SEL_REG 0x0024
31 #define SPI_CFG2_REG 0x0028
32 #define SPI_TX_SRC_REG_64 0x002c
33 #define SPI_RX_DST_REG_64 0x0030
34 #define SPI_CFG3_IPM_REG 0x0040
36 #define SPI_CFG0_SCK_HIGH_OFFSET 0
37 #define SPI_CFG0_SCK_LOW_OFFSET 8
38 #define SPI_CFG0_CS_HOLD_OFFSET 16
39 #define SPI_CFG0_CS_SETUP_OFFSET 24
40 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
41 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
43 #define SPI_CFG1_CS_IDLE_OFFSET 0
44 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
45 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
46 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29
47 #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30
49 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
50 #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000
52 #define SPI_CFG1_CS_IDLE_MASK 0xff
53 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
54 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
55 #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
56 #define SPI_CFG2_SCK_HIGH_OFFSET 0
57 #define SPI_CFG2_SCK_LOW_OFFSET 16
59 #define SPI_CMD_ACT BIT(0)
60 #define SPI_CMD_RESUME BIT(1)
61 #define SPI_CMD_RST BIT(2)
62 #define SPI_CMD_PAUSE_EN BIT(4)
63 #define SPI_CMD_DEASSERT BIT(5)
64 #define SPI_CMD_SAMPLE_SEL BIT(6)
65 #define SPI_CMD_CS_POL BIT(7)
66 #define SPI_CMD_CPHA BIT(8)
67 #define SPI_CMD_CPOL BIT(9)
68 #define SPI_CMD_RX_DMA BIT(10)
69 #define SPI_CMD_TX_DMA BIT(11)
70 #define SPI_CMD_TXMSBF BIT(12)
71 #define SPI_CMD_RXMSBF BIT(13)
72 #define SPI_CMD_RX_ENDIAN BIT(14)
73 #define SPI_CMD_TX_ENDIAN BIT(15)
74 #define SPI_CMD_FINISH_IE BIT(16)
75 #define SPI_CMD_PAUSE_IE BIT(17)
76 #define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
77 #define SPI_CMD_IPM_SPIM_LOOP BIT(21)
78 #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
80 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)
81 #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
82 #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
83 #define MT8173_SPI_MAX_PAD_SEL 3
85 #define MTK_SPI_PAUSE_INT_STATUS 0x2
87 #define MTK_SPI_IDLE 0
88 #define MTK_SPI_PAUSED 1
90 #define MTK_SPI_MAX_FIFO_SIZE 32U
91 #define MTK_SPI_PACKET_SIZE 1024
92 #define MTK_SPI_IPM_PACKET_SIZE SZ_64K
93 #define MTK_SPI_32BITS_MASK (0xffffffff)
95 #define DMA_ADDR_EXT_BITS (36)
96 #define DMA_ADDR_DEF_BITS (32)
98 struct mtk_spi_compatible {
100 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
102 /* some IC design adjust cfg register to enhance time accuracy */
104 /* some IC support DMA addr extension */
106 /* some IC no need unprepare SPI clk */
107 bool no_need_unprepare;
108 /* IPM design adjust and extend register to support more features */
118 struct clk *parent_clk, *sel_clk, *spi_clk;
119 struct spi_transfer *cur_transfer;
122 struct scatterlist *tx_sgl, *rx_sgl;
123 u32 tx_sgl_len, rx_sgl_len;
124 const struct mtk_spi_compatible *dev_comp;
128 static const struct mtk_spi_compatible mtk_common_compat;
130 static const struct mtk_spi_compatible mt2712_compat = {
134 static const struct mtk_spi_compatible mtk_ipm_compat = {
135 .enhance_timing = true,
140 static const struct mtk_spi_compatible mt6765_compat = {
141 .need_pad_sel = true,
143 .enhance_timing = true,
147 static const struct mtk_spi_compatible mt7622_compat = {
149 .enhance_timing = true,
152 static const struct mtk_spi_compatible mt8173_compat = {
153 .need_pad_sel = true,
157 static const struct mtk_spi_compatible mt8183_compat = {
158 .need_pad_sel = true,
160 .enhance_timing = true,
163 static const struct mtk_spi_compatible mt6893_compat = {
164 .need_pad_sel = true,
166 .enhance_timing = true,
168 .no_need_unprepare = true,
172 * A piece of default chip info unless the platform
175 static const struct mtk_chip_config mtk_default_chip_info = {
180 static const struct of_device_id mtk_spi_of_match[] = {
181 { .compatible = "mediatek,spi-ipm",
182 .data = (void *)&mtk_ipm_compat,
184 { .compatible = "mediatek,mt2701-spi",
185 .data = (void *)&mtk_common_compat,
187 { .compatible = "mediatek,mt2712-spi",
188 .data = (void *)&mt2712_compat,
190 { .compatible = "mediatek,mt6589-spi",
191 .data = (void *)&mtk_common_compat,
193 { .compatible = "mediatek,mt6765-spi",
194 .data = (void *)&mt6765_compat,
196 { .compatible = "mediatek,mt7622-spi",
197 .data = (void *)&mt7622_compat,
199 { .compatible = "mediatek,mt7629-spi",
200 .data = (void *)&mt7622_compat,
202 { .compatible = "mediatek,mt8135-spi",
203 .data = (void *)&mtk_common_compat,
205 { .compatible = "mediatek,mt8173-spi",
206 .data = (void *)&mt8173_compat,
208 { .compatible = "mediatek,mt8183-spi",
209 .data = (void *)&mt8183_compat,
211 { .compatible = "mediatek,mt8192-spi",
212 .data = (void *)&mt6765_compat,
214 { .compatible = "mediatek,mt6893-spi",
215 .data = (void *)&mt6893_compat,
219 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
221 static void mtk_spi_reset(struct mtk_spi *mdata)
225 /* set the software reset bit in SPI_CMD_REG. */
226 reg_val = readl(mdata->base + SPI_CMD_REG);
227 reg_val |= SPI_CMD_RST;
228 writel(reg_val, mdata->base + SPI_CMD_REG);
230 reg_val = readl(mdata->base + SPI_CMD_REG);
231 reg_val &= ~SPI_CMD_RST;
232 writel(reg_val, mdata->base + SPI_CMD_REG);
235 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
237 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
238 struct spi_delay *cs_setup = &spi->cs_setup;
239 struct spi_delay *cs_hold = &spi->cs_hold;
240 struct spi_delay *cs_inactive = &spi->cs_inactive;
241 u32 setup, hold, inactive;
245 delay = spi_delay_to_ns(cs_setup, NULL);
248 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
250 delay = spi_delay_to_ns(cs_hold, NULL);
253 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
255 delay = spi_delay_to_ns(cs_inactive, NULL);
258 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
261 reg_val = readl(mdata->base + SPI_CFG0_REG);
262 if (mdata->dev_comp->enhance_timing) {
264 hold = min_t(u32, hold, 0x10000);
265 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
266 reg_val |= (((hold - 1) & 0xffff)
267 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
270 setup = min_t(u32, setup, 0x10000);
271 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
272 reg_val |= (((setup - 1) & 0xffff)
273 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
277 hold = min_t(u32, hold, 0x100);
278 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
279 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
282 setup = min_t(u32, setup, 0x100);
283 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
284 reg_val |= (((setup - 1) & 0xff)
285 << SPI_CFG0_CS_SETUP_OFFSET);
288 writel(reg_val, mdata->base + SPI_CFG0_REG);
292 inactive = min_t(u32, inactive, 0x100);
293 reg_val = readl(mdata->base + SPI_CFG1_REG);
294 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
295 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
296 writel(reg_val, mdata->base + SPI_CFG1_REG);
302 static int mtk_spi_hw_init(struct spi_master *master,
303 struct spi_device *spi)
307 struct mtk_chip_config *chip_config = spi->controller_data;
308 struct mtk_spi *mdata = spi_master_get_devdata(master);
310 cpha = spi->mode & SPI_CPHA ? 1 : 0;
311 cpol = spi->mode & SPI_CPOL ? 1 : 0;
313 reg_val = readl(mdata->base + SPI_CMD_REG);
314 if (mdata->dev_comp->ipm_design) {
315 /* SPI transfer without idle time until packet length done */
316 reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
317 if (spi->mode & SPI_LOOP)
318 reg_val |= SPI_CMD_IPM_SPIM_LOOP;
320 reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
324 reg_val |= SPI_CMD_CPHA;
326 reg_val &= ~SPI_CMD_CPHA;
328 reg_val |= SPI_CMD_CPOL;
330 reg_val &= ~SPI_CMD_CPOL;
332 /* set the mlsbx and mlsbtx */
333 if (spi->mode & SPI_LSB_FIRST) {
334 reg_val &= ~SPI_CMD_TXMSBF;
335 reg_val &= ~SPI_CMD_RXMSBF;
337 reg_val |= SPI_CMD_TXMSBF;
338 reg_val |= SPI_CMD_RXMSBF;
341 /* set the tx/rx endian */
342 #ifdef __LITTLE_ENDIAN
343 reg_val &= ~SPI_CMD_TX_ENDIAN;
344 reg_val &= ~SPI_CMD_RX_ENDIAN;
346 reg_val |= SPI_CMD_TX_ENDIAN;
347 reg_val |= SPI_CMD_RX_ENDIAN;
350 if (mdata->dev_comp->enhance_timing) {
351 /* set CS polarity */
352 if (spi->mode & SPI_CS_HIGH)
353 reg_val |= SPI_CMD_CS_POL;
355 reg_val &= ~SPI_CMD_CS_POL;
357 if (chip_config->sample_sel)
358 reg_val |= SPI_CMD_SAMPLE_SEL;
360 reg_val &= ~SPI_CMD_SAMPLE_SEL;
363 /* set finish and pause interrupt always enable */
364 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
366 /* disable dma mode */
367 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
369 /* disable deassert mode */
370 reg_val &= ~SPI_CMD_DEASSERT;
372 writel(reg_val, mdata->base + SPI_CMD_REG);
375 if (mdata->dev_comp->need_pad_sel)
376 writel(mdata->pad_sel[spi->chip_select],
377 mdata->base + SPI_PAD_SEL_REG);
380 if (mdata->dev_comp->enhance_timing) {
381 if (mdata->dev_comp->ipm_design) {
382 reg_val = readl(mdata->base + SPI_CMD_REG);
383 reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
384 reg_val |= ((chip_config->tick_delay & 0x7)
385 << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
386 writel(reg_val, mdata->base + SPI_CMD_REG);
388 reg_val = readl(mdata->base + SPI_CFG1_REG);
389 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
390 reg_val |= ((chip_config->tick_delay & 0x7)
391 << SPI_CFG1_GET_TICK_DLY_OFFSET);
392 writel(reg_val, mdata->base + SPI_CFG1_REG);
395 reg_val = readl(mdata->base + SPI_CFG1_REG);
396 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
397 reg_val |= ((chip_config->tick_delay & 0x3)
398 << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
399 writel(reg_val, mdata->base + SPI_CFG1_REG);
402 /* set hw cs timing */
403 mtk_spi_set_hw_cs_timing(spi);
407 static int mtk_spi_prepare_message(struct spi_master *master,
408 struct spi_message *msg)
410 return mtk_spi_hw_init(master, msg->spi);
413 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
416 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
418 if (spi->mode & SPI_CS_HIGH)
421 reg_val = readl(mdata->base + SPI_CMD_REG);
423 reg_val |= SPI_CMD_PAUSE_EN;
424 writel(reg_val, mdata->base + SPI_CMD_REG);
426 reg_val &= ~SPI_CMD_PAUSE_EN;
427 writel(reg_val, mdata->base + SPI_CMD_REG);
428 mdata->state = MTK_SPI_IDLE;
429 mtk_spi_reset(mdata);
433 static void mtk_spi_prepare_transfer(struct spi_master *master,
436 u32 div, sck_time, reg_val;
437 struct mtk_spi *mdata = spi_master_get_devdata(master);
439 if (speed_hz < mdata->spi_clk_hz / 2)
440 div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
444 sck_time = (div + 1) / 2;
446 if (mdata->dev_comp->enhance_timing) {
447 reg_val = readl(mdata->base + SPI_CFG2_REG);
448 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
449 reg_val |= (((sck_time - 1) & 0xffff)
450 << SPI_CFG2_SCK_HIGH_OFFSET);
451 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
452 reg_val |= (((sck_time - 1) & 0xffff)
453 << SPI_CFG2_SCK_LOW_OFFSET);
454 writel(reg_val, mdata->base + SPI_CFG2_REG);
456 reg_val = readl(mdata->base + SPI_CFG0_REG);
457 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
458 reg_val |= (((sck_time - 1) & 0xff)
459 << SPI_CFG0_SCK_HIGH_OFFSET);
460 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
461 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
462 writel(reg_val, mdata->base + SPI_CFG0_REG);
466 static void mtk_spi_setup_packet(struct spi_master *master)
468 u32 packet_size, packet_loop, reg_val;
469 struct mtk_spi *mdata = spi_master_get_devdata(master);
471 if (mdata->dev_comp->ipm_design)
472 packet_size = min_t(u32,
474 MTK_SPI_IPM_PACKET_SIZE);
476 packet_size = min_t(u32,
478 MTK_SPI_PACKET_SIZE);
480 packet_loop = mdata->xfer_len / packet_size;
482 reg_val = readl(mdata->base + SPI_CFG1_REG);
483 if (mdata->dev_comp->ipm_design)
484 reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
486 reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
487 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
488 reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
489 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
490 writel(reg_val, mdata->base + SPI_CFG1_REG);
493 static void mtk_spi_enable_transfer(struct spi_master *master)
496 struct mtk_spi *mdata = spi_master_get_devdata(master);
498 cmd = readl(mdata->base + SPI_CMD_REG);
499 if (mdata->state == MTK_SPI_IDLE)
502 cmd |= SPI_CMD_RESUME;
503 writel(cmd, mdata->base + SPI_CMD_REG);
506 static int mtk_spi_get_mult_delta(u32 xfer_len)
510 if (xfer_len > MTK_SPI_PACKET_SIZE)
511 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
518 static void mtk_spi_update_mdata_len(struct spi_master *master)
521 struct mtk_spi *mdata = spi_master_get_devdata(master);
523 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
524 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
525 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
526 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
527 mdata->rx_sgl_len = mult_delta;
528 mdata->tx_sgl_len -= mdata->xfer_len;
530 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
531 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
532 mdata->tx_sgl_len = mult_delta;
533 mdata->rx_sgl_len -= mdata->xfer_len;
535 } else if (mdata->tx_sgl_len) {
536 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
537 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
538 mdata->tx_sgl_len = mult_delta;
539 } else if (mdata->rx_sgl_len) {
540 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
541 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
542 mdata->rx_sgl_len = mult_delta;
546 static void mtk_spi_setup_dma_addr(struct spi_master *master,
547 struct spi_transfer *xfer)
549 struct mtk_spi *mdata = spi_master_get_devdata(master);
552 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
553 mdata->base + SPI_TX_SRC_REG);
554 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
555 if (mdata->dev_comp->dma_ext)
556 writel((u32)(xfer->tx_dma >> 32),
557 mdata->base + SPI_TX_SRC_REG_64);
562 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
563 mdata->base + SPI_RX_DST_REG);
564 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
565 if (mdata->dev_comp->dma_ext)
566 writel((u32)(xfer->rx_dma >> 32),
567 mdata->base + SPI_RX_DST_REG_64);
572 static int mtk_spi_fifo_transfer(struct spi_master *master,
573 struct spi_device *spi,
574 struct spi_transfer *xfer)
578 struct mtk_spi *mdata = spi_master_get_devdata(master);
580 mdata->cur_transfer = xfer;
581 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
582 mdata->num_xfered = 0;
583 mtk_spi_prepare_transfer(master, xfer->speed_hz);
584 mtk_spi_setup_packet(master);
588 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
589 remainder = xfer->len % 4;
592 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
593 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
597 mtk_spi_enable_transfer(master);
602 static int mtk_spi_dma_transfer(struct spi_master *master,
603 struct spi_device *spi,
604 struct spi_transfer *xfer)
607 struct mtk_spi *mdata = spi_master_get_devdata(master);
609 mdata->tx_sgl = NULL;
610 mdata->rx_sgl = NULL;
611 mdata->tx_sgl_len = 0;
612 mdata->rx_sgl_len = 0;
613 mdata->cur_transfer = xfer;
614 mdata->num_xfered = 0;
616 mtk_spi_prepare_transfer(master, xfer->speed_hz);
618 cmd = readl(mdata->base + SPI_CMD_REG);
620 cmd |= SPI_CMD_TX_DMA;
622 cmd |= SPI_CMD_RX_DMA;
623 writel(cmd, mdata->base + SPI_CMD_REG);
626 mdata->tx_sgl = xfer->tx_sg.sgl;
628 mdata->rx_sgl = xfer->rx_sg.sgl;
631 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
632 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
635 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
636 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
639 mtk_spi_update_mdata_len(master);
640 mtk_spi_setup_packet(master);
641 mtk_spi_setup_dma_addr(master, xfer);
642 mtk_spi_enable_transfer(master);
647 static int mtk_spi_transfer_one(struct spi_master *master,
648 struct spi_device *spi,
649 struct spi_transfer *xfer)
651 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
654 /* prepare xfer direction and duplex mode */
655 if (mdata->dev_comp->ipm_design) {
656 if (!xfer->tx_buf || !xfer->rx_buf) {
657 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
659 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
661 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
664 if (master->can_dma(master, spi, xfer))
665 return mtk_spi_dma_transfer(master, spi, xfer);
667 return mtk_spi_fifo_transfer(master, spi, xfer);
670 static bool mtk_spi_can_dma(struct spi_master *master,
671 struct spi_device *spi,
672 struct spi_transfer *xfer)
674 /* Buffers for DMA transactions must be 4-byte aligned */
675 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
676 (unsigned long)xfer->tx_buf % 4 == 0 &&
677 (unsigned long)xfer->rx_buf % 4 == 0);
680 static int mtk_spi_setup(struct spi_device *spi)
682 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
684 if (!spi->controller_data)
685 spi->controller_data = (void *)&mtk_default_chip_info;
687 if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
688 /* CS de-asserted, gpiolib will handle inversion */
689 gpiod_direction_output(spi->cs_gpiod, 0);
694 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
696 u32 cmd, reg_val, cnt, remainder, len;
697 struct spi_master *master = dev_id;
698 struct mtk_spi *mdata = spi_master_get_devdata(master);
699 struct spi_transfer *trans = mdata->cur_transfer;
701 reg_val = readl(mdata->base + SPI_STATUS0_REG);
702 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
703 mdata->state = MTK_SPI_PAUSED;
705 mdata->state = MTK_SPI_IDLE;
707 if (!master->can_dma(master, NULL, trans)) {
709 cnt = mdata->xfer_len / 4;
710 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
711 trans->rx_buf + mdata->num_xfered, cnt);
712 remainder = mdata->xfer_len % 4;
714 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
715 memcpy(trans->rx_buf +
723 mdata->num_xfered += mdata->xfer_len;
724 if (mdata->num_xfered == trans->len) {
725 spi_finalize_current_transfer(master);
729 len = trans->len - mdata->num_xfered;
730 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
731 mtk_spi_setup_packet(master);
733 cnt = mdata->xfer_len / 4;
734 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
735 trans->tx_buf + mdata->num_xfered, cnt);
737 remainder = mdata->xfer_len % 4;
741 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
743 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
746 mtk_spi_enable_transfer(master);
752 trans->tx_dma += mdata->xfer_len;
754 trans->rx_dma += mdata->xfer_len;
756 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
757 mdata->tx_sgl = sg_next(mdata->tx_sgl);
759 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
760 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
763 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
764 mdata->rx_sgl = sg_next(mdata->rx_sgl);
766 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
767 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
771 if (!mdata->tx_sgl && !mdata->rx_sgl) {
772 /* spi disable dma */
773 cmd = readl(mdata->base + SPI_CMD_REG);
774 cmd &= ~SPI_CMD_TX_DMA;
775 cmd &= ~SPI_CMD_RX_DMA;
776 writel(cmd, mdata->base + SPI_CMD_REG);
778 spi_finalize_current_transfer(master);
782 mtk_spi_update_mdata_len(master);
783 mtk_spi_setup_packet(master);
784 mtk_spi_setup_dma_addr(master, trans);
785 mtk_spi_enable_transfer(master);
790 static int mtk_spi_probe(struct platform_device *pdev)
792 struct spi_master *master;
793 struct mtk_spi *mdata;
794 const struct of_device_id *of_id;
795 int i, irq, ret, addr_bits;
797 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
799 dev_err(&pdev->dev, "failed to alloc spi master\n");
803 master->auto_runtime_pm = true;
804 master->dev.of_node = pdev->dev.of_node;
805 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
807 master->set_cs = mtk_spi_set_cs;
808 master->prepare_message = mtk_spi_prepare_message;
809 master->transfer_one = mtk_spi_transfer_one;
810 master->can_dma = mtk_spi_can_dma;
811 master->setup = mtk_spi_setup;
812 master->set_cs_timing = mtk_spi_set_hw_cs_timing;
813 master->use_gpio_descriptors = true;
815 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
817 dev_err(&pdev->dev, "failed to probe of_node\n");
822 mdata = spi_master_get_devdata(master);
823 mdata->dev_comp = of_id->data;
825 if (mdata->dev_comp->enhance_timing)
826 master->mode_bits |= SPI_CS_HIGH;
828 if (mdata->dev_comp->must_tx)
829 master->flags = SPI_MASTER_MUST_TX;
830 if (mdata->dev_comp->ipm_design)
831 master->mode_bits |= SPI_LOOP;
833 if (mdata->dev_comp->need_pad_sel) {
834 mdata->pad_num = of_property_count_u32_elems(
836 "mediatek,pad-select");
837 if (mdata->pad_num < 0) {
839 "No 'mediatek,pad-select' property\n");
844 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
845 sizeof(u32), GFP_KERNEL);
846 if (!mdata->pad_sel) {
851 for (i = 0; i < mdata->pad_num; i++) {
852 of_property_read_u32_index(pdev->dev.of_node,
853 "mediatek,pad-select",
854 i, &mdata->pad_sel[i]);
855 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
856 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
857 i, mdata->pad_sel[i]);
864 platform_set_drvdata(pdev, master);
865 mdata->base = devm_platform_ioremap_resource(pdev, 0);
866 if (IS_ERR(mdata->base)) {
867 ret = PTR_ERR(mdata->base);
871 irq = platform_get_irq(pdev, 0);
877 if (!pdev->dev.dma_mask)
878 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
880 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
881 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
883 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
887 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
888 if (IS_ERR(mdata->parent_clk)) {
889 ret = PTR_ERR(mdata->parent_clk);
890 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
894 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
895 if (IS_ERR(mdata->sel_clk)) {
896 ret = PTR_ERR(mdata->sel_clk);
897 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
901 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
902 if (IS_ERR(mdata->spi_clk)) {
903 ret = PTR_ERR(mdata->spi_clk);
904 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
908 ret = clk_prepare_enable(mdata->spi_clk);
910 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
914 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
916 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
917 clk_disable_unprepare(mdata->spi_clk);
921 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
923 if (mdata->dev_comp->no_need_unprepare)
924 clk_disable(mdata->spi_clk);
926 clk_disable_unprepare(mdata->spi_clk);
928 pm_runtime_enable(&pdev->dev);
930 if (mdata->dev_comp->need_pad_sel) {
931 if (mdata->pad_num != master->num_chipselect) {
933 "pad_num does not match num_chipselect(%d != %d)\n",
934 mdata->pad_num, master->num_chipselect);
936 goto err_disable_runtime_pm;
939 if (!master->cs_gpiods && master->num_chipselect > 1) {
941 "cs_gpios not specified and num_chipselect > 1\n");
943 goto err_disable_runtime_pm;
947 if (mdata->dev_comp->dma_ext)
948 addr_bits = DMA_ADDR_EXT_BITS;
950 addr_bits = DMA_ADDR_DEF_BITS;
951 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
953 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
956 ret = devm_spi_register_master(&pdev->dev, master);
958 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
959 goto err_disable_runtime_pm;
964 err_disable_runtime_pm:
965 pm_runtime_disable(&pdev->dev);
967 spi_master_put(master);
972 static int mtk_spi_remove(struct platform_device *pdev)
974 struct spi_master *master = platform_get_drvdata(pdev);
975 struct mtk_spi *mdata = spi_master_get_devdata(master);
977 pm_runtime_disable(&pdev->dev);
979 mtk_spi_reset(mdata);
981 if (mdata->dev_comp->no_need_unprepare)
982 clk_unprepare(mdata->spi_clk);
987 #ifdef CONFIG_PM_SLEEP
988 static int mtk_spi_suspend(struct device *dev)
991 struct spi_master *master = dev_get_drvdata(dev);
992 struct mtk_spi *mdata = spi_master_get_devdata(master);
994 ret = spi_master_suspend(master);
998 if (!pm_runtime_suspended(dev))
999 clk_disable_unprepare(mdata->spi_clk);
1004 static int mtk_spi_resume(struct device *dev)
1007 struct spi_master *master = dev_get_drvdata(dev);
1008 struct mtk_spi *mdata = spi_master_get_devdata(master);
1010 if (!pm_runtime_suspended(dev)) {
1011 ret = clk_prepare_enable(mdata->spi_clk);
1013 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
1018 ret = spi_master_resume(master);
1020 clk_disable_unprepare(mdata->spi_clk);
1024 #endif /* CONFIG_PM_SLEEP */
1027 static int mtk_spi_runtime_suspend(struct device *dev)
1029 struct spi_master *master = dev_get_drvdata(dev);
1030 struct mtk_spi *mdata = spi_master_get_devdata(master);
1032 if (mdata->dev_comp->no_need_unprepare)
1033 clk_disable(mdata->spi_clk);
1035 clk_disable_unprepare(mdata->spi_clk);
1040 static int mtk_spi_runtime_resume(struct device *dev)
1042 struct spi_master *master = dev_get_drvdata(dev);
1043 struct mtk_spi *mdata = spi_master_get_devdata(master);
1046 if (mdata->dev_comp->no_need_unprepare)
1047 ret = clk_enable(mdata->spi_clk);
1049 ret = clk_prepare_enable(mdata->spi_clk);
1051 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
1057 #endif /* CONFIG_PM */
1059 static const struct dev_pm_ops mtk_spi_pm = {
1060 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
1061 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
1062 mtk_spi_runtime_resume, NULL)
1065 static struct platform_driver mtk_spi_driver = {
1069 .of_match_table = mtk_spi_of_match,
1071 .probe = mtk_spi_probe,
1072 .remove = mtk_spi_remove,
1075 module_platform_driver(mtk_spi_driver);
1077 MODULE_DESCRIPTION("MTK SPI Controller driver");
1078 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
1079 MODULE_LICENSE("GPL v2");
1080 MODULE_ALIAS("platform:mtk-spi");