1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/of_gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
22 #define SPI_CFG0_REG 0x0000
23 #define SPI_CFG1_REG 0x0004
24 #define SPI_TX_SRC_REG 0x0008
25 #define SPI_RX_DST_REG 0x000c
26 #define SPI_TX_DATA_REG 0x0010
27 #define SPI_RX_DATA_REG 0x0014
28 #define SPI_CMD_REG 0x0018
29 #define SPI_STATUS0_REG 0x001c
30 #define SPI_PAD_SEL_REG 0x0024
31 #define SPI_CFG2_REG 0x0028
32 #define SPI_TX_SRC_REG_64 0x002c
33 #define SPI_RX_DST_REG_64 0x0030
35 #define SPI_CFG0_SCK_HIGH_OFFSET 0
36 #define SPI_CFG0_SCK_LOW_OFFSET 8
37 #define SPI_CFG0_CS_HOLD_OFFSET 16
38 #define SPI_CFG0_CS_SETUP_OFFSET 24
39 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
40 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
42 #define SPI_CFG1_CS_IDLE_OFFSET 0
43 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
44 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
45 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29
47 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
48 #define SPI_CFG1_CS_IDLE_MASK 0xff
49 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
50 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
51 #define SPI_CFG2_SCK_HIGH_OFFSET 0
52 #define SPI_CFG2_SCK_LOW_OFFSET 16
54 #define SPI_CMD_ACT BIT(0)
55 #define SPI_CMD_RESUME BIT(1)
56 #define SPI_CMD_RST BIT(2)
57 #define SPI_CMD_PAUSE_EN BIT(4)
58 #define SPI_CMD_DEASSERT BIT(5)
59 #define SPI_CMD_SAMPLE_SEL BIT(6)
60 #define SPI_CMD_CS_POL BIT(7)
61 #define SPI_CMD_CPHA BIT(8)
62 #define SPI_CMD_CPOL BIT(9)
63 #define SPI_CMD_RX_DMA BIT(10)
64 #define SPI_CMD_TX_DMA BIT(11)
65 #define SPI_CMD_TXMSBF BIT(12)
66 #define SPI_CMD_RXMSBF BIT(13)
67 #define SPI_CMD_RX_ENDIAN BIT(14)
68 #define SPI_CMD_TX_ENDIAN BIT(15)
69 #define SPI_CMD_FINISH_IE BIT(16)
70 #define SPI_CMD_PAUSE_IE BIT(17)
72 #define MT8173_SPI_MAX_PAD_SEL 3
74 #define MTK_SPI_PAUSE_INT_STATUS 0x2
76 #define MTK_SPI_IDLE 0
77 #define MTK_SPI_PAUSED 1
79 #define MTK_SPI_MAX_FIFO_SIZE 32U
80 #define MTK_SPI_PACKET_SIZE 1024
81 #define MTK_SPI_32BITS_MASK (0xffffffff)
83 #define DMA_ADDR_EXT_BITS (36)
84 #define DMA_ADDR_DEF_BITS (32)
86 struct mtk_spi_compatible {
88 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
90 /* some IC design adjust cfg register to enhance time accuracy */
92 /* some IC support DMA addr extension */
94 /* some IC no need unprepare SPI clk */
95 bool no_need_unprepare;
103 struct clk *parent_clk, *sel_clk, *spi_clk;
104 struct spi_transfer *cur_transfer;
107 struct scatterlist *tx_sgl, *rx_sgl;
108 u32 tx_sgl_len, rx_sgl_len;
109 const struct mtk_spi_compatible *dev_comp;
113 static const struct mtk_spi_compatible mtk_common_compat;
115 static const struct mtk_spi_compatible mt2712_compat = {
119 static const struct mtk_spi_compatible mt6765_compat = {
120 .need_pad_sel = true,
122 .enhance_timing = true,
126 static const struct mtk_spi_compatible mt7622_compat = {
128 .enhance_timing = true,
131 static const struct mtk_spi_compatible mt8173_compat = {
132 .need_pad_sel = true,
136 static const struct mtk_spi_compatible mt8183_compat = {
137 .need_pad_sel = true,
139 .enhance_timing = true,
142 static const struct mtk_spi_compatible mt6893_compat = {
143 .need_pad_sel = true,
145 .enhance_timing = true,
147 .no_need_unprepare = true,
151 * A piece of default chip info unless the platform
154 static const struct mtk_chip_config mtk_default_chip_info = {
159 static const struct of_device_id mtk_spi_of_match[] = {
160 { .compatible = "mediatek,mt2701-spi",
161 .data = (void *)&mtk_common_compat,
163 { .compatible = "mediatek,mt2712-spi",
164 .data = (void *)&mt2712_compat,
166 { .compatible = "mediatek,mt6589-spi",
167 .data = (void *)&mtk_common_compat,
169 { .compatible = "mediatek,mt6765-spi",
170 .data = (void *)&mt6765_compat,
172 { .compatible = "mediatek,mt7622-spi",
173 .data = (void *)&mt7622_compat,
175 { .compatible = "mediatek,mt7629-spi",
176 .data = (void *)&mt7622_compat,
178 { .compatible = "mediatek,mt8135-spi",
179 .data = (void *)&mtk_common_compat,
181 { .compatible = "mediatek,mt8173-spi",
182 .data = (void *)&mt8173_compat,
184 { .compatible = "mediatek,mt8183-spi",
185 .data = (void *)&mt8183_compat,
187 { .compatible = "mediatek,mt8192-spi",
188 .data = (void *)&mt6765_compat,
190 { .compatible = "mediatek,mt6893-spi",
191 .data = (void *)&mt6893_compat,
195 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
197 static void mtk_spi_reset(struct mtk_spi *mdata)
201 /* set the software reset bit in SPI_CMD_REG. */
202 reg_val = readl(mdata->base + SPI_CMD_REG);
203 reg_val |= SPI_CMD_RST;
204 writel(reg_val, mdata->base + SPI_CMD_REG);
206 reg_val = readl(mdata->base + SPI_CMD_REG);
207 reg_val &= ~SPI_CMD_RST;
208 writel(reg_val, mdata->base + SPI_CMD_REG);
211 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
213 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
214 struct spi_delay *cs_setup = &spi->cs_setup;
215 struct spi_delay *cs_hold = &spi->cs_hold;
216 struct spi_delay *cs_inactive = &spi->cs_inactive;
217 u32 setup, hold, inactive;
221 delay = spi_delay_to_ns(cs_setup, NULL);
224 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
226 delay = spi_delay_to_ns(cs_hold, NULL);
229 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
231 delay = spi_delay_to_ns(cs_inactive, NULL);
234 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
236 setup = setup ? setup : 1;
237 hold = hold ? hold : 1;
238 inactive = inactive ? inactive : 1;
240 reg_val = readl(mdata->base + SPI_CFG0_REG);
241 if (mdata->dev_comp->enhance_timing) {
242 hold = min_t(u32, hold, 0x10000);
243 setup = min_t(u32, setup, 0x10000);
244 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
245 reg_val |= (((hold - 1) & 0xffff)
246 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
247 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
248 reg_val |= (((setup - 1) & 0xffff)
249 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
251 hold = min_t(u32, hold, 0x100);
252 setup = min_t(u32, setup, 0x100);
253 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
254 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
255 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
256 reg_val |= (((setup - 1) & 0xff)
257 << SPI_CFG0_CS_SETUP_OFFSET);
259 writel(reg_val, mdata->base + SPI_CFG0_REG);
261 inactive = min_t(u32, inactive, 0x100);
262 reg_val = readl(mdata->base + SPI_CFG1_REG);
263 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
264 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
265 writel(reg_val, mdata->base + SPI_CFG1_REG);
270 static int mtk_spi_prepare_message(struct spi_master *master,
271 struct spi_message *msg)
275 struct spi_device *spi = msg->spi;
276 struct mtk_chip_config *chip_config = spi->controller_data;
277 struct mtk_spi *mdata = spi_master_get_devdata(master);
279 cpha = spi->mode & SPI_CPHA ? 1 : 0;
280 cpol = spi->mode & SPI_CPOL ? 1 : 0;
282 reg_val = readl(mdata->base + SPI_CMD_REG);
284 reg_val |= SPI_CMD_CPHA;
286 reg_val &= ~SPI_CMD_CPHA;
288 reg_val |= SPI_CMD_CPOL;
290 reg_val &= ~SPI_CMD_CPOL;
292 /* set the mlsbx and mlsbtx */
293 if (spi->mode & SPI_LSB_FIRST) {
294 reg_val &= ~SPI_CMD_TXMSBF;
295 reg_val &= ~SPI_CMD_RXMSBF;
297 reg_val |= SPI_CMD_TXMSBF;
298 reg_val |= SPI_CMD_RXMSBF;
301 /* set the tx/rx endian */
302 #ifdef __LITTLE_ENDIAN
303 reg_val &= ~SPI_CMD_TX_ENDIAN;
304 reg_val &= ~SPI_CMD_RX_ENDIAN;
306 reg_val |= SPI_CMD_TX_ENDIAN;
307 reg_val |= SPI_CMD_RX_ENDIAN;
310 if (mdata->dev_comp->enhance_timing) {
311 /* set CS polarity */
312 if (spi->mode & SPI_CS_HIGH)
313 reg_val |= SPI_CMD_CS_POL;
315 reg_val &= ~SPI_CMD_CS_POL;
317 if (chip_config->sample_sel)
318 reg_val |= SPI_CMD_SAMPLE_SEL;
320 reg_val &= ~SPI_CMD_SAMPLE_SEL;
323 /* set finish and pause interrupt always enable */
324 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
326 /* disable dma mode */
327 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
329 /* disable deassert mode */
330 reg_val &= ~SPI_CMD_DEASSERT;
332 writel(reg_val, mdata->base + SPI_CMD_REG);
335 if (mdata->dev_comp->need_pad_sel)
336 writel(mdata->pad_sel[spi->chip_select],
337 mdata->base + SPI_PAD_SEL_REG);
340 reg_val = readl(mdata->base + SPI_CFG1_REG);
341 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
342 reg_val |= ((chip_config->tick_delay & 0x7)
343 << SPI_CFG1_GET_TICK_DLY_OFFSET);
344 writel(reg_val, mdata->base + SPI_CFG1_REG);
346 /* set hw cs timing */
347 mtk_spi_set_hw_cs_timing(spi);
351 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
354 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
356 if (spi->mode & SPI_CS_HIGH)
359 reg_val = readl(mdata->base + SPI_CMD_REG);
361 reg_val |= SPI_CMD_PAUSE_EN;
362 writel(reg_val, mdata->base + SPI_CMD_REG);
364 reg_val &= ~SPI_CMD_PAUSE_EN;
365 writel(reg_val, mdata->base + SPI_CMD_REG);
366 mdata->state = MTK_SPI_IDLE;
367 mtk_spi_reset(mdata);
371 static void mtk_spi_prepare_transfer(struct spi_master *master,
372 struct spi_transfer *xfer)
374 u32 div, sck_time, reg_val;
375 struct mtk_spi *mdata = spi_master_get_devdata(master);
377 if (xfer->speed_hz < mdata->spi_clk_hz / 2)
378 div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz);
382 sck_time = (div + 1) / 2;
384 if (mdata->dev_comp->enhance_timing) {
385 reg_val = readl(mdata->base + SPI_CFG2_REG);
386 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
387 reg_val |= (((sck_time - 1) & 0xffff)
388 << SPI_CFG2_SCK_HIGH_OFFSET);
389 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
390 reg_val |= (((sck_time - 1) & 0xffff)
391 << SPI_CFG2_SCK_LOW_OFFSET);
392 writel(reg_val, mdata->base + SPI_CFG2_REG);
394 reg_val = readl(mdata->base + SPI_CFG0_REG);
395 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
396 reg_val |= (((sck_time - 1) & 0xff)
397 << SPI_CFG0_SCK_HIGH_OFFSET);
398 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
399 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
400 writel(reg_val, mdata->base + SPI_CFG0_REG);
404 static void mtk_spi_setup_packet(struct spi_master *master)
406 u32 packet_size, packet_loop, reg_val;
407 struct mtk_spi *mdata = spi_master_get_devdata(master);
409 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
410 packet_loop = mdata->xfer_len / packet_size;
412 reg_val = readl(mdata->base + SPI_CFG1_REG);
413 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
414 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
415 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
416 writel(reg_val, mdata->base + SPI_CFG1_REG);
419 static void mtk_spi_enable_transfer(struct spi_master *master)
422 struct mtk_spi *mdata = spi_master_get_devdata(master);
424 cmd = readl(mdata->base + SPI_CMD_REG);
425 if (mdata->state == MTK_SPI_IDLE)
428 cmd |= SPI_CMD_RESUME;
429 writel(cmd, mdata->base + SPI_CMD_REG);
432 static int mtk_spi_get_mult_delta(u32 xfer_len)
436 if (xfer_len > MTK_SPI_PACKET_SIZE)
437 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
444 static void mtk_spi_update_mdata_len(struct spi_master *master)
447 struct mtk_spi *mdata = spi_master_get_devdata(master);
449 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
450 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
451 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
452 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
453 mdata->rx_sgl_len = mult_delta;
454 mdata->tx_sgl_len -= mdata->xfer_len;
456 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
457 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
458 mdata->tx_sgl_len = mult_delta;
459 mdata->rx_sgl_len -= mdata->xfer_len;
461 } else if (mdata->tx_sgl_len) {
462 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
463 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
464 mdata->tx_sgl_len = mult_delta;
465 } else if (mdata->rx_sgl_len) {
466 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
467 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
468 mdata->rx_sgl_len = mult_delta;
472 static void mtk_spi_setup_dma_addr(struct spi_master *master,
473 struct spi_transfer *xfer)
475 struct mtk_spi *mdata = spi_master_get_devdata(master);
478 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
479 mdata->base + SPI_TX_SRC_REG);
480 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
481 if (mdata->dev_comp->dma_ext)
482 writel((u32)(xfer->tx_dma >> 32),
483 mdata->base + SPI_TX_SRC_REG_64);
488 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
489 mdata->base + SPI_RX_DST_REG);
490 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
491 if (mdata->dev_comp->dma_ext)
492 writel((u32)(xfer->rx_dma >> 32),
493 mdata->base + SPI_RX_DST_REG_64);
498 static int mtk_spi_fifo_transfer(struct spi_master *master,
499 struct spi_device *spi,
500 struct spi_transfer *xfer)
504 struct mtk_spi *mdata = spi_master_get_devdata(master);
506 mdata->cur_transfer = xfer;
507 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
508 mdata->num_xfered = 0;
509 mtk_spi_prepare_transfer(master, xfer);
510 mtk_spi_setup_packet(master);
514 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
515 remainder = xfer->len % 4;
518 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
519 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
523 mtk_spi_enable_transfer(master);
528 static int mtk_spi_dma_transfer(struct spi_master *master,
529 struct spi_device *spi,
530 struct spi_transfer *xfer)
533 struct mtk_spi *mdata = spi_master_get_devdata(master);
535 mdata->tx_sgl = NULL;
536 mdata->rx_sgl = NULL;
537 mdata->tx_sgl_len = 0;
538 mdata->rx_sgl_len = 0;
539 mdata->cur_transfer = xfer;
540 mdata->num_xfered = 0;
542 mtk_spi_prepare_transfer(master, xfer);
544 cmd = readl(mdata->base + SPI_CMD_REG);
546 cmd |= SPI_CMD_TX_DMA;
548 cmd |= SPI_CMD_RX_DMA;
549 writel(cmd, mdata->base + SPI_CMD_REG);
552 mdata->tx_sgl = xfer->tx_sg.sgl;
554 mdata->rx_sgl = xfer->rx_sg.sgl;
557 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
558 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
561 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
562 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
565 mtk_spi_update_mdata_len(master);
566 mtk_spi_setup_packet(master);
567 mtk_spi_setup_dma_addr(master, xfer);
568 mtk_spi_enable_transfer(master);
573 static int mtk_spi_transfer_one(struct spi_master *master,
574 struct spi_device *spi,
575 struct spi_transfer *xfer)
577 if (master->can_dma(master, spi, xfer))
578 return mtk_spi_dma_transfer(master, spi, xfer);
580 return mtk_spi_fifo_transfer(master, spi, xfer);
583 static bool mtk_spi_can_dma(struct spi_master *master,
584 struct spi_device *spi,
585 struct spi_transfer *xfer)
587 /* Buffers for DMA transactions must be 4-byte aligned */
588 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
589 (unsigned long)xfer->tx_buf % 4 == 0 &&
590 (unsigned long)xfer->rx_buf % 4 == 0);
593 static int mtk_spi_setup(struct spi_device *spi)
595 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
597 if (!spi->controller_data)
598 spi->controller_data = (void *)&mtk_default_chip_info;
600 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
601 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
606 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
608 u32 cmd, reg_val, cnt, remainder, len;
609 struct spi_master *master = dev_id;
610 struct mtk_spi *mdata = spi_master_get_devdata(master);
611 struct spi_transfer *trans = mdata->cur_transfer;
613 reg_val = readl(mdata->base + SPI_STATUS0_REG);
614 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
615 mdata->state = MTK_SPI_PAUSED;
617 mdata->state = MTK_SPI_IDLE;
619 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
621 cnt = mdata->xfer_len / 4;
622 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
623 trans->rx_buf + mdata->num_xfered, cnt);
624 remainder = mdata->xfer_len % 4;
626 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
627 memcpy(trans->rx_buf +
635 mdata->num_xfered += mdata->xfer_len;
636 if (mdata->num_xfered == trans->len) {
637 spi_finalize_current_transfer(master);
641 len = trans->len - mdata->num_xfered;
642 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
643 mtk_spi_setup_packet(master);
645 cnt = mdata->xfer_len / 4;
646 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
647 trans->tx_buf + mdata->num_xfered, cnt);
649 remainder = mdata->xfer_len % 4;
653 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
655 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
658 mtk_spi_enable_transfer(master);
664 trans->tx_dma += mdata->xfer_len;
666 trans->rx_dma += mdata->xfer_len;
668 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
669 mdata->tx_sgl = sg_next(mdata->tx_sgl);
671 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
672 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
675 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
676 mdata->rx_sgl = sg_next(mdata->rx_sgl);
678 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
679 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
683 if (!mdata->tx_sgl && !mdata->rx_sgl) {
684 /* spi disable dma */
685 cmd = readl(mdata->base + SPI_CMD_REG);
686 cmd &= ~SPI_CMD_TX_DMA;
687 cmd &= ~SPI_CMD_RX_DMA;
688 writel(cmd, mdata->base + SPI_CMD_REG);
690 spi_finalize_current_transfer(master);
694 mtk_spi_update_mdata_len(master);
695 mtk_spi_setup_packet(master);
696 mtk_spi_setup_dma_addr(master, trans);
697 mtk_spi_enable_transfer(master);
702 static int mtk_spi_probe(struct platform_device *pdev)
704 struct spi_master *master;
705 struct mtk_spi *mdata;
706 const struct of_device_id *of_id;
707 int i, irq, ret, addr_bits;
709 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
711 dev_err(&pdev->dev, "failed to alloc spi master\n");
715 master->auto_runtime_pm = true;
716 master->dev.of_node = pdev->dev.of_node;
717 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
719 master->set_cs = mtk_spi_set_cs;
720 master->prepare_message = mtk_spi_prepare_message;
721 master->transfer_one = mtk_spi_transfer_one;
722 master->can_dma = mtk_spi_can_dma;
723 master->setup = mtk_spi_setup;
724 master->set_cs_timing = mtk_spi_set_hw_cs_timing;
726 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
728 dev_err(&pdev->dev, "failed to probe of_node\n");
733 mdata = spi_master_get_devdata(master);
734 mdata->dev_comp = of_id->data;
736 if (mdata->dev_comp->enhance_timing)
737 master->mode_bits |= SPI_CS_HIGH;
739 if (mdata->dev_comp->must_tx)
740 master->flags = SPI_MASTER_MUST_TX;
742 if (mdata->dev_comp->need_pad_sel) {
743 mdata->pad_num = of_property_count_u32_elems(
745 "mediatek,pad-select");
746 if (mdata->pad_num < 0) {
748 "No 'mediatek,pad-select' property\n");
753 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
754 sizeof(u32), GFP_KERNEL);
755 if (!mdata->pad_sel) {
760 for (i = 0; i < mdata->pad_num; i++) {
761 of_property_read_u32_index(pdev->dev.of_node,
762 "mediatek,pad-select",
763 i, &mdata->pad_sel[i]);
764 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
765 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
766 i, mdata->pad_sel[i]);
773 platform_set_drvdata(pdev, master);
774 mdata->base = devm_platform_ioremap_resource(pdev, 0);
775 if (IS_ERR(mdata->base)) {
776 ret = PTR_ERR(mdata->base);
780 irq = platform_get_irq(pdev, 0);
786 if (!pdev->dev.dma_mask)
787 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
789 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
790 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
792 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
796 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
797 if (IS_ERR(mdata->parent_clk)) {
798 ret = PTR_ERR(mdata->parent_clk);
799 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
803 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
804 if (IS_ERR(mdata->sel_clk)) {
805 ret = PTR_ERR(mdata->sel_clk);
806 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
810 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
811 if (IS_ERR(mdata->spi_clk)) {
812 ret = PTR_ERR(mdata->spi_clk);
813 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
817 ret = clk_prepare_enable(mdata->spi_clk);
819 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
823 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
825 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
826 clk_disable_unprepare(mdata->spi_clk);
830 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
832 if (mdata->dev_comp->no_need_unprepare)
833 clk_disable(mdata->spi_clk);
835 clk_disable_unprepare(mdata->spi_clk);
837 pm_runtime_enable(&pdev->dev);
839 if (mdata->dev_comp->need_pad_sel) {
840 if (mdata->pad_num != master->num_chipselect) {
842 "pad_num does not match num_chipselect(%d != %d)\n",
843 mdata->pad_num, master->num_chipselect);
845 goto err_disable_runtime_pm;
848 if (!master->cs_gpios && master->num_chipselect > 1) {
850 "cs_gpios not specified and num_chipselect > 1\n");
852 goto err_disable_runtime_pm;
855 if (master->cs_gpios) {
856 for (i = 0; i < master->num_chipselect; i++) {
857 ret = devm_gpio_request(&pdev->dev,
859 dev_name(&pdev->dev));
862 "can't get CS GPIO %i\n", i);
863 goto err_disable_runtime_pm;
869 if (mdata->dev_comp->dma_ext)
870 addr_bits = DMA_ADDR_EXT_BITS;
872 addr_bits = DMA_ADDR_DEF_BITS;
873 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
875 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
878 ret = devm_spi_register_master(&pdev->dev, master);
880 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
881 goto err_disable_runtime_pm;
886 err_disable_runtime_pm:
887 pm_runtime_disable(&pdev->dev);
889 spi_master_put(master);
894 static int mtk_spi_remove(struct platform_device *pdev)
896 struct spi_master *master = platform_get_drvdata(pdev);
897 struct mtk_spi *mdata = spi_master_get_devdata(master);
899 pm_runtime_disable(&pdev->dev);
901 mtk_spi_reset(mdata);
903 if (mdata->dev_comp->no_need_unprepare)
904 clk_unprepare(mdata->spi_clk);
909 #ifdef CONFIG_PM_SLEEP
910 static int mtk_spi_suspend(struct device *dev)
913 struct spi_master *master = dev_get_drvdata(dev);
914 struct mtk_spi *mdata = spi_master_get_devdata(master);
916 ret = spi_master_suspend(master);
920 if (!pm_runtime_suspended(dev))
921 clk_disable_unprepare(mdata->spi_clk);
926 static int mtk_spi_resume(struct device *dev)
929 struct spi_master *master = dev_get_drvdata(dev);
930 struct mtk_spi *mdata = spi_master_get_devdata(master);
932 if (!pm_runtime_suspended(dev)) {
933 ret = clk_prepare_enable(mdata->spi_clk);
935 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
940 ret = spi_master_resume(master);
942 clk_disable_unprepare(mdata->spi_clk);
946 #endif /* CONFIG_PM_SLEEP */
949 static int mtk_spi_runtime_suspend(struct device *dev)
951 struct spi_master *master = dev_get_drvdata(dev);
952 struct mtk_spi *mdata = spi_master_get_devdata(master);
954 if (mdata->dev_comp->no_need_unprepare)
955 clk_disable(mdata->spi_clk);
957 clk_disable_unprepare(mdata->spi_clk);
962 static int mtk_spi_runtime_resume(struct device *dev)
964 struct spi_master *master = dev_get_drvdata(dev);
965 struct mtk_spi *mdata = spi_master_get_devdata(master);
968 if (mdata->dev_comp->no_need_unprepare)
969 ret = clk_enable(mdata->spi_clk);
971 ret = clk_prepare_enable(mdata->spi_clk);
973 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
979 #endif /* CONFIG_PM */
981 static const struct dev_pm_ops mtk_spi_pm = {
982 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
983 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
984 mtk_spi_runtime_resume, NULL)
987 static struct platform_driver mtk_spi_driver = {
991 .of_match_table = mtk_spi_of_match,
993 .probe = mtk_spi_probe,
994 .remove = mtk_spi_remove,
997 module_platform_driver(mtk_spi_driver);
999 MODULE_DESCRIPTION("MTK SPI Controller driver");
1000 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
1001 MODULE_LICENSE("GPL v2");
1002 MODULE_ALIAS("platform:mtk-spi");