Merge tag 'for-5.7/dm-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/devic...
[linux-2.6-microblaze.git] / drivers / spi / spi-meson-spicc.c
1 /*
2  * Driver for Amlogic Meson SPI communication controller (SPICC)
3  *
4  * Copyright (C) BayLibre, SAS
5  * Author: Neil Armstrong <narmstrong@baylibre.com>
6  *
7  * SPDX-License-Identifier: GPL-2.0+
8  */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/device.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22 #include <linux/interrupt.h>
23 #include <linux/reset.h>
24
25 /*
26  * The Meson SPICC controller could support DMA based transfers, but is not
27  * implemented by the vendor code, and while having the registers documentation
28  * it has never worked on the GXL Hardware.
29  * The PIO mode is the only mode implemented, and due to badly designed HW :
30  * - all transfers are cutted in 16 words burst because the FIFO hangs on
31  *   TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
32  *   FIFO max size chunk only
33  * - CS management is dumb, and goes UP between every burst, so is really a
34  *   "Data Valid" signal than a Chip Select, GPIO link should be used instead
35  *   to have a CS go down over the full transfer
36  */
37
38 #define SPICC_MAX_BURST 128
39
40 /* Register Map */
41 #define SPICC_RXDATA    0x00
42
43 #define SPICC_TXDATA    0x04
44
45 #define SPICC_CONREG    0x08
46 #define SPICC_ENABLE            BIT(0)
47 #define SPICC_MODE_MASTER       BIT(1)
48 #define SPICC_XCH               BIT(2)
49 #define SPICC_SMC               BIT(3)
50 #define SPICC_POL               BIT(4)
51 #define SPICC_PHA               BIT(5)
52 #define SPICC_SSCTL             BIT(6)
53 #define SPICC_SSPOL             BIT(7)
54 #define SPICC_DRCTL_MASK        GENMASK(9, 8)
55 #define SPICC_DRCTL_IGNORE      0
56 #define SPICC_DRCTL_FALLING     1
57 #define SPICC_DRCTL_LOWLEVEL    2
58 #define SPICC_CS_MASK           GENMASK(13, 12)
59 #define SPICC_DATARATE_MASK     GENMASK(18, 16)
60 #define SPICC_DATARATE_DIV4     0
61 #define SPICC_DATARATE_DIV8     1
62 #define SPICC_DATARATE_DIV16    2
63 #define SPICC_DATARATE_DIV32    3
64 #define SPICC_BITLENGTH_MASK    GENMASK(24, 19)
65 #define SPICC_BURSTLENGTH_MASK  GENMASK(31, 25)
66
67 #define SPICC_INTREG    0x0c
68 #define SPICC_TE_EN     BIT(0) /* TX FIFO Empty Interrupt */
69 #define SPICC_TH_EN     BIT(1) /* TX FIFO Half-Full Interrupt */
70 #define SPICC_TF_EN     BIT(2) /* TX FIFO Full Interrupt */
71 #define SPICC_RR_EN     BIT(3) /* RX FIFO Ready Interrupt */
72 #define SPICC_RH_EN     BIT(4) /* RX FIFO Half-Full Interrupt */
73 #define SPICC_RF_EN     BIT(5) /* RX FIFO Full Interrupt */
74 #define SPICC_RO_EN     BIT(6) /* RX FIFO Overflow Interrupt */
75 #define SPICC_TC_EN     BIT(7) /* Transfert Complete Interrupt */
76
77 #define SPICC_DMAREG    0x10
78 #define SPICC_DMA_ENABLE                BIT(0)
79 #define SPICC_TXFIFO_THRESHOLD_MASK     GENMASK(5, 1)
80 #define SPICC_RXFIFO_THRESHOLD_MASK     GENMASK(10, 6)
81 #define SPICC_READ_BURST_MASK           GENMASK(14, 11)
82 #define SPICC_WRITE_BURST_MASK          GENMASK(18, 15)
83 #define SPICC_DMA_URGENT                BIT(19)
84 #define SPICC_DMA_THREADID_MASK         GENMASK(25, 20)
85 #define SPICC_DMA_BURSTNUM_MASK         GENMASK(31, 26)
86
87 #define SPICC_STATREG   0x14
88 #define SPICC_TE        BIT(0) /* TX FIFO Empty Interrupt */
89 #define SPICC_TH        BIT(1) /* TX FIFO Half-Full Interrupt */
90 #define SPICC_TF        BIT(2) /* TX FIFO Full Interrupt */
91 #define SPICC_RR        BIT(3) /* RX FIFO Ready Interrupt */
92 #define SPICC_RH        BIT(4) /* RX FIFO Half-Full Interrupt */
93 #define SPICC_RF        BIT(5) /* RX FIFO Full Interrupt */
94 #define SPICC_RO        BIT(6) /* RX FIFO Overflow Interrupt */
95 #define SPICC_TC        BIT(7) /* Transfert Complete Interrupt */
96
97 #define SPICC_PERIODREG 0x18
98 #define SPICC_PERIOD    GENMASK(14, 0)  /* Wait cycles */
99
100 #define SPICC_TESTREG   0x1c
101 #define SPICC_TXCNT_MASK        GENMASK(4, 0)   /* TX FIFO Counter */
102 #define SPICC_RXCNT_MASK        GENMASK(9, 5)   /* RX FIFO Counter */
103 #define SPICC_SMSTATUS_MASK     GENMASK(12, 10) /* State Machine Status */
104 #define SPICC_LBC_RO            BIT(13) /* Loop Back Control Read-Only */
105 #define SPICC_LBC_W1            BIT(14) /* Loop Back Control Write-Only */
106 #define SPICC_SWAP_RO           BIT(14) /* RX FIFO Data Swap Read-Only */
107 #define SPICC_SWAP_W1           BIT(15) /* RX FIFO Data Swap Write-Only */
108 #define SPICC_DLYCTL_RO_MASK    GENMASK(20, 15) /* Delay Control Read-Only */
109 #define SPICC_MO_DELAY_MASK     GENMASK(17, 16) /* Master Output Delay */
110 #define SPICC_MO_NO_DELAY       0
111 #define SPICC_MO_DELAY_1_CYCLE  1
112 #define SPICC_MO_DELAY_2_CYCLE  2
113 #define SPICC_MO_DELAY_3_CYCLE  3
114 #define SPICC_MI_DELAY_MASK     GENMASK(19, 18) /* Master Input Delay */
115 #define SPICC_MI_NO_DELAY       0
116 #define SPICC_MI_DELAY_1_CYCLE  1
117 #define SPICC_MI_DELAY_2_CYCLE  2
118 #define SPICC_MI_DELAY_3_CYCLE  3
119 #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
120 #define SPICC_CAP_AHEAD_2_CYCLE 0
121 #define SPICC_CAP_AHEAD_1_CYCLE 1
122 #define SPICC_CAP_NO_DELAY      2
123 #define SPICC_CAP_DELAY_1_CYCLE 3
124 #define SPICC_FIFORST_RO_MASK   GENMASK(22, 21) /* FIFO Softreset Read-Only */
125 #define SPICC_FIFORST_W1_MASK   GENMASK(23, 22) /* FIFO Softreset Write-Only */
126
127 #define SPICC_DRADDR    0x20    /* Read Address of DMA */
128
129 #define SPICC_DWADDR    0x24    /* Write Address of DMA */
130
131 #define SPICC_ENH_CTL0  0x38    /* Enhanced Feature */
132 #define SPICC_ENH_CLK_CS_DELAY_MASK     GENMASK(15, 0)
133 #define SPICC_ENH_DATARATE_MASK         GENMASK(23, 16)
134 #define SPICC_ENH_DATARATE_EN           BIT(24)
135 #define SPICC_ENH_MOSI_OEN              BIT(25)
136 #define SPICC_ENH_CLK_OEN               BIT(26)
137 #define SPICC_ENH_CS_OEN                BIT(27)
138 #define SPICC_ENH_CLK_CS_DELAY_EN       BIT(28)
139 #define SPICC_ENH_MAIN_CLK_AO           BIT(29)
140
141 #define writel_bits_relaxed(mask, val, addr) \
142         writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
143
144 struct meson_spicc_data {
145         unsigned int                    max_speed_hz;
146         unsigned int                    min_speed_hz;
147         unsigned int                    fifo_size;
148         bool                            has_oen;
149         bool                            has_enhance_clk_div;
150         bool                            has_pclk;
151 };
152
153 struct meson_spicc_device {
154         struct spi_master               *master;
155         struct platform_device          *pdev;
156         void __iomem                    *base;
157         struct clk                      *core;
158         struct clk                      *pclk;
159         struct clk                      *clk;
160         struct spi_message              *message;
161         struct spi_transfer             *xfer;
162         const struct meson_spicc_data   *data;
163         u8                              *tx_buf;
164         u8                              *rx_buf;
165         unsigned int                    bytes_per_word;
166         unsigned long                   tx_remain;
167         unsigned long                   rx_remain;
168         unsigned long                   xfer_remain;
169 };
170
171 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
172 {
173         u32 conf;
174
175         if (!spicc->data->has_oen)
176                 return;
177
178         conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
179                 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
180
181         writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
182 }
183
184 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
185 {
186         return !!FIELD_GET(SPICC_TF,
187                            readl_relaxed(spicc->base + SPICC_STATREG));
188 }
189
190 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
191 {
192         return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
193                          readl_relaxed(spicc->base + SPICC_STATREG));
194 }
195
196 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
197 {
198         unsigned int bytes = spicc->bytes_per_word;
199         unsigned int byte_shift = 0;
200         u32 data = 0;
201         u8 byte;
202
203         while (bytes--) {
204                 byte = *spicc->tx_buf++;
205                 data |= (byte & 0xff) << byte_shift;
206                 byte_shift += 8;
207         }
208
209         spicc->tx_remain--;
210         return data;
211 }
212
213 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
214                                          u32 data)
215 {
216         unsigned int bytes = spicc->bytes_per_word;
217         unsigned int byte_shift = 0;
218         u8 byte;
219
220         while (bytes--) {
221                 byte = (data >> byte_shift) & 0xff;
222                 *spicc->rx_buf++ = byte;
223                 byte_shift += 8;
224         }
225
226         spicc->rx_remain--;
227 }
228
229 static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
230 {
231         /* Empty RX FIFO */
232         while (spicc->rx_remain &&
233                meson_spicc_rxready(spicc))
234                 meson_spicc_push_data(spicc,
235                                 readl_relaxed(spicc->base + SPICC_RXDATA));
236 }
237
238 static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
239 {
240         /* Fill Up TX FIFO */
241         while (spicc->tx_remain &&
242                !meson_spicc_txfull(spicc))
243                 writel_relaxed(meson_spicc_pull_data(spicc),
244                                spicc->base + SPICC_TXDATA);
245 }
246
247 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
248 {
249
250         unsigned int burst_len = min_t(unsigned int,
251                                        spicc->xfer_remain /
252                                        spicc->bytes_per_word,
253                                        spicc->data->fifo_size);
254         /* Setup Xfer variables */
255         spicc->tx_remain = burst_len;
256         spicc->rx_remain = burst_len;
257         spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
258
259         /* Setup burst length */
260         writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
261                         FIELD_PREP(SPICC_BURSTLENGTH_MASK,
262                                 burst_len - 1),
263                         spicc->base + SPICC_CONREG);
264
265         /* Fill TX FIFO */
266         meson_spicc_tx(spicc);
267 }
268
269 static irqreturn_t meson_spicc_irq(int irq, void *data)
270 {
271         struct meson_spicc_device *spicc = (void *) data;
272
273         writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
274
275         /* Empty RX FIFO */
276         meson_spicc_rx(spicc);
277
278         if (!spicc->xfer_remain) {
279                 /* Disable all IRQs */
280                 writel(0, spicc->base + SPICC_INTREG);
281
282                 spi_finalize_current_transfer(spicc->master);
283
284                 return IRQ_HANDLED;
285         }
286
287         /* Setup burst */
288         meson_spicc_setup_burst(spicc);
289
290         /* Start burst */
291         writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
292
293         return IRQ_HANDLED;
294 }
295
296 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
297 {
298         u32 div, hz;
299         u32 mi_delay, cap_delay;
300         u32 conf;
301
302         if (spicc->data->has_enhance_clk_div) {
303                 div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
304                                 readl_relaxed(spicc->base + SPICC_ENH_CTL0));
305                 div++;
306                 div <<= 1;
307         } else {
308                 div = FIELD_GET(SPICC_DATARATE_MASK,
309                                 readl_relaxed(spicc->base + SPICC_CONREG));
310                 div += 2;
311                 div = 1 << div;
312         }
313
314         mi_delay = SPICC_MI_NO_DELAY;
315         cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
316         hz = clk_get_rate(spicc->clk);
317
318         if (hz >= 100000000)
319                 cap_delay = SPICC_CAP_DELAY_1_CYCLE;
320         else if (hz >= 80000000)
321                 cap_delay = SPICC_CAP_NO_DELAY;
322         else if (hz >= 40000000)
323                 cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
324         else if (div >= 16)
325                 mi_delay = SPICC_MI_DELAY_3_CYCLE;
326         else if (div >= 8)
327                 mi_delay = SPICC_MI_DELAY_2_CYCLE;
328         else if (div >= 6)
329                 mi_delay = SPICC_MI_DELAY_1_CYCLE;
330
331         conf = readl_relaxed(spicc->base + SPICC_TESTREG);
332         conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
333                   | SPICC_MI_CAP_DELAY_MASK);
334         conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
335         conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
336         writel_relaxed(conf, spicc->base + SPICC_TESTREG);
337 }
338
339 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
340                                    struct spi_transfer *xfer)
341 {
342         u32 conf, conf_orig;
343
344         /* Read original configuration */
345         conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
346
347         /* Setup word width */
348         conf &= ~SPICC_BITLENGTH_MASK;
349         conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
350                            (spicc->bytes_per_word << 3) - 1);
351
352         /* Ignore if unchanged */
353         if (conf != conf_orig)
354                 writel_relaxed(conf, spicc->base + SPICC_CONREG);
355
356         clk_set_rate(spicc->clk, xfer->speed_hz);
357
358         meson_spicc_auto_io_delay(spicc);
359
360         writel_relaxed(0, spicc->base + SPICC_DMAREG);
361 }
362
363 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
364 {
365         u32 data;
366
367         if (spicc->data->has_oen)
368                 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
369                                     SPICC_ENH_MAIN_CLK_AO,
370                                     spicc->base + SPICC_ENH_CTL0);
371
372         writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
373                             spicc->base + SPICC_TESTREG);
374
375         while (meson_spicc_rxready(spicc))
376                 data = readl_relaxed(spicc->base + SPICC_RXDATA);
377
378         if (spicc->data->has_oen)
379                 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
380                                     spicc->base + SPICC_ENH_CTL0);
381 }
382
383 static int meson_spicc_transfer_one(struct spi_master *master,
384                                     struct spi_device *spi,
385                                     struct spi_transfer *xfer)
386 {
387         struct meson_spicc_device *spicc = spi_master_get_devdata(master);
388
389         /* Store current transfer */
390         spicc->xfer = xfer;
391
392         /* Setup transfer parameters */
393         spicc->tx_buf = (u8 *)xfer->tx_buf;
394         spicc->rx_buf = (u8 *)xfer->rx_buf;
395         spicc->xfer_remain = xfer->len;
396
397         /* Pre-calculate word size */
398         spicc->bytes_per_word =
399            DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
400
401         if (xfer->len % spicc->bytes_per_word)
402                 return -EINVAL;
403
404         /* Setup transfer parameters */
405         meson_spicc_setup_xfer(spicc, xfer);
406
407         meson_spicc_reset_fifo(spicc);
408
409         /* Setup burst */
410         meson_spicc_setup_burst(spicc);
411
412         /* Start burst */
413         writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
414
415         /* Enable interrupts */
416         writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
417
418         return 1;
419 }
420
421 static int meson_spicc_prepare_message(struct spi_master *master,
422                                        struct spi_message *message)
423 {
424         struct meson_spicc_device *spicc = spi_master_get_devdata(master);
425         struct spi_device *spi = message->spi;
426         u32 conf = 0;
427
428         /* Store current message */
429         spicc->message = message;
430
431         /* Enable Master */
432         conf |= SPICC_ENABLE;
433         conf |= SPICC_MODE_MASTER;
434
435         /* SMC = 0 */
436
437         /* Setup transfer mode */
438         if (spi->mode & SPI_CPOL)
439                 conf |= SPICC_POL;
440         else
441                 conf &= ~SPICC_POL;
442
443         if (spi->mode & SPI_CPHA)
444                 conf |= SPICC_PHA;
445         else
446                 conf &= ~SPICC_PHA;
447
448         /* SSCTL = 0 */
449
450         if (spi->mode & SPI_CS_HIGH)
451                 conf |= SPICC_SSPOL;
452         else
453                 conf &= ~SPICC_SSPOL;
454
455         if (spi->mode & SPI_READY)
456                 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
457         else
458                 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
459
460         /* Select CS */
461         conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
462
463         /* Default Clock rate core/4 */
464
465         /* Default 8bit word */
466         conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
467
468         writel_relaxed(conf, spicc->base + SPICC_CONREG);
469
470         /* Setup no wait cycles by default */
471         writel_relaxed(0, spicc->base + SPICC_PERIODREG);
472
473         writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
474
475         return 0;
476 }
477
478 static int meson_spicc_unprepare_transfer(struct spi_master *master)
479 {
480         struct meson_spicc_device *spicc = spi_master_get_devdata(master);
481
482         /* Disable all IRQs */
483         writel(0, spicc->base + SPICC_INTREG);
484
485         device_reset_optional(&spicc->pdev->dev);
486
487         return 0;
488 }
489
490 static int meson_spicc_setup(struct spi_device *spi)
491 {
492         if (!spi->controller_state)
493                 spi->controller_state = spi_master_get_devdata(spi->master);
494
495         return 0;
496 }
497
498 static void meson_spicc_cleanup(struct spi_device *spi)
499 {
500         spi->controller_state = NULL;
501 }
502
503 /*
504  * The Clock Mux
505  *            x-----------------x   x------------x    x------\
506  *        |---| pow2 fixed div  |---| pow2 div   |----|      |
507  *        |   x-----------------x   x------------x    |      |
508  * src ---|                                           | mux  |-- out
509  *        |   x-----------------x   x------------x    |      |
510  *        |---| enh fixed div   |---| enh div    |0---|      |
511  *            x-----------------x   x------------x    x------/
512  *
513  * Clk path for GX series:
514  *    src -> pow2 fixed div -> pow2 div -> out
515  *
516  * Clk path for AXG series:
517  *    src -> pow2 fixed div -> pow2 div -> mux -> out
518  *    src -> enh fixed div -> enh div -> mux -> out
519  *
520  * Clk path for G12A series:
521  *    pclk -> pow2 fixed div -> pow2 div -> mux -> out
522  *    pclk -> enh fixed div -> enh div -> mux -> out
523  */
524
525 static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
526 {
527         struct device *dev = &spicc->pdev->dev;
528         struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div;
529         struct clk_divider *pow2_div, *enh_div;
530         struct clk_mux *mux;
531         struct clk_init_data init;
532         struct clk *clk;
533         struct clk_parent_data parent_data[2];
534         char name[64];
535
536         memset(&init, 0, sizeof(init));
537         memset(&parent_data, 0, sizeof(parent_data));
538
539         init.parent_data = parent_data;
540
541         /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
542
543         pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
544         if (!pow2_fixed_div)
545                 return -ENOMEM;
546
547         snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
548         init.name = name;
549         init.ops = &clk_fixed_factor_ops;
550         init.flags = 0;
551         if (spicc->data->has_pclk)
552                 parent_data[0].hw = __clk_get_hw(spicc->pclk);
553         else
554                 parent_data[0].hw = __clk_get_hw(spicc->core);
555         init.num_parents = 1;
556
557         pow2_fixed_div->mult = 1,
558         pow2_fixed_div->div = 4,
559         pow2_fixed_div->hw.init = &init;
560
561         clk = devm_clk_register(dev, &pow2_fixed_div->hw);
562         if (WARN_ON(IS_ERR(clk)))
563                 return PTR_ERR(clk);
564
565         pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL);
566         if (!pow2_div)
567                 return -ENOMEM;
568
569         snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
570         init.name = name;
571         init.ops = &clk_divider_ops;
572         init.flags = CLK_SET_RATE_PARENT;
573         parent_data[0].hw = &pow2_fixed_div->hw;
574         init.num_parents = 1;
575
576         pow2_div->shift = 16,
577         pow2_div->width = 3,
578         pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO,
579         pow2_div->reg = spicc->base + SPICC_CONREG;
580         pow2_div->hw.init = &init;
581
582         clk = devm_clk_register(dev, &pow2_div->hw);
583         if (WARN_ON(IS_ERR(clk)))
584                 return PTR_ERR(clk);
585
586         if (!spicc->data->has_enhance_clk_div) {
587                 spicc->clk = clk;
588                 return 0;
589         }
590
591         /* algorithm for enh div: rate = freq / 2 / (N + 1) */
592
593         enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
594         if (!enh_fixed_div)
595                 return -ENOMEM;
596
597         snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
598         init.name = name;
599         init.ops = &clk_fixed_factor_ops;
600         init.flags = 0;
601         if (spicc->data->has_pclk)
602                 parent_data[0].hw = __clk_get_hw(spicc->pclk);
603         else
604                 parent_data[0].hw = __clk_get_hw(spicc->core);
605         init.num_parents = 1;
606
607         enh_fixed_div->mult = 1,
608         enh_fixed_div->div = 2,
609         enh_fixed_div->hw.init = &init;
610
611         clk = devm_clk_register(dev, &enh_fixed_div->hw);
612         if (WARN_ON(IS_ERR(clk)))
613                 return PTR_ERR(clk);
614
615         enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
616         if (!enh_div)
617                 return -ENOMEM;
618
619         snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
620         init.name = name;
621         init.ops = &clk_divider_ops;
622         init.flags = CLK_SET_RATE_PARENT;
623         parent_data[0].hw = &enh_fixed_div->hw;
624         init.num_parents = 1;
625
626         enh_div->shift  = 16,
627         enh_div->width  = 8,
628         enh_div->reg = spicc->base + SPICC_ENH_CTL0;
629         enh_div->hw.init = &init;
630
631         clk = devm_clk_register(dev, &enh_div->hw);
632         if (WARN_ON(IS_ERR(clk)))
633                 return PTR_ERR(clk);
634
635         mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
636         if (!mux)
637                 return -ENOMEM;
638
639         snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
640         init.name = name;
641         init.ops = &clk_mux_ops;
642         parent_data[0].hw = &pow2_div->hw;
643         parent_data[1].hw = &enh_div->hw;
644         init.num_parents = 2;
645         init.flags = CLK_SET_RATE_PARENT;
646
647         mux->mask = 0x1,
648         mux->shift = 24,
649         mux->reg = spicc->base + SPICC_ENH_CTL0;
650         mux->hw.init = &init;
651
652         spicc->clk = devm_clk_register(dev, &mux->hw);
653         if (WARN_ON(IS_ERR(spicc->clk)))
654                 return PTR_ERR(spicc->clk);
655
656         return 0;
657 }
658
659 static int meson_spicc_probe(struct platform_device *pdev)
660 {
661         struct spi_master *master;
662         struct meson_spicc_device *spicc;
663         int ret, irq;
664
665         master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
666         if (!master) {
667                 dev_err(&pdev->dev, "master allocation failed\n");
668                 return -ENOMEM;
669         }
670         spicc = spi_master_get_devdata(master);
671         spicc->master = master;
672
673         spicc->data = of_device_get_match_data(&pdev->dev);
674         if (!spicc->data) {
675                 dev_err(&pdev->dev, "failed to get match data\n");
676                 ret = -EINVAL;
677                 goto out_master;
678         }
679
680         spicc->pdev = pdev;
681         platform_set_drvdata(pdev, spicc);
682
683         spicc->base = devm_platform_ioremap_resource(pdev, 0);
684         if (IS_ERR(spicc->base)) {
685                 dev_err(&pdev->dev, "io resource mapping failed\n");
686                 ret = PTR_ERR(spicc->base);
687                 goto out_master;
688         }
689
690         /* Set master mode and enable controller */
691         writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
692                        spicc->base + SPICC_CONREG);
693
694         /* Disable all IRQs */
695         writel_relaxed(0, spicc->base + SPICC_INTREG);
696
697         irq = platform_get_irq(pdev, 0);
698         ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
699                                0, NULL, spicc);
700         if (ret) {
701                 dev_err(&pdev->dev, "irq request failed\n");
702                 goto out_master;
703         }
704
705         spicc->core = devm_clk_get(&pdev->dev, "core");
706         if (IS_ERR(spicc->core)) {
707                 dev_err(&pdev->dev, "core clock request failed\n");
708                 ret = PTR_ERR(spicc->core);
709                 goto out_master;
710         }
711
712         if (spicc->data->has_pclk) {
713                 spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
714                 if (IS_ERR(spicc->pclk)) {
715                         dev_err(&pdev->dev, "pclk clock request failed\n");
716                         ret = PTR_ERR(spicc->pclk);
717                         goto out_master;
718                 }
719         }
720
721         ret = clk_prepare_enable(spicc->core);
722         if (ret) {
723                 dev_err(&pdev->dev, "core clock enable failed\n");
724                 goto out_master;
725         }
726
727         ret = clk_prepare_enable(spicc->pclk);
728         if (ret) {
729                 dev_err(&pdev->dev, "pclk clock enable failed\n");
730                 goto out_master;
731         }
732
733         device_reset_optional(&pdev->dev);
734
735         master->num_chipselect = 4;
736         master->dev.of_node = pdev->dev.of_node;
737         master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
738         master->bits_per_word_mask = SPI_BPW_MASK(32) |
739                                      SPI_BPW_MASK(24) |
740                                      SPI_BPW_MASK(16) |
741                                      SPI_BPW_MASK(8);
742         master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
743         master->min_speed_hz = spicc->data->min_speed_hz;
744         master->max_speed_hz = spicc->data->max_speed_hz;
745         master->setup = meson_spicc_setup;
746         master->cleanup = meson_spicc_cleanup;
747         master->prepare_message = meson_spicc_prepare_message;
748         master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
749         master->transfer_one = meson_spicc_transfer_one;
750         master->use_gpio_descriptors = true;
751
752         meson_spicc_oen_enable(spicc);
753
754         ret = meson_spicc_clk_init(spicc);
755         if (ret) {
756                 dev_err(&pdev->dev, "clock registration failed\n");
757                 goto out_master;
758         }
759
760         ret = devm_spi_register_master(&pdev->dev, master);
761         if (ret) {
762                 dev_err(&pdev->dev, "spi master registration failed\n");
763                 goto out_clk;
764         }
765
766         return 0;
767
768 out_clk:
769         clk_disable_unprepare(spicc->core);
770         clk_disable_unprepare(spicc->pclk);
771
772 out_master:
773         spi_master_put(master);
774
775         return ret;
776 }
777
778 static int meson_spicc_remove(struct platform_device *pdev)
779 {
780         struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
781
782         /* Disable SPI */
783         writel(0, spicc->base + SPICC_CONREG);
784
785         clk_disable_unprepare(spicc->core);
786         clk_disable_unprepare(spicc->pclk);
787
788         return 0;
789 }
790
791 static const struct meson_spicc_data meson_spicc_gx_data = {
792         .max_speed_hz           = 30000000,
793         .min_speed_hz           = 325000,
794         .fifo_size              = 16,
795 };
796
797 static const struct meson_spicc_data meson_spicc_axg_data = {
798         .max_speed_hz           = 80000000,
799         .min_speed_hz           = 325000,
800         .fifo_size              = 16,
801         .has_oen                = true,
802         .has_enhance_clk_div    = true,
803 };
804
805 static const struct meson_spicc_data meson_spicc_g12a_data = {
806         .max_speed_hz           = 166666666,
807         .min_speed_hz           = 50000,
808         .fifo_size              = 15,
809         .has_oen                = true,
810         .has_enhance_clk_div    = true,
811         .has_pclk               = true,
812 };
813
814 static const struct of_device_id meson_spicc_of_match[] = {
815         {
816                 .compatible     = "amlogic,meson-gx-spicc",
817                 .data           = &meson_spicc_gx_data,
818         },
819         {
820                 .compatible = "amlogic,meson-axg-spicc",
821                 .data           = &meson_spicc_axg_data,
822         },
823         {
824                 .compatible = "amlogic,meson-g12a-spicc",
825                 .data           = &meson_spicc_g12a_data,
826         },
827         { /* sentinel */ }
828 };
829 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
830
831 static struct platform_driver meson_spicc_driver = {
832         .probe   = meson_spicc_probe,
833         .remove  = meson_spicc_remove,
834         .driver  = {
835                 .name = "meson-spicc",
836                 .of_match_table = of_match_ptr(meson_spicc_of_match),
837         },
838 };
839
840 module_platform_driver(meson_spicc_driver);
841
842 MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
843 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
844 MODULE_LICENSE("GPL");