2 * Driver for Amlogic Meson SPI communication controller (SPICC)
4 * Copyright (C) BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22 #include <linux/interrupt.h>
23 #include <linux/reset.h>
24 #include <linux/pinctrl/consumer.h>
27 * The Meson SPICC controller could support DMA based transfers, but is not
28 * implemented by the vendor code, and while having the registers documentation
29 * it has never worked on the GXL Hardware.
30 * The PIO mode is the only mode implemented, and due to badly designed HW :
31 * - all transfers are cutted in 16 words burst because the FIFO hangs on
32 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * FIFO max size chunk only
34 * - CS management is dumb, and goes UP between every burst, so is really a
35 * "Data Valid" signal than a Chip Select, GPIO link should be used instead
36 * to have a CS go down over the full transfer
39 #define SPICC_MAX_BURST 128
42 #define SPICC_RXDATA 0x00
44 #define SPICC_TXDATA 0x04
46 #define SPICC_CONREG 0x08
47 #define SPICC_ENABLE BIT(0)
48 #define SPICC_MODE_MASTER BIT(1)
49 #define SPICC_XCH BIT(2)
50 #define SPICC_SMC BIT(3)
51 #define SPICC_POL BIT(4)
52 #define SPICC_PHA BIT(5)
53 #define SPICC_SSCTL BIT(6)
54 #define SPICC_SSPOL BIT(7)
55 #define SPICC_DRCTL_MASK GENMASK(9, 8)
56 #define SPICC_DRCTL_IGNORE 0
57 #define SPICC_DRCTL_FALLING 1
58 #define SPICC_DRCTL_LOWLEVEL 2
59 #define SPICC_CS_MASK GENMASK(13, 12)
60 #define SPICC_DATARATE_MASK GENMASK(18, 16)
61 #define SPICC_DATARATE_DIV4 0
62 #define SPICC_DATARATE_DIV8 1
63 #define SPICC_DATARATE_DIV16 2
64 #define SPICC_DATARATE_DIV32 3
65 #define SPICC_BITLENGTH_MASK GENMASK(24, 19)
66 #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
68 #define SPICC_INTREG 0x0c
69 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
70 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
71 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
72 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
73 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
74 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
75 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
76 #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
78 #define SPICC_DMAREG 0x10
79 #define SPICC_DMA_ENABLE BIT(0)
80 #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
81 #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
82 #define SPICC_READ_BURST_MASK GENMASK(14, 11)
83 #define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
84 #define SPICC_DMA_URGENT BIT(19)
85 #define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
86 #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
88 #define SPICC_STATREG 0x14
89 #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
90 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
91 #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
92 #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
93 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
94 #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
95 #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
96 #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
98 #define SPICC_PERIODREG 0x18
99 #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
101 #define SPICC_TESTREG 0x1c
102 #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
103 #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
104 #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
105 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
106 #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
107 #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
108 #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
109 #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
110 #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
111 #define SPICC_MO_NO_DELAY 0
112 #define SPICC_MO_DELAY_1_CYCLE 1
113 #define SPICC_MO_DELAY_2_CYCLE 2
114 #define SPICC_MO_DELAY_3_CYCLE 3
115 #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
116 #define SPICC_MI_NO_DELAY 0
117 #define SPICC_MI_DELAY_1_CYCLE 1
118 #define SPICC_MI_DELAY_2_CYCLE 2
119 #define SPICC_MI_DELAY_3_CYCLE 3
120 #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
121 #define SPICC_CAP_AHEAD_2_CYCLE 0
122 #define SPICC_CAP_AHEAD_1_CYCLE 1
123 #define SPICC_CAP_NO_DELAY 2
124 #define SPICC_CAP_DELAY_1_CYCLE 3
125 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
126 #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
128 #define SPICC_DRADDR 0x20 /* Read Address of DMA */
130 #define SPICC_DWADDR 0x24 /* Write Address of DMA */
132 #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
133 #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
134 #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
135 #define SPICC_ENH_DATARATE_EN BIT(24)
136 #define SPICC_ENH_MOSI_OEN BIT(25)
137 #define SPICC_ENH_CLK_OEN BIT(26)
138 #define SPICC_ENH_CS_OEN BIT(27)
139 #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
140 #define SPICC_ENH_MAIN_CLK_AO BIT(29)
142 #define writel_bits_relaxed(mask, val, addr) \
143 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
145 struct meson_spicc_data {
146 unsigned int max_speed_hz;
147 unsigned int min_speed_hz;
148 unsigned int fifo_size;
150 bool has_enhance_clk_div;
154 struct meson_spicc_device {
155 struct spi_master *master;
156 struct platform_device *pdev;
160 struct clk_divider pow2_div;
162 struct spi_message *message;
163 struct spi_transfer *xfer;
164 struct completion done;
165 const struct meson_spicc_data *data;
168 unsigned int bytes_per_word;
169 unsigned long tx_remain;
170 unsigned long rx_remain;
171 unsigned long xfer_remain;
172 struct pinctrl *pinctrl;
173 struct pinctrl_state *pins_idle_high;
174 struct pinctrl_state *pins_idle_low;
177 #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
179 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
183 if (!spicc->data->has_oen) {
184 /* Try to get pinctrl states for idle high/low */
185 spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl,
187 if (IS_ERR(spicc->pins_idle_high)) {
188 dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n");
189 spicc->pins_idle_high = NULL;
191 spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl,
193 if (IS_ERR(spicc->pins_idle_low)) {
194 dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n");
195 spicc->pins_idle_low = NULL;
200 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
201 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
203 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
206 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
208 return !!FIELD_GET(SPICC_TF,
209 readl_relaxed(spicc->base + SPICC_STATREG));
212 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
214 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
215 readl_relaxed(spicc->base + SPICC_STATREG));
218 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
220 unsigned int bytes = spicc->bytes_per_word;
221 unsigned int byte_shift = 0;
226 byte = *spicc->tx_buf++;
227 data |= (byte & 0xff) << byte_shift;
235 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
238 unsigned int bytes = spicc->bytes_per_word;
239 unsigned int byte_shift = 0;
243 byte = (data >> byte_shift) & 0xff;
244 *spicc->rx_buf++ = byte;
251 static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
254 while (spicc->rx_remain &&
255 meson_spicc_rxready(spicc))
256 meson_spicc_push_data(spicc,
257 readl_relaxed(spicc->base + SPICC_RXDATA));
260 static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
262 /* Fill Up TX FIFO */
263 while (spicc->tx_remain &&
264 !meson_spicc_txfull(spicc))
265 writel_relaxed(meson_spicc_pull_data(spicc),
266 spicc->base + SPICC_TXDATA);
269 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
272 unsigned int burst_len = min_t(unsigned int,
274 spicc->bytes_per_word,
275 spicc->data->fifo_size);
276 /* Setup Xfer variables */
277 spicc->tx_remain = burst_len;
278 spicc->rx_remain = burst_len;
279 spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
281 /* Setup burst length */
282 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
283 FIELD_PREP(SPICC_BURSTLENGTH_MASK,
285 spicc->base + SPICC_CONREG);
288 meson_spicc_tx(spicc);
291 static irqreturn_t meson_spicc_irq(int irq, void *data)
293 struct meson_spicc_device *spicc = (void *) data;
295 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
298 meson_spicc_rx(spicc);
300 if (!spicc->xfer_remain) {
301 /* Disable all IRQs */
302 writel(0, spicc->base + SPICC_INTREG);
304 complete(&spicc->done);
310 meson_spicc_setup_burst(spicc);
313 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
318 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
321 u32 mi_delay, cap_delay;
324 if (spicc->data->has_enhance_clk_div) {
325 div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
326 readl_relaxed(spicc->base + SPICC_ENH_CTL0));
330 div = FIELD_GET(SPICC_DATARATE_MASK,
331 readl_relaxed(spicc->base + SPICC_CONREG));
336 mi_delay = SPICC_MI_NO_DELAY;
337 cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
338 hz = clk_get_rate(spicc->clk);
341 cap_delay = SPICC_CAP_DELAY_1_CYCLE;
342 else if (hz >= 80000000)
343 cap_delay = SPICC_CAP_NO_DELAY;
344 else if (hz >= 40000000)
345 cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
347 mi_delay = SPICC_MI_DELAY_3_CYCLE;
349 mi_delay = SPICC_MI_DELAY_2_CYCLE;
351 mi_delay = SPICC_MI_DELAY_1_CYCLE;
353 conf = readl_relaxed(spicc->base + SPICC_TESTREG);
354 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
355 | SPICC_MI_CAP_DELAY_MASK);
356 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
357 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
358 writel_relaxed(conf, spicc->base + SPICC_TESTREG);
361 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
362 struct spi_transfer *xfer)
366 /* Read original configuration */
367 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
369 /* Setup word width */
370 conf &= ~SPICC_BITLENGTH_MASK;
371 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
372 (spicc->bytes_per_word << 3) - 1);
374 /* Ignore if unchanged */
375 if (conf != conf_orig)
376 writel_relaxed(conf, spicc->base + SPICC_CONREG);
378 clk_set_rate(spicc->clk, xfer->speed_hz);
380 meson_spicc_auto_io_delay(spicc);
382 writel_relaxed(0, spicc->base + SPICC_DMAREG);
385 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
387 if (spicc->data->has_oen)
388 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
389 SPICC_ENH_MAIN_CLK_AO,
390 spicc->base + SPICC_ENH_CTL0);
392 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
393 spicc->base + SPICC_TESTREG);
395 while (meson_spicc_rxready(spicc))
396 readl_relaxed(spicc->base + SPICC_RXDATA);
398 if (spicc->data->has_oen)
399 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
400 spicc->base + SPICC_ENH_CTL0);
403 static int meson_spicc_transfer_one(struct spi_master *master,
404 struct spi_device *spi,
405 struct spi_transfer *xfer)
407 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
410 /* Store current transfer */
413 /* Setup transfer parameters */
414 spicc->tx_buf = (u8 *)xfer->tx_buf;
415 spicc->rx_buf = (u8 *)xfer->rx_buf;
416 spicc->xfer_remain = xfer->len;
418 /* Pre-calculate word size */
419 spicc->bytes_per_word =
420 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
422 if (xfer->len % spicc->bytes_per_word)
425 /* Setup transfer parameters */
426 meson_spicc_setup_xfer(spicc, xfer);
428 meson_spicc_reset_fifo(spicc);
431 meson_spicc_setup_burst(spicc);
433 /* Setup wait for completion */
434 reinit_completion(&spicc->done);
436 /* For each byte we wait for 8 cycles of the SPI clock */
437 timeout = 8LL * MSEC_PER_SEC * xfer->len;
438 do_div(timeout, xfer->speed_hz);
440 /* Add 10us delay between each fifo bursts */
441 timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;
443 /* Increase it twice and add 200 ms tolerance */
444 timeout += timeout + 200;
447 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
449 /* Enable interrupts */
450 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
452 if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))
458 static int meson_spicc_prepare_message(struct spi_master *master,
459 struct spi_message *message)
461 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
462 struct spi_device *spi = message->spi;
463 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
465 /* Store current message */
466 spicc->message = message;
469 conf |= SPICC_ENABLE;
470 conf |= SPICC_MODE_MASTER;
474 /* Setup transfer mode */
475 if (spi->mode & SPI_CPOL)
480 if (!spicc->data->has_oen) {
481 if (spi->mode & SPI_CPOL) {
482 if (spicc->pins_idle_high)
483 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high);
485 if (spicc->pins_idle_low)
486 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low);
490 if (spi->mode & SPI_CPHA)
497 if (spi->mode & SPI_CS_HIGH)
500 conf &= ~SPICC_SSPOL;
502 if (spi->mode & SPI_READY)
503 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
505 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
508 conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0));
510 /* Default 8bit word */
511 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
513 writel_relaxed(conf, spicc->base + SPICC_CONREG);
515 /* Setup no wait cycles by default */
516 writel_relaxed(0, spicc->base + SPICC_PERIODREG);
518 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
523 static int meson_spicc_unprepare_transfer(struct spi_master *master)
525 struct meson_spicc_device *spicc = spi_master_get_devdata(master);
526 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
528 /* Disable all IRQs */
529 writel(0, spicc->base + SPICC_INTREG);
531 device_reset_optional(&spicc->pdev->dev);
533 /* Set default configuration, keeping datarate field */
534 writel_relaxed(conf, spicc->base + SPICC_CONREG);
536 if (!spicc->data->has_oen)
537 pinctrl_select_default_state(&spicc->pdev->dev);
542 static int meson_spicc_setup(struct spi_device *spi)
544 if (!spi->controller_state)
545 spi->controller_state = spi_master_get_devdata(spi->master);
550 static void meson_spicc_cleanup(struct spi_device *spi)
552 spi->controller_state = NULL;
557 * x-----------------x x------------x x------\
558 * |---| pow2 fixed div |---| pow2 div |----| |
559 * | x-----------------x x------------x | |
560 * src ---| | mux |-- out
561 * | x-----------------x x------------x | |
562 * |---| enh fixed div |---| enh div |0---| |
563 * x-----------------x x------------x x------/
565 * Clk path for GX series:
566 * src -> pow2 fixed div -> pow2 div -> out
568 * Clk path for AXG series:
569 * src -> pow2 fixed div -> pow2 div -> mux -> out
570 * src -> enh fixed div -> enh div -> mux -> out
572 * Clk path for G12A series:
573 * pclk -> pow2 fixed div -> pow2 div -> mux -> out
574 * pclk -> enh fixed div -> enh div -> mux -> out
576 * The pow2 divider is tied to the controller HW state, and the
577 * divider is only valid when the controller is initialized.
579 * A set of clock ops is added to make sure we don't read/set this
580 * clock rate while the controller is in an unknown state.
583 static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
584 unsigned long parent_rate)
586 struct clk_divider *divider = to_clk_divider(hw);
587 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
589 if (!spicc->master->cur_msg)
592 return clk_divider_ops.recalc_rate(hw, parent_rate);
595 static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
596 struct clk_rate_request *req)
598 struct clk_divider *divider = to_clk_divider(hw);
599 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
601 if (!spicc->master->cur_msg)
604 return clk_divider_ops.determine_rate(hw, req);
607 static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
608 unsigned long parent_rate)
610 struct clk_divider *divider = to_clk_divider(hw);
611 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
613 if (!spicc->master->cur_msg)
616 return clk_divider_ops.set_rate(hw, rate, parent_rate);
619 static const struct clk_ops meson_spicc_pow2_clk_ops = {
620 .recalc_rate = meson_spicc_pow2_recalc_rate,
621 .determine_rate = meson_spicc_pow2_determine_rate,
622 .set_rate = meson_spicc_pow2_set_rate,
625 static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
627 struct device *dev = &spicc->pdev->dev;
628 struct clk_fixed_factor *pow2_fixed_div;
629 struct clk_init_data init;
631 struct clk_parent_data parent_data[2];
634 memset(&init, 0, sizeof(init));
635 memset(&parent_data, 0, sizeof(parent_data));
637 init.parent_data = parent_data;
639 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
641 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
645 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
647 init.ops = &clk_fixed_factor_ops;
649 if (spicc->data->has_pclk)
650 parent_data[0].hw = __clk_get_hw(spicc->pclk);
652 parent_data[0].hw = __clk_get_hw(spicc->core);
653 init.num_parents = 1;
655 pow2_fixed_div->mult = 1,
656 pow2_fixed_div->div = 4,
657 pow2_fixed_div->hw.init = &init;
659 clk = devm_clk_register(dev, &pow2_fixed_div->hw);
660 if (WARN_ON(IS_ERR(clk)))
663 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
665 init.ops = &meson_spicc_pow2_clk_ops;
667 * Set NOCACHE here to make sure we read the actual HW value
668 * since we reset the HW after each transfer.
670 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
671 parent_data[0].hw = &pow2_fixed_div->hw;
672 init.num_parents = 1;
674 spicc->pow2_div.shift = 16,
675 spicc->pow2_div.width = 3,
676 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO,
677 spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
678 spicc->pow2_div.hw.init = &init;
680 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
681 if (WARN_ON(IS_ERR(spicc->clk)))
682 return PTR_ERR(spicc->clk);
687 static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
689 struct device *dev = &spicc->pdev->dev;
690 struct clk_fixed_factor *enh_fixed_div;
691 struct clk_divider *enh_div;
693 struct clk_init_data init;
695 struct clk_parent_data parent_data[2];
698 memset(&init, 0, sizeof(init));
699 memset(&parent_data, 0, sizeof(parent_data));
701 init.parent_data = parent_data;
703 /* algorithm for enh div: rate = freq / 2 / (N + 1) */
705 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
709 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
711 init.ops = &clk_fixed_factor_ops;
713 if (spicc->data->has_pclk)
714 parent_data[0].hw = __clk_get_hw(spicc->pclk);
716 parent_data[0].hw = __clk_get_hw(spicc->core);
717 init.num_parents = 1;
719 enh_fixed_div->mult = 1,
720 enh_fixed_div->div = 2,
721 enh_fixed_div->hw.init = &init;
723 clk = devm_clk_register(dev, &enh_fixed_div->hw);
724 if (WARN_ON(IS_ERR(clk)))
727 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
731 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
733 init.ops = &clk_divider_ops;
734 init.flags = CLK_SET_RATE_PARENT;
735 parent_data[0].hw = &enh_fixed_div->hw;
736 init.num_parents = 1;
740 enh_div->reg = spicc->base + SPICC_ENH_CTL0;
741 enh_div->hw.init = &init;
743 clk = devm_clk_register(dev, &enh_div->hw);
744 if (WARN_ON(IS_ERR(clk)))
747 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
751 snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
753 init.ops = &clk_mux_ops;
754 parent_data[0].hw = &spicc->pow2_div.hw;
755 parent_data[1].hw = &enh_div->hw;
756 init.num_parents = 2;
757 init.flags = CLK_SET_RATE_PARENT;
761 mux->reg = spicc->base + SPICC_ENH_CTL0;
762 mux->hw.init = &init;
764 spicc->clk = devm_clk_register(dev, &mux->hw);
765 if (WARN_ON(IS_ERR(spicc->clk)))
766 return PTR_ERR(spicc->clk);
771 static int meson_spicc_probe(struct platform_device *pdev)
773 struct spi_master *master;
774 struct meson_spicc_device *spicc;
777 master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
779 dev_err(&pdev->dev, "master allocation failed\n");
782 spicc = spi_master_get_devdata(master);
783 spicc->master = master;
785 spicc->data = of_device_get_match_data(&pdev->dev);
787 dev_err(&pdev->dev, "failed to get match data\n");
793 platform_set_drvdata(pdev, spicc);
795 init_completion(&spicc->done);
797 spicc->base = devm_platform_ioremap_resource(pdev, 0);
798 if (IS_ERR(spicc->base)) {
799 dev_err(&pdev->dev, "io resource mapping failed\n");
800 ret = PTR_ERR(spicc->base);
804 /* Set master mode and enable controller */
805 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
806 spicc->base + SPICC_CONREG);
808 /* Disable all IRQs */
809 writel_relaxed(0, spicc->base + SPICC_INTREG);
811 irq = platform_get_irq(pdev, 0);
817 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
820 dev_err(&pdev->dev, "irq request failed\n");
824 spicc->core = devm_clk_get(&pdev->dev, "core");
825 if (IS_ERR(spicc->core)) {
826 dev_err(&pdev->dev, "core clock request failed\n");
827 ret = PTR_ERR(spicc->core);
831 if (spicc->data->has_pclk) {
832 spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
833 if (IS_ERR(spicc->pclk)) {
834 dev_err(&pdev->dev, "pclk clock request failed\n");
835 ret = PTR_ERR(spicc->pclk);
840 ret = clk_prepare_enable(spicc->core);
842 dev_err(&pdev->dev, "core clock enable failed\n");
846 ret = clk_prepare_enable(spicc->pclk);
848 dev_err(&pdev->dev, "pclk clock enable failed\n");
852 spicc->pinctrl = devm_pinctrl_get(&pdev->dev);
853 if (IS_ERR(spicc->pinctrl)) {
854 ret = PTR_ERR(spicc->pinctrl);
858 device_reset_optional(&pdev->dev);
860 master->num_chipselect = 4;
861 master->dev.of_node = pdev->dev.of_node;
862 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
863 master->bits_per_word_mask = SPI_BPW_MASK(32) |
867 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
868 master->min_speed_hz = spicc->data->min_speed_hz;
869 master->max_speed_hz = spicc->data->max_speed_hz;
870 master->setup = meson_spicc_setup;
871 master->cleanup = meson_spicc_cleanup;
872 master->prepare_message = meson_spicc_prepare_message;
873 master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
874 master->transfer_one = meson_spicc_transfer_one;
875 master->use_gpio_descriptors = true;
877 meson_spicc_oen_enable(spicc);
879 ret = meson_spicc_pow2_clk_init(spicc);
881 dev_err(&pdev->dev, "pow2 clock registration failed\n");
885 if (spicc->data->has_enhance_clk_div) {
886 ret = meson_spicc_enh_clk_init(spicc);
888 dev_err(&pdev->dev, "clock registration failed\n");
893 ret = devm_spi_register_master(&pdev->dev, master);
895 dev_err(&pdev->dev, "spi master registration failed\n");
902 clk_disable_unprepare(spicc->pclk);
905 clk_disable_unprepare(spicc->core);
908 spi_master_put(master);
913 static void meson_spicc_remove(struct platform_device *pdev)
915 struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
918 writel(0, spicc->base + SPICC_CONREG);
920 clk_disable_unprepare(spicc->core);
921 clk_disable_unprepare(spicc->pclk);
923 spi_master_put(spicc->master);
926 static const struct meson_spicc_data meson_spicc_gx_data = {
927 .max_speed_hz = 30000000,
928 .min_speed_hz = 325000,
932 static const struct meson_spicc_data meson_spicc_axg_data = {
933 .max_speed_hz = 80000000,
934 .min_speed_hz = 325000,
937 .has_enhance_clk_div = true,
940 static const struct meson_spicc_data meson_spicc_g12a_data = {
941 .max_speed_hz = 166666666,
942 .min_speed_hz = 50000,
945 .has_enhance_clk_div = true,
949 static const struct of_device_id meson_spicc_of_match[] = {
951 .compatible = "amlogic,meson-gx-spicc",
952 .data = &meson_spicc_gx_data,
955 .compatible = "amlogic,meson-axg-spicc",
956 .data = &meson_spicc_axg_data,
959 .compatible = "amlogic,meson-g12a-spicc",
960 .data = &meson_spicc_g12a_data,
964 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
966 static struct platform_driver meson_spicc_driver = {
967 .probe = meson_spicc_probe,
968 .remove_new = meson_spicc_remove,
970 .name = "meson-spicc",
971 .of_match_table = of_match_ptr(meson_spicc_of_match),
975 module_platform_driver(meson_spicc_driver);
977 MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
978 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
979 MODULE_LICENSE("GPL");