1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_bitbang.h>
21 #include <linux/types.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
26 #include <linux/platform_data/dma-imx.h>
27 #include <linux/platform_data/spi-imx.h>
29 #define DRIVER_NAME "spi_imx"
31 static bool use_dma = true;
32 module_param(use_dma, bool, 0644);
33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
35 #define MXC_CSPIRXDATA 0x00
36 #define MXC_CSPITXDATA 0x04
37 #define MXC_CSPICTRL 0x08
38 #define MXC_CSPIINT 0x0c
39 #define MXC_RESET 0x1c
41 /* generic defines to abstract from the different register layouts */
42 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
43 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
44 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
46 /* The maximum bytes that a sdma BD can transfer. */
47 #define MAX_SDMA_BD_BYTES (1 << 15)
48 #define MX51_ECSPI_CTRL_MAX_BURST 512
49 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
50 #define MX53_MAX_TRANSFER_BYTES 512
52 enum spi_imx_devtype {
57 IMX35_CSPI, /* CSPI on all i.mx except above */
58 IMX51_ECSPI, /* ECSPI on i.mx51 */
59 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
64 struct spi_imx_devtype_data {
65 void (*intctrl)(struct spi_imx_data *, int);
66 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
67 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *,
68 struct spi_transfer *);
69 void (*trigger)(struct spi_imx_data *);
70 int (*rx_available)(struct spi_imx_data *);
71 void (*reset)(struct spi_imx_data *);
72 void (*setup_wml)(struct spi_imx_data *);
73 void (*disable)(struct spi_imx_data *);
74 void (*disable_dma)(struct spi_imx_data *);
77 unsigned int fifo_size;
79 enum spi_imx_devtype devtype;
83 struct spi_bitbang bitbang;
86 struct completion xfer_done;
88 unsigned long base_phys;
92 unsigned long spi_clk;
93 unsigned int spi_bus_clk;
95 unsigned int bits_per_word;
96 unsigned int spi_drctl;
98 unsigned int count, remainder;
99 void (*tx)(struct spi_imx_data *);
100 void (*rx)(struct spi_imx_data *);
103 unsigned int txfifo; /* number of words pushed in tx FIFO */
104 unsigned int dynamic_burst;
109 unsigned int slave_burst;
114 struct completion dma_rx_completion;
115 struct completion dma_tx_completion;
117 const struct spi_imx_devtype_data *devtype_data;
120 static inline int is_imx27_cspi(struct spi_imx_data *d)
122 return d->devtype_data->devtype == IMX27_CSPI;
125 static inline int is_imx35_cspi(struct spi_imx_data *d)
127 return d->devtype_data->devtype == IMX35_CSPI;
130 static inline int is_imx51_ecspi(struct spi_imx_data *d)
132 return d->devtype_data->devtype == IMX51_ECSPI;
135 static inline int is_imx53_ecspi(struct spi_imx_data *d)
137 return d->devtype_data->devtype == IMX53_ECSPI;
140 #define MXC_SPI_BUF_RX(type) \
141 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
143 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
145 if (spi_imx->rx_buf) { \
146 *(type *)spi_imx->rx_buf = val; \
147 spi_imx->rx_buf += sizeof(type); \
150 spi_imx->remainder -= sizeof(type); \
153 #define MXC_SPI_BUF_TX(type) \
154 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
158 if (spi_imx->tx_buf) { \
159 val = *(type *)spi_imx->tx_buf; \
160 spi_imx->tx_buf += sizeof(type); \
163 spi_imx->count -= sizeof(type); \
165 writel(val, spi_imx->base + MXC_CSPITXDATA); \
175 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
176 * (which is currently not the case in this driver)
178 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
179 256, 384, 512, 768, 1024};
182 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
183 unsigned int fspi, unsigned int max, unsigned int *fres)
187 for (i = 2; i < max; i++)
188 if (fspi * mxc_clkdivs[i] >= fin)
191 *fres = fin / mxc_clkdivs[i];
195 /* MX1, MX31, MX35, MX51 CSPI */
196 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
197 unsigned int fspi, unsigned int *fres)
201 for (i = 0; i < 7; i++) {
202 if (fspi * div >= fin)
212 static int spi_imx_bytes_per_word(const int bits_per_word)
214 if (bits_per_word <= 8)
216 else if (bits_per_word <= 16)
222 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
223 struct spi_transfer *transfer)
225 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
233 if (spi_imx->slave_mode)
236 if (transfer->len < spi_imx->devtype_data->fifo_size)
239 spi_imx->dynamic_burst = 0;
244 #define MX51_ECSPI_CTRL 0x08
245 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
246 #define MX51_ECSPI_CTRL_XCH (1 << 2)
247 #define MX51_ECSPI_CTRL_SMC (1 << 3)
248 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
249 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
250 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
251 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
252 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
253 #define MX51_ECSPI_CTRL_BL_OFFSET 20
254 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
256 #define MX51_ECSPI_CONFIG 0x0c
257 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
258 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
259 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
260 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
261 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
263 #define MX51_ECSPI_INT 0x10
264 #define MX51_ECSPI_INT_TEEN (1 << 0)
265 #define MX51_ECSPI_INT_RREN (1 << 3)
266 #define MX51_ECSPI_INT_RDREN (1 << 4)
268 #define MX51_ECSPI_DMA 0x14
269 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
270 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
271 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
273 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
274 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
275 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
277 #define MX51_ECSPI_STAT 0x18
278 #define MX51_ECSPI_STAT_RR (1 << 3)
280 #define MX51_ECSPI_TESTREG 0x20
281 #define MX51_ECSPI_TESTREG_LBC BIT(31)
283 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
285 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
286 #ifdef __LITTLE_ENDIAN
287 unsigned int bytes_per_word;
290 if (spi_imx->rx_buf) {
291 #ifdef __LITTLE_ENDIAN
292 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
293 if (bytes_per_word == 1)
294 val = cpu_to_be32(val);
295 else if (bytes_per_word == 2)
296 val = (val << 16) | (val >> 16);
298 *(u32 *)spi_imx->rx_buf = val;
299 spi_imx->rx_buf += sizeof(u32);
302 spi_imx->remainder -= sizeof(u32);
305 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
310 unaligned = spi_imx->remainder % 4;
313 spi_imx_buf_rx_swap_u32(spi_imx);
317 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
318 spi_imx_buf_rx_u16(spi_imx);
322 val = readl(spi_imx->base + MXC_CSPIRXDATA);
324 while (unaligned--) {
325 if (spi_imx->rx_buf) {
326 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
329 spi_imx->remainder--;
333 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
336 #ifdef __LITTLE_ENDIAN
337 unsigned int bytes_per_word;
340 if (spi_imx->tx_buf) {
341 val = *(u32 *)spi_imx->tx_buf;
342 spi_imx->tx_buf += sizeof(u32);
345 spi_imx->count -= sizeof(u32);
346 #ifdef __LITTLE_ENDIAN
347 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
349 if (bytes_per_word == 1)
350 val = cpu_to_be32(val);
351 else if (bytes_per_word == 2)
352 val = (val << 16) | (val >> 16);
354 writel(val, spi_imx->base + MXC_CSPITXDATA);
357 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
362 unaligned = spi_imx->count % 4;
365 spi_imx_buf_tx_swap_u32(spi_imx);
369 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
370 spi_imx_buf_tx_u16(spi_imx);
374 while (unaligned--) {
375 if (spi_imx->tx_buf) {
376 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
382 writel(val, spi_imx->base + MXC_CSPITXDATA);
385 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
387 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
389 if (spi_imx->rx_buf) {
390 int n_bytes = spi_imx->slave_burst % sizeof(val);
393 n_bytes = sizeof(val);
395 memcpy(spi_imx->rx_buf,
396 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
398 spi_imx->rx_buf += n_bytes;
399 spi_imx->slave_burst -= n_bytes;
402 spi_imx->remainder -= sizeof(u32);
405 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
408 int n_bytes = spi_imx->count % sizeof(val);
411 n_bytes = sizeof(val);
413 if (spi_imx->tx_buf) {
414 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
415 spi_imx->tx_buf, n_bytes);
416 val = cpu_to_be32(val);
417 spi_imx->tx_buf += n_bytes;
420 spi_imx->count -= n_bytes;
422 writel(val, spi_imx->base + MXC_CSPITXDATA);
426 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
427 unsigned int fspi, unsigned int *fres)
430 * there are two 4-bit dividers, the pre-divider divides by
431 * $pre, the post-divider by 2^$post
433 unsigned int pre, post;
434 unsigned int fin = spi_imx->spi_clk;
436 if (unlikely(fspi > fin))
439 post = fls(fin) - fls(fspi);
440 if (fin > fspi << post)
443 /* now we have: (fin <= fspi << post) with post being minimal */
445 post = max(4U, post) - 4;
446 if (unlikely(post > 0xf)) {
447 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
452 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
454 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
455 __func__, fin, fspi, post, pre);
457 /* Resulting frequency for the SCLK line. */
458 *fres = (fin / (pre + 1)) >> post;
460 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
461 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
464 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
468 if (enable & MXC_INT_TE)
469 val |= MX51_ECSPI_INT_TEEN;
471 if (enable & MXC_INT_RR)
472 val |= MX51_ECSPI_INT_RREN;
474 if (enable & MXC_INT_RDR)
475 val |= MX51_ECSPI_INT_RDREN;
477 writel(val, spi_imx->base + MX51_ECSPI_INT);
480 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
484 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
485 reg |= MX51_ECSPI_CTRL_XCH;
486 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
489 static void mx51_disable_dma(struct spi_imx_data *spi_imx)
491 writel(0, spi_imx->base + MX51_ECSPI_DMA);
494 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
498 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
499 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
500 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
503 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
504 struct spi_message *msg)
506 struct spi_device *spi = msg->spi;
507 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
509 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
511 /* set Master or Slave mode */
512 if (spi_imx->slave_mode)
513 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
515 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
518 * Enable SPI_RDY handling (falling edge/level triggered).
520 if (spi->mode & SPI_READY)
521 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
523 /* set chip select to use */
524 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
527 * The ctrl register must be written first, with the EN bit set other
528 * registers must not be written to.
530 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
532 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
533 if (spi->mode & SPI_LOOP)
534 testreg |= MX51_ECSPI_TESTREG_LBC;
536 testreg &= ~MX51_ECSPI_TESTREG_LBC;
537 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
540 * eCSPI burst completion by Chip Select signal in Slave mode
541 * is not functional for imx53 Soc, config SPI burst completed when
542 * BURST_LENGTH + 1 bits are received
544 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
545 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
547 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
549 if (spi->mode & SPI_CPHA)
550 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
552 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
554 if (spi->mode & SPI_CPOL) {
555 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
556 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
558 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
559 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
562 if (spi->mode & SPI_CS_HIGH)
563 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
565 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
567 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
572 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
573 struct spi_device *spi,
574 struct spi_transfer *t)
576 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
577 u32 clk = t->speed_hz, delay;
579 /* Clear BL field and set the right value */
580 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
581 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
582 ctrl |= (spi_imx->slave_burst * 8 - 1)
583 << MX51_ECSPI_CTRL_BL_OFFSET;
585 ctrl |= (spi_imx->bits_per_word - 1)
586 << MX51_ECSPI_CTRL_BL_OFFSET;
588 /* set clock speed */
589 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
590 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
591 ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
592 spi_imx->spi_bus_clk = clk;
595 ctrl |= MX51_ECSPI_CTRL_SMC;
597 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
600 * Wait until the changes in the configuration register CONFIGREG
601 * propagate into the hardware. It takes exactly one tick of the
602 * SCLK clock, but we will wait two SCLK clock just to be sure. The
603 * effect of the delay it takes for the hardware to apply changes
604 * is noticable if the SCLK clock run very slow. In such a case, if
605 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
606 * be asserted before the SCLK polarity changes, which would disrupt
607 * the SPI communication as the device on the other end would consider
608 * the change of SCLK polarity as a clock tick already.
610 delay = (2 * 1000000) / clk;
611 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
613 else /* SCLK is _very_ slow */
614 usleep_range(delay, delay + 10);
619 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
622 * Configure the DMA register: setup the watermark
623 * and enable DMA request.
625 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
626 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
627 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
628 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
629 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
632 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
634 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
637 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
639 /* drain receive buffer */
640 while (mx51_ecspi_rx_available(spi_imx))
641 readl(spi_imx->base + MXC_CSPIRXDATA);
644 #define MX31_INTREG_TEEN (1 << 0)
645 #define MX31_INTREG_RREN (1 << 3)
647 #define MX31_CSPICTRL_ENABLE (1 << 0)
648 #define MX31_CSPICTRL_MASTER (1 << 1)
649 #define MX31_CSPICTRL_XCH (1 << 2)
650 #define MX31_CSPICTRL_SMC (1 << 3)
651 #define MX31_CSPICTRL_POL (1 << 4)
652 #define MX31_CSPICTRL_PHA (1 << 5)
653 #define MX31_CSPICTRL_SSCTL (1 << 6)
654 #define MX31_CSPICTRL_SSPOL (1 << 7)
655 #define MX31_CSPICTRL_BC_SHIFT 8
656 #define MX35_CSPICTRL_BL_SHIFT 20
657 #define MX31_CSPICTRL_CS_SHIFT 24
658 #define MX35_CSPICTRL_CS_SHIFT 12
659 #define MX31_CSPICTRL_DR_SHIFT 16
661 #define MX31_CSPI_DMAREG 0x10
662 #define MX31_DMAREG_RH_DEN (1<<4)
663 #define MX31_DMAREG_TH_DEN (1<<1)
665 #define MX31_CSPISTATUS 0x14
666 #define MX31_STATUS_RR (1 << 3)
668 #define MX31_CSPI_TESTREG 0x1C
669 #define MX31_TEST_LBC (1 << 14)
671 /* These functions also work for the i.MX35, but be aware that
672 * the i.MX35 has a slightly different register layout for bits
673 * we do not use here.
675 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
677 unsigned int val = 0;
679 if (enable & MXC_INT_TE)
680 val |= MX31_INTREG_TEEN;
681 if (enable & MXC_INT_RR)
682 val |= MX31_INTREG_RREN;
684 writel(val, spi_imx->base + MXC_CSPIINT);
687 static void mx31_trigger(struct spi_imx_data *spi_imx)
691 reg = readl(spi_imx->base + MXC_CSPICTRL);
692 reg |= MX31_CSPICTRL_XCH;
693 writel(reg, spi_imx->base + MXC_CSPICTRL);
696 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
697 struct spi_message *msg)
702 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
703 struct spi_device *spi,
704 struct spi_transfer *t)
706 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
709 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
710 MX31_CSPICTRL_DR_SHIFT;
711 spi_imx->spi_bus_clk = clk;
713 if (is_imx35_cspi(spi_imx)) {
714 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
715 reg |= MX31_CSPICTRL_SSCTL;
717 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
720 if (spi->mode & SPI_CPHA)
721 reg |= MX31_CSPICTRL_PHA;
722 if (spi->mode & SPI_CPOL)
723 reg |= MX31_CSPICTRL_POL;
724 if (spi->mode & SPI_CS_HIGH)
725 reg |= MX31_CSPICTRL_SSPOL;
726 if (!gpio_is_valid(spi->cs_gpio))
727 reg |= (spi->chip_select) <<
728 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
729 MX31_CSPICTRL_CS_SHIFT);
732 reg |= MX31_CSPICTRL_SMC;
734 writel(reg, spi_imx->base + MXC_CSPICTRL);
736 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
737 if (spi->mode & SPI_LOOP)
738 reg |= MX31_TEST_LBC;
740 reg &= ~MX31_TEST_LBC;
741 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
743 if (spi_imx->usedma) {
745 * configure DMA requests when RXFIFO is half full and
746 * when TXFIFO is half empty
748 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
749 spi_imx->base + MX31_CSPI_DMAREG);
755 static int mx31_rx_available(struct spi_imx_data *spi_imx)
757 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
760 static void mx31_reset(struct spi_imx_data *spi_imx)
762 /* drain receive buffer */
763 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
764 readl(spi_imx->base + MXC_CSPIRXDATA);
767 #define MX21_INTREG_RR (1 << 4)
768 #define MX21_INTREG_TEEN (1 << 9)
769 #define MX21_INTREG_RREN (1 << 13)
771 #define MX21_CSPICTRL_POL (1 << 5)
772 #define MX21_CSPICTRL_PHA (1 << 6)
773 #define MX21_CSPICTRL_SSPOL (1 << 8)
774 #define MX21_CSPICTRL_XCH (1 << 9)
775 #define MX21_CSPICTRL_ENABLE (1 << 10)
776 #define MX21_CSPICTRL_MASTER (1 << 11)
777 #define MX21_CSPICTRL_DR_SHIFT 14
778 #define MX21_CSPICTRL_CS_SHIFT 19
780 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
782 unsigned int val = 0;
784 if (enable & MXC_INT_TE)
785 val |= MX21_INTREG_TEEN;
786 if (enable & MXC_INT_RR)
787 val |= MX21_INTREG_RREN;
789 writel(val, spi_imx->base + MXC_CSPIINT);
792 static void mx21_trigger(struct spi_imx_data *spi_imx)
796 reg = readl(spi_imx->base + MXC_CSPICTRL);
797 reg |= MX21_CSPICTRL_XCH;
798 writel(reg, spi_imx->base + MXC_CSPICTRL);
801 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
802 struct spi_message *msg)
807 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
808 struct spi_device *spi,
809 struct spi_transfer *t)
811 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
812 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
815 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk)
816 << MX21_CSPICTRL_DR_SHIFT;
817 spi_imx->spi_bus_clk = clk;
819 reg |= spi_imx->bits_per_word - 1;
821 if (spi->mode & SPI_CPHA)
822 reg |= MX21_CSPICTRL_PHA;
823 if (spi->mode & SPI_CPOL)
824 reg |= MX21_CSPICTRL_POL;
825 if (spi->mode & SPI_CS_HIGH)
826 reg |= MX21_CSPICTRL_SSPOL;
827 if (!gpio_is_valid(spi->cs_gpio))
828 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
830 writel(reg, spi_imx->base + MXC_CSPICTRL);
835 static int mx21_rx_available(struct spi_imx_data *spi_imx)
837 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
840 static void mx21_reset(struct spi_imx_data *spi_imx)
842 writel(1, spi_imx->base + MXC_RESET);
845 #define MX1_INTREG_RR (1 << 3)
846 #define MX1_INTREG_TEEN (1 << 8)
847 #define MX1_INTREG_RREN (1 << 11)
849 #define MX1_CSPICTRL_POL (1 << 4)
850 #define MX1_CSPICTRL_PHA (1 << 5)
851 #define MX1_CSPICTRL_XCH (1 << 8)
852 #define MX1_CSPICTRL_ENABLE (1 << 9)
853 #define MX1_CSPICTRL_MASTER (1 << 10)
854 #define MX1_CSPICTRL_DR_SHIFT 13
856 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
858 unsigned int val = 0;
860 if (enable & MXC_INT_TE)
861 val |= MX1_INTREG_TEEN;
862 if (enable & MXC_INT_RR)
863 val |= MX1_INTREG_RREN;
865 writel(val, spi_imx->base + MXC_CSPIINT);
868 static void mx1_trigger(struct spi_imx_data *spi_imx)
872 reg = readl(spi_imx->base + MXC_CSPICTRL);
873 reg |= MX1_CSPICTRL_XCH;
874 writel(reg, spi_imx->base + MXC_CSPICTRL);
877 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
878 struct spi_message *msg)
883 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
884 struct spi_device *spi,
885 struct spi_transfer *t)
887 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
890 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
891 MX1_CSPICTRL_DR_SHIFT;
892 spi_imx->spi_bus_clk = clk;
894 reg |= spi_imx->bits_per_word - 1;
896 if (spi->mode & SPI_CPHA)
897 reg |= MX1_CSPICTRL_PHA;
898 if (spi->mode & SPI_CPOL)
899 reg |= MX1_CSPICTRL_POL;
901 writel(reg, spi_imx->base + MXC_CSPICTRL);
906 static int mx1_rx_available(struct spi_imx_data *spi_imx)
908 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
911 static void mx1_reset(struct spi_imx_data *spi_imx)
913 writel(1, spi_imx->base + MXC_RESET);
916 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
917 .intctrl = mx1_intctrl,
918 .prepare_message = mx1_prepare_message,
919 .prepare_transfer = mx1_prepare_transfer,
920 .trigger = mx1_trigger,
921 .rx_available = mx1_rx_available,
924 .has_dmamode = false,
925 .dynamic_burst = false,
926 .has_slavemode = false,
927 .devtype = IMX1_CSPI,
930 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
931 .intctrl = mx21_intctrl,
932 .prepare_message = mx21_prepare_message,
933 .prepare_transfer = mx21_prepare_transfer,
934 .trigger = mx21_trigger,
935 .rx_available = mx21_rx_available,
938 .has_dmamode = false,
939 .dynamic_burst = false,
940 .has_slavemode = false,
941 .devtype = IMX21_CSPI,
944 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
945 /* i.mx27 cspi shares the functions with i.mx21 one */
946 .intctrl = mx21_intctrl,
947 .prepare_message = mx21_prepare_message,
948 .prepare_transfer = mx21_prepare_transfer,
949 .trigger = mx21_trigger,
950 .rx_available = mx21_rx_available,
953 .has_dmamode = false,
954 .dynamic_burst = false,
955 .has_slavemode = false,
956 .devtype = IMX27_CSPI,
959 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
960 .intctrl = mx31_intctrl,
961 .prepare_message = mx31_prepare_message,
962 .prepare_transfer = mx31_prepare_transfer,
963 .trigger = mx31_trigger,
964 .rx_available = mx31_rx_available,
967 .has_dmamode = false,
968 .dynamic_burst = false,
969 .has_slavemode = false,
970 .devtype = IMX31_CSPI,
973 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
974 /* i.mx35 and later cspi shares the functions with i.mx31 one */
975 .intctrl = mx31_intctrl,
976 .prepare_message = mx31_prepare_message,
977 .prepare_transfer = mx31_prepare_transfer,
978 .trigger = mx31_trigger,
979 .rx_available = mx31_rx_available,
983 .dynamic_burst = false,
984 .has_slavemode = false,
985 .devtype = IMX35_CSPI,
988 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
989 .intctrl = mx51_ecspi_intctrl,
990 .prepare_message = mx51_ecspi_prepare_message,
991 .prepare_transfer = mx51_ecspi_prepare_transfer,
992 .trigger = mx51_ecspi_trigger,
993 .rx_available = mx51_ecspi_rx_available,
994 .reset = mx51_ecspi_reset,
995 .setup_wml = mx51_setup_wml,
996 .disable_dma = mx51_disable_dma,
999 .dynamic_burst = true,
1000 .has_slavemode = true,
1001 .disable = mx51_ecspi_disable,
1002 .devtype = IMX51_ECSPI,
1005 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1006 .intctrl = mx51_ecspi_intctrl,
1007 .prepare_message = mx51_ecspi_prepare_message,
1008 .prepare_transfer = mx51_ecspi_prepare_transfer,
1009 .trigger = mx51_ecspi_trigger,
1010 .rx_available = mx51_ecspi_rx_available,
1011 .disable_dma = mx51_disable_dma,
1012 .reset = mx51_ecspi_reset,
1014 .has_dmamode = true,
1015 .has_slavemode = true,
1016 .disable = mx51_ecspi_disable,
1017 .devtype = IMX53_ECSPI,
1020 static const struct platform_device_id spi_imx_devtype[] = {
1022 .name = "imx1-cspi",
1023 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1025 .name = "imx21-cspi",
1026 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1028 .name = "imx27-cspi",
1029 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1031 .name = "imx31-cspi",
1032 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1034 .name = "imx35-cspi",
1035 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1037 .name = "imx51-ecspi",
1038 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1040 .name = "imx53-ecspi",
1041 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1047 static const struct of_device_id spi_imx_dt_ids[] = {
1048 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1049 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1050 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1051 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1052 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1053 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1054 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1057 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1059 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
1061 int active = is_active != BITBANG_CS_INACTIVE;
1062 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
1064 if (spi->mode & SPI_NO_CS)
1067 if (!gpio_is_valid(spi->cs_gpio))
1070 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1073 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1077 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1078 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1079 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1080 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1083 static void spi_imx_push(struct spi_imx_data *spi_imx)
1085 unsigned int burst_len, fifo_words;
1087 if (spi_imx->dynamic_burst)
1090 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1092 * Reload the FIFO when the remaining bytes to be transferred in the
1093 * current burst is 0. This only applies when bits_per_word is a
1096 if (!spi_imx->remainder) {
1097 if (spi_imx->dynamic_burst) {
1099 /* We need to deal unaligned data first */
1100 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1103 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1105 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1107 spi_imx->remainder = burst_len;
1109 spi_imx->remainder = fifo_words;
1113 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1114 if (!spi_imx->count)
1116 if (spi_imx->dynamic_burst &&
1117 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1120 spi_imx->tx(spi_imx);
1124 if (!spi_imx->slave_mode)
1125 spi_imx->devtype_data->trigger(spi_imx);
1128 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1130 struct spi_imx_data *spi_imx = dev_id;
1132 while (spi_imx->txfifo &&
1133 spi_imx->devtype_data->rx_available(spi_imx)) {
1134 spi_imx->rx(spi_imx);
1138 if (spi_imx->count) {
1139 spi_imx_push(spi_imx);
1143 if (spi_imx->txfifo) {
1144 /* No data left to push, but still waiting for rx data,
1145 * enable receive data available interrupt.
1147 spi_imx->devtype_data->intctrl(
1148 spi_imx, MXC_INT_RR);
1152 spi_imx->devtype_data->intctrl(spi_imx, 0);
1153 complete(&spi_imx->xfer_done);
1158 static int spi_imx_dma_configure(struct spi_master *master)
1161 enum dma_slave_buswidth buswidth;
1162 struct dma_slave_config rx = {}, tx = {};
1163 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1165 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1167 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1170 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1173 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1179 tx.direction = DMA_MEM_TO_DEV;
1180 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1181 tx.dst_addr_width = buswidth;
1182 tx.dst_maxburst = spi_imx->wml;
1183 ret = dmaengine_slave_config(master->dma_tx, &tx);
1185 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1189 rx.direction = DMA_DEV_TO_MEM;
1190 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1191 rx.src_addr_width = buswidth;
1192 rx.src_maxburst = spi_imx->wml;
1193 ret = dmaengine_slave_config(master->dma_rx, &rx);
1195 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1202 static int spi_imx_setupxfer(struct spi_device *spi,
1203 struct spi_transfer *t)
1205 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1210 spi_imx->bits_per_word = t->bits_per_word;
1213 * Initialize the functions for transfer. To transfer non byte-aligned
1214 * words, we have to use multiple word-size bursts, we can't use
1215 * dynamic_burst in that case.
1217 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1218 (spi_imx->bits_per_word == 8 ||
1219 spi_imx->bits_per_word == 16 ||
1220 spi_imx->bits_per_word == 32)) {
1222 spi_imx->rx = spi_imx_buf_rx_swap;
1223 spi_imx->tx = spi_imx_buf_tx_swap;
1224 spi_imx->dynamic_burst = 1;
1227 if (spi_imx->bits_per_word <= 8) {
1228 spi_imx->rx = spi_imx_buf_rx_u8;
1229 spi_imx->tx = spi_imx_buf_tx_u8;
1230 } else if (spi_imx->bits_per_word <= 16) {
1231 spi_imx->rx = spi_imx_buf_rx_u16;
1232 spi_imx->tx = spi_imx_buf_tx_u16;
1234 spi_imx->rx = spi_imx_buf_rx_u32;
1235 spi_imx->tx = spi_imx_buf_tx_u32;
1237 spi_imx->dynamic_burst = 0;
1240 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1241 spi_imx->usedma = true;
1243 spi_imx->usedma = false;
1245 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1246 spi_imx->rx = mx53_ecspi_rx_slave;
1247 spi_imx->tx = mx53_ecspi_tx_slave;
1248 spi_imx->slave_burst = t->len;
1251 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
1256 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1258 struct spi_master *master = spi_imx->bitbang.master;
1260 if (master->dma_rx) {
1261 dma_release_channel(master->dma_rx);
1262 master->dma_rx = NULL;
1265 if (master->dma_tx) {
1266 dma_release_channel(master->dma_tx);
1267 master->dma_tx = NULL;
1271 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1272 struct spi_master *master)
1276 /* use pio mode for i.mx6dl chip TKT238285 */
1277 if (of_machine_is_compatible("fsl,imx6dl"))
1280 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1282 /* Prepare for TX DMA: */
1283 master->dma_tx = dma_request_chan(dev, "tx");
1284 if (IS_ERR(master->dma_tx)) {
1285 ret = PTR_ERR(master->dma_tx);
1286 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1287 master->dma_tx = NULL;
1291 /* Prepare for RX : */
1292 master->dma_rx = dma_request_chan(dev, "rx");
1293 if (IS_ERR(master->dma_rx)) {
1294 ret = PTR_ERR(master->dma_rx);
1295 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1296 master->dma_rx = NULL;
1300 init_completion(&spi_imx->dma_rx_completion);
1301 init_completion(&spi_imx->dma_tx_completion);
1302 master->can_dma = spi_imx_can_dma;
1303 master->max_dma_len = MAX_SDMA_BD_BYTES;
1304 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1309 spi_imx_sdma_exit(spi_imx);
1313 static void spi_imx_dma_rx_callback(void *cookie)
1315 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1317 complete(&spi_imx->dma_rx_completion);
1320 static void spi_imx_dma_tx_callback(void *cookie)
1322 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1324 complete(&spi_imx->dma_tx_completion);
1327 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1329 unsigned long timeout = 0;
1331 /* Time with actual data transfer and CS change delay related to HW */
1332 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1334 /* Add extra second for scheduler related activities */
1337 /* Double calculated timeout */
1338 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1341 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1342 struct spi_transfer *transfer)
1344 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1345 unsigned long transfer_timeout;
1346 unsigned long timeout;
1347 struct spi_master *master = spi_imx->bitbang.master;
1348 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1349 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1350 unsigned int bytes_per_word, i;
1353 /* Get the right burst length from the last sg to ensure no tail data */
1354 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1355 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1356 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1359 /* Use 1 as wml in case no available burst length got */
1365 ret = spi_imx_dma_configure(master);
1369 if (!spi_imx->devtype_data->setup_wml) {
1370 dev_err(spi_imx->dev, "No setup_wml()?\n");
1373 spi_imx->devtype_data->setup_wml(spi_imx);
1376 * The TX DMA setup starts the transfer, so make sure RX is configured
1379 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1380 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1381 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1385 desc_rx->callback = spi_imx_dma_rx_callback;
1386 desc_rx->callback_param = (void *)spi_imx;
1387 dmaengine_submit(desc_rx);
1388 reinit_completion(&spi_imx->dma_rx_completion);
1389 dma_async_issue_pending(master->dma_rx);
1391 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1392 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1393 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1395 dmaengine_terminate_all(master->dma_tx);
1396 dmaengine_terminate_all(master->dma_rx);
1400 desc_tx->callback = spi_imx_dma_tx_callback;
1401 desc_tx->callback_param = (void *)spi_imx;
1402 dmaengine_submit(desc_tx);
1403 reinit_completion(&spi_imx->dma_tx_completion);
1404 dma_async_issue_pending(master->dma_tx);
1406 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1408 /* Wait SDMA to finish the data transfer.*/
1409 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1412 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1413 dmaengine_terminate_all(master->dma_tx);
1414 dmaengine_terminate_all(master->dma_rx);
1418 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1421 dev_err(&master->dev, "I/O Error in DMA RX\n");
1422 spi_imx->devtype_data->reset(spi_imx);
1423 dmaengine_terminate_all(master->dma_rx);
1427 return transfer->len;
1430 static int spi_imx_pio_transfer(struct spi_device *spi,
1431 struct spi_transfer *transfer)
1433 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1434 unsigned long transfer_timeout;
1435 unsigned long timeout;
1437 spi_imx->tx_buf = transfer->tx_buf;
1438 spi_imx->rx_buf = transfer->rx_buf;
1439 spi_imx->count = transfer->len;
1440 spi_imx->txfifo = 0;
1441 spi_imx->remainder = 0;
1443 reinit_completion(&spi_imx->xfer_done);
1445 spi_imx_push(spi_imx);
1447 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1449 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1451 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1454 dev_err(&spi->dev, "I/O Error in PIO\n");
1455 spi_imx->devtype_data->reset(spi_imx);
1459 return transfer->len;
1462 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1463 struct spi_transfer *transfer)
1465 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1466 int ret = transfer->len;
1468 if (is_imx53_ecspi(spi_imx) &&
1469 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1470 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1471 MX53_MAX_TRANSFER_BYTES);
1475 spi_imx->tx_buf = transfer->tx_buf;
1476 spi_imx->rx_buf = transfer->rx_buf;
1477 spi_imx->count = transfer->len;
1478 spi_imx->txfifo = 0;
1479 spi_imx->remainder = 0;
1481 reinit_completion(&spi_imx->xfer_done);
1482 spi_imx->slave_aborted = false;
1484 spi_imx_push(spi_imx);
1486 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1488 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1489 spi_imx->slave_aborted) {
1490 dev_dbg(&spi->dev, "interrupted\n");
1494 /* ecspi has a HW issue when works in Slave mode,
1495 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1496 * ECSPI_TXDATA keeps shift out the last word data,
1497 * so we have to disable ECSPI when in slave mode after the
1498 * transfer completes
1500 if (spi_imx->devtype_data->disable)
1501 spi_imx->devtype_data->disable(spi_imx);
1506 static int spi_imx_transfer(struct spi_device *spi,
1507 struct spi_transfer *transfer)
1509 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1512 /* flush rxfifo before transfer */
1513 while (spi_imx->devtype_data->rx_available(spi_imx))
1514 readl(spi_imx->base + MXC_CSPIRXDATA);
1516 if (spi_imx->slave_mode)
1517 return spi_imx_pio_transfer_slave(spi, transfer);
1520 * fallback PIO mode if dma setup error happen, for example sdma
1521 * firmware may not be updated as ERR009165 required.
1523 if (spi_imx->usedma) {
1524 ret = spi_imx_dma_transfer(spi_imx, transfer);
1528 spi_imx->devtype_data->disable_dma(spi_imx);
1530 spi_imx->usedma = false;
1531 spi_imx->dynamic_burst = spi_imx->devtype_data->dynamic_burst;
1532 dev_dbg(&spi->dev, "Fallback to PIO mode\n");
1535 return spi_imx_pio_transfer(spi, transfer);
1538 static int spi_imx_setup(struct spi_device *spi)
1540 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1541 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1543 if (spi->mode & SPI_NO_CS)
1546 if (gpio_is_valid(spi->cs_gpio))
1547 gpio_direction_output(spi->cs_gpio,
1548 spi->mode & SPI_CS_HIGH ? 0 : 1);
1550 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1555 static void spi_imx_cleanup(struct spi_device *spi)
1560 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1562 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1565 ret = clk_enable(spi_imx->clk_per);
1569 ret = clk_enable(spi_imx->clk_ipg);
1571 clk_disable(spi_imx->clk_per);
1575 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1577 clk_disable(spi_imx->clk_ipg);
1578 clk_disable(spi_imx->clk_per);
1585 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1587 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1589 clk_disable(spi_imx->clk_ipg);
1590 clk_disable(spi_imx->clk_per);
1594 static int spi_imx_slave_abort(struct spi_master *master)
1596 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1598 spi_imx->slave_aborted = true;
1599 complete(&spi_imx->xfer_done);
1604 static int spi_imx_probe(struct platform_device *pdev)
1606 struct device_node *np = pdev->dev.of_node;
1607 const struct of_device_id *of_id =
1608 of_match_device(spi_imx_dt_ids, &pdev->dev);
1609 struct spi_imx_master *mxc_platform_info =
1610 dev_get_platdata(&pdev->dev);
1611 struct spi_master *master;
1612 struct spi_imx_data *spi_imx;
1613 struct resource *res;
1614 int i, ret, irq, spi_drctl;
1615 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1616 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1619 if (!np && !mxc_platform_info) {
1620 dev_err(&pdev->dev, "can't get the platform data\n");
1624 slave_mode = devtype_data->has_slavemode &&
1625 of_property_read_bool(np, "spi-slave");
1627 master = spi_alloc_slave(&pdev->dev,
1628 sizeof(struct spi_imx_data));
1630 master = spi_alloc_master(&pdev->dev,
1631 sizeof(struct spi_imx_data));
1635 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1636 if ((ret < 0) || (spi_drctl >= 0x3)) {
1637 /* '11' is reserved */
1641 platform_set_drvdata(pdev, master);
1643 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1644 master->bus_num = np ? -1 : pdev->id;
1646 spi_imx = spi_master_get_devdata(master);
1647 spi_imx->bitbang.master = master;
1648 spi_imx->dev = &pdev->dev;
1649 spi_imx->slave_mode = slave_mode;
1651 spi_imx->devtype_data = devtype_data;
1653 /* Get number of chip selects, either platform data or OF */
1654 if (mxc_platform_info) {
1655 master->num_chipselect = mxc_platform_info->num_chipselect;
1656 if (mxc_platform_info->chipselect) {
1657 master->cs_gpios = devm_kcalloc(&master->dev,
1658 master->num_chipselect, sizeof(int),
1660 if (!master->cs_gpios)
1663 for (i = 0; i < master->num_chipselect; i++)
1664 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1669 if (!of_property_read_u32(np, "num-cs", &num_cs))
1670 master->num_chipselect = num_cs;
1671 /* If not preset, default value of 1 is used */
1674 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1675 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1676 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1677 spi_imx->bitbang.master->setup = spi_imx_setup;
1678 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1679 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1680 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1681 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1682 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1684 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1685 is_imx53_ecspi(spi_imx))
1686 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1688 spi_imx->spi_drctl = spi_drctl;
1690 init_completion(&spi_imx->xfer_done);
1692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1693 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1694 if (IS_ERR(spi_imx->base)) {
1695 ret = PTR_ERR(spi_imx->base);
1696 goto out_master_put;
1698 spi_imx->base_phys = res->start;
1700 irq = platform_get_irq(pdev, 0);
1703 goto out_master_put;
1706 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1707 dev_name(&pdev->dev), spi_imx);
1709 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1710 goto out_master_put;
1713 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1714 if (IS_ERR(spi_imx->clk_ipg)) {
1715 ret = PTR_ERR(spi_imx->clk_ipg);
1716 goto out_master_put;
1719 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1720 if (IS_ERR(spi_imx->clk_per)) {
1721 ret = PTR_ERR(spi_imx->clk_per);
1722 goto out_master_put;
1725 ret = clk_prepare_enable(spi_imx->clk_per);
1727 goto out_master_put;
1729 ret = clk_prepare_enable(spi_imx->clk_ipg);
1733 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1735 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1736 * if validated on other chips.
1738 if (spi_imx->devtype_data->has_dmamode) {
1739 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1740 if (ret == -EPROBE_DEFER)
1744 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1748 spi_imx->devtype_data->reset(spi_imx);
1750 spi_imx->devtype_data->intctrl(spi_imx, 0);
1752 master->dev.of_node = pdev->dev.of_node;
1753 ret = spi_bitbang_start(&spi_imx->bitbang);
1755 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1759 /* Request GPIO CS lines, if any */
1760 if (!spi_imx->slave_mode && master->cs_gpios) {
1761 for (i = 0; i < master->num_chipselect; i++) {
1762 if (!gpio_is_valid(master->cs_gpios[i]))
1765 ret = devm_gpio_request(&pdev->dev,
1766 master->cs_gpios[i],
1769 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1770 master->cs_gpios[i]);
1771 goto out_spi_bitbang;
1776 dev_info(&pdev->dev, "probed\n");
1778 clk_disable(spi_imx->clk_ipg);
1779 clk_disable(spi_imx->clk_per);
1783 spi_bitbang_stop(&spi_imx->bitbang);
1785 clk_disable_unprepare(spi_imx->clk_ipg);
1787 clk_disable_unprepare(spi_imx->clk_per);
1789 spi_master_put(master);
1794 static int spi_imx_remove(struct platform_device *pdev)
1796 struct spi_master *master = platform_get_drvdata(pdev);
1797 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1800 spi_bitbang_stop(&spi_imx->bitbang);
1802 ret = clk_enable(spi_imx->clk_per);
1806 ret = clk_enable(spi_imx->clk_ipg);
1808 clk_disable(spi_imx->clk_per);
1812 writel(0, spi_imx->base + MXC_CSPICTRL);
1813 clk_disable_unprepare(spi_imx->clk_ipg);
1814 clk_disable_unprepare(spi_imx->clk_per);
1815 spi_imx_sdma_exit(spi_imx);
1816 spi_master_put(master);
1821 static struct platform_driver spi_imx_driver = {
1823 .name = DRIVER_NAME,
1824 .of_match_table = spi_imx_dt_ids,
1826 .id_table = spi_imx_devtype,
1827 .probe = spi_imx_probe,
1828 .remove = spi_imx_remove,
1830 module_platform_driver(spi_imx_driver);
1832 MODULE_DESCRIPTION("SPI Controller driver");
1833 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1834 MODULE_LICENSE("GPL");
1835 MODULE_ALIAS("platform:" DRIVER_NAME);